A Script-Based Cycle-True Verification Framework to Speed-Up Hardware and Software Co-Design: Performance Evaluation on ECC Accelerator Use-Case

Round 1

Reviewer 1 Report

The paper is well writen and only some minor changes are requiered.

1. Some fonts of more figures must be incresed

2. Comparison with other similar methods is required 

Author Response

Thank you for your precious and valuable review. I hope the revised manuscript satisfies your requests.

Author Response File: Author Response.pdf

Reviewer 2 Report

The Conway-Mead revolution in Microelectronic Chip Design has opened Design Automation to Software Compiler Techniques. This has created the concept of the ToolBag, mechanized by Makefile Technology. The resulting strategy is called Hardware Compilation, and has been popularized in the Gajski Y-Chart. In the academic world, this has caused a lot of confusion: are Hardware (HW) and Software (SW) two fully different disciplines or are they just aspects of the same reality? The feud still lives on.

 

The proposed paper documents the outgrowth of the 1990’ concept to the current multi-dimensional potential. Classic HW present a small number of design software packages, each to be handled by an expert after considerable education at that design level. The compiler version provides a multitude of design steps. Here the single designer selects a mix of compiled experts to keep total control over the design. The expectation is that the former excels in all detail while the latter gives a much better composition.

 

The proposed paper goes into the full detail of the toolbag. Unfortunately, the authors touch only lightly on the underlying philosophy. Hence, it seems that the hardware compilation requires many experts because of the many tools in the bag. It is worth to emphasize that it rather brings the knowledge of many experts to the benefit of the single architect. The facts are present in the text but they could be presented on a single golden platter.

 

For the same reason am I missing the tool charts. Many tools can be present in a bag, but a meaningful collection stresses added value (or over completeness). The glue is the target strategy, with questions such as: how much is required for efficiency as in principle more tools can be less. Such a discussion will support the benefits of Makefile, the real motor of HW compilation.

 

It is clear that a journal publication forces to material selection. Such a selection will be based on the message that will be conveyed to the readership. Just by looking at the title, my first impression is that no main subject has been selected. Consequently, there is no single reason for reading the manuscript that emerges from the text. The principle of Hardware Compilation comes already from the early ‘90s. Therefore, I expect a good reason for publishing a HC paper or the text must clearly say that its main virtue is the documentation of the author’s version.

 

So, I suggest to the authors to go once more through the presentation and giving it some more anchoring. Overall I am reasonable happy.

Author Response

Thank you for your precious and detailed revision.

Author Response File: Author Response.pdf

Reviewer 3 Report

1.  The quantitative performance must be included in the abstract. 

2. It would be good to provide github for further evaluation.

3. There is not comparison with the commercially available design flow.

4. Formatting: please check Table 1 caption, and the font size.

5. It is not clear what are the conclusion for Figure 14, and Figure 15. The only show case of the tool. Is it only on the power aspect? 

6. The only reported performance advantage is 30 min setup, which may depend on the user experience. The performance should emphasis on how the tool help in reduce the design cycles, more optimized area, power, speed, etc.  

Author Response

Thank you for your valuable revision. I hope the revised manuscript satisfies your requests. We will soon publish our work on GitHub as you suggested.

Author Response File: Author Response.pdf