Reduced-Cost Optimization-Based Miniaturization of Microwave Passives by Multi-Resolution EM Simulations for Internet of Things and Space-Limited Applications

Abstract

Stringent performance specifications along with constraints imposed on physical dimensions make the design of contemporary microwave components a truly onerous task. In recent years, the latter demand has been growing in importance with the innovative application of areas such as the Internet of Things coming into play. The need to employ full-wave electromagnetic (EM) simulations for response evaluation, reliable, yet CPU-heavy, only aggravates the issue. This paper proposes a reduced-cost miniaturization algorithm that employs a trust-region search procedure and multi-resolution EM simulations. In our approach, the resolution of the EM model is adjusted throughout the optimization process based on its convergence status starting from the lowest admissible fidelity. As the algorithm converges, the resolution is increased up to the high-fidelity one, used at the final phase to ensure reliability. Four microwave components have been utilized as verification structures: an impedance matching transformer and three branch-line couplers. Significant savings in terms of the number of EM analyses required to conclude the size reduction process of 41, 42, 38 and 50 percent have been obtained (in comparison to a single-fidelity procedure). The footprint area of the designs optimized using the proposed approach are equal to 32, 205, 410 and 132 mm², in comparison to 52, 275, 525 and 213 mm² of the initial (and already compact) design.

1. Introduction

Nowadays, the design of microwave components has become an intricate process that has to satisfy stringent performance requirements, but must also enable the implementation of additional functionalities. Performance specifications pertinent to electrical characteristics of the circuit are typically related to operating frequency and/or frequencies (in the case of multi-band structures), bandwidth, power split ratio, insertion loss levels, allocation of transmission zeros, etc. [1,2,3]. Additional functionalities may include multi-band operation [4,5], tunability [6] or harmonic suppression [7]. Meeting these requirements can be even more challenging due to growing demands for compact size [8,9], which is imperative for emerging applications (e.g., 5G communications [10], Internet of Things (IoT) [11], energy harvesting [12] or sensors [13]). Various methods for miniaturization of microwave components have evolved, including topological modifications, such as transmission line folding [14], employment of compact microstrip resonant cells using the slow-wave phenomenon [15], defected ground structures [16] and high-permittivity substrates [17]. Consequently, compact microwave structures usually feature intricate geometries characterized by large numbers of geometry parameters, simultaneous adjustment of which is indispensable to ascertain the component′s best achievable performance. This, in turn, is of paramount importance, especially for cutting-edge technologies (5G/6G, Internet of Things).

In practice, the tuning process must be executed with the use of full-wave electromagnetic (EM) simulation tools. The employment of EM analysis for the design of compact components is necessary to represent EM cross-coupling effects in tightly packed layouts of miniaturized circuits [18], the effects of environmental components (e.g., connectors) [19], or simply because equivalent network models are grossly inaccurate in characterizing topologically involved structures. On the other hand, rigorous numerical optimization using EM simulations tends to be CPU-heavy. Nevertheless, it is the only approach allowing for the efficient handling of a number of performance figures (e.g., return loss, bandwidth or operating frequency/frequencies), and, at the same time, ensuring control over the physical size of the circuit under study. As the design objectives typically stay in conflict, in practice, the obtained designs constitute trade-offs between the considered performance figures. From a numerical perspective, miniaturization tasks are constrained problems with the constraints being expensive to evaluate. Handling such optimization tasks is numerically demanding, as designs featuring minimum size normally reside at the feasible region boundary. The aforementioned factors make simulation-based miniaturization of microwave components challenging.

The high cost of EM-driven optimization of microwave components, including size-reduction-oriented tasks, is troublesome both in the case of local [20,21,22] and global search [23], especially when using population-based metaheuristics [24,25,26]. Among the techniques designed for streamlining local gradient-based search algorithms, adjoint sensitivities [27,28] and sparse sensitivity updates [29,30,31] may be listed. A completely different strategy is fostered by surrogate-assisted schemes. The surrogate (or a metamodel) is a faster, yet accurate representation of the component under design. There are two kinds of surrogates: physics-based [32] and data-driven [33]. The former involves a low-fidelity representation of the system, e.g., an equivalent circuit. The low-fidelity model is corrected to improve its misalignment with the high-fidelity (EM) model. Representative techniques of this class are space mapping [34], feature-based optimization [35,36] or adaptive response scaling [37]. The second group of surrogates is more generic, as their construction does not require any problem-specific knowledge. The popularity of data-driven models comes from an easy access and versatility (mainly via third-party Matlab toolboxes of many kinds, e.g., SUMO [38], DACE [39], UQlab [40]). Multiple modelling techniques are available, including kriging [41], radial basis functions (RBF) [42], Gaussian process regression [43], support vector regression [44] or neural networks [45,46,47,48]. Still, their applicability is limited by the curse of dimensionality. Setting up reliable surrogates for contemporary microwave devices of intricate topologies and featuring a large number of variables is hardly possible, particularly if the model has to cover broad ranges of operating and geometry parameters (which is imperative from the standpoint of design usability of the model).

This paper proposes an efficient and reliable algorithm for simulation-driven miniaturization of compact microwave components. Our methodology employs multi-fidelity EM simulations selected over a specified range of allowable resolutions: from the minimal (still ensuring satisfactory accuracy) to the high-fidelity model [49]. In addition, the formulation of the design task permits an efficient treatment of design constraints while directly handling size reduction of the structure under design. The entire procedure is embedded into a trust-region gradient-based framework. During the optimization process, the model discretization level is set contingent upon the algorithm convergence status. Adopting the aforementioned mechanisms permits sizeable computational savings without degrading the process reliability. The proposed technique has been employed to miniaturize four compact microwave components: a three-section impedance matching transformer, as well as three branch-line couplers, and is compared to single-fidelity trust-region gradient-based algorithm. The computational cost has been reduced by nearly 50 percent.

The proposed approach enables a rapid rendition of minimum-size microwave components. By means of simultaneous adjustment of all geometry parameters, it allows for additional miniaturization beyond what is possible by pure topology selection of the circuit. Short running time and generality of the presented algorithm make it useful for yielding top-quality structures and to reduce circuit development time, both being of paramount importance for academic research and even more for industry, particularly, in the context of rapidly growing areas including, e.g., the Internet of Things.

The novelty and the technical contributions of the work under review include: (i) development of an algorithm for direct optimization-based miniaturization of microwave components with multi-fidelity EM simulations, (ii) implementation of the size reduction algorithm integrating local gradient-based search with automated adjustment of the model discretization level and (iii) demonstrating a significant speedup of the search process with only a minor increase in the device footprint area with respect to the reference procedure.

2. Miniaturization of Microwave Passives by Multi-Fidelity Simulations

This section describes the proposed miniaturization procedure with multi-resolution EM simulations. The section begins with a formulation of optimization-based miniaturization of microwave passives (Section 2.1). Section 2.2 recalls the standard trust-region algorithm employed in this work as a search engine. The delineation of the multi-fidelity model adjustment scheme and the entire miniaturization framework in Section 2.3 and Section 2.4, respectively, concludes this part of the manuscript.

2.1. Problem Formulation

Nowadays, the design of compact microwave components is more often than not performed through rigorous numerical optimization. Circuit miniaturization is no exception here. In this work, the size reduction task is tackled by solving

$${\mathit{x}}^{*}=\arg \underset{\mathit{x}}{\min }U(\mathit{x}),$$

(1)

which may also be subject to the inequality constraints g_k(x) ≤ 0, k = 1, …, n_g, as well as equality constraints h_k(x) = 0, k = 1, …, n_h. In (1), U is the scalar objective function quantifying the design quality, and x denotes the vector of design variables. For size reduction, U(x) = A(x), with A being the circuit size. Here, we adopt a penalty approach [50], in which the constraints are dealt with in an implicit manner. Thus, the reformulated objective function U_P is employed, which accounts for the primary objective (here, the component′s footprint) and other requirements. We have

$${\mathit{x}}^{*}=\arg \underset{\mathit{x}}{\min }{U}_P(\mathit{x}),$$

(2)

where the function U_P is defined as follows

$$U_P(\mathit{x})=U(\mathit{x})+{\displaystyle {\sum }_{k=1}^{n_g+n_h}{\beta }_k{c}_k(\mathit{x})}$$

(3)

with c_k(x), k = 1, …, n_g + n_h, representing the penalty functions that quantify constraint violations, whereas β_k denotes the penalty coefficients. In (3), the primary objective (size reduction) is supplemented by the contributions proportional to suitably quantified constraint violations. The coefficients β_k are typically set up based on designer’s experience on a case-to-case basis.

2.2. Search Engine: Trust-Region Local Search

This section recalls the standard trust-region (TR) algorithm [51], which is exploited here as a search engine. The TR algorithm iteratively yields a series of approximations x⁽ⁱ⁾, i = 0, 1, …, to x^* (i.e., the optimal solution), where x⁽⁰⁾ denotes the initial design. Each consecutive vector x⁽ⁱ⁾ is established by solving

$${\mathit{x}}^{(i+1)}=\arg \underset{\mathit{x};\hspace{0.33em}-d^{(i)}\le \mathit{x}-{\mathit{x}}^{(i)}\le d^{(i)}}{\min }{U}_L^{(i)}(\mathit{x}),$$

(4)

where U_L⁽ⁱ⁾ is defined as U_P, but with linear model L⁽ⁱ⁾ of the circuit response R(x). Our principal objective is to reduce the circuit size A(x), which can be evaluated analytically based on the parameter vector x. Thus, there is no need to use the linear model to assess it. Still, when calculating the constraints, the linear expansion model L⁽ⁱ⁾ = R(x⁽ⁱ⁾) + J_R(x⁽ⁱ⁾)·(x − x⁽ⁱ⁾) needs to be employed.

2.3. Model Fidelity Arrangement

Our algorithm exploits multi-fidelity model simulations to expedite miniaturization of microwave passives. Although variable-fidelity frameworks have been employed in antenna [52] and microwave design [53], they typically utilize two levels of resolution: low- and high-fidelity models. Here, we follow the concept introduced in [49], where a continuous range of resolution levels is exploited, delimited by two boundary levels: the lowest one that is still practically useful and the one corresponding to the high-fidelity model. The actual selection of the two levels is of paramount importance. The lowest resolution r_min has to ensure adequate accuracy of the associated model while offering sufficient computational savings, whereas the highest resolution r_max needs to provide an accurate representation of the system outputs.

The model fidelity arrangement utilized in this work is based on the following suppositions: (i) the procedure is initiated with r_min (for the sake of computational savings); (ii) in the consecutive iterations, the resolution r is increased step-by-step, contingent upon the convergence status of the optimization procedure; and (iii) close to the termination, r_max is enforced (for the sake of reliability).

The following factor assessing the convergence status is defined as

$$Q^{(i)}({\epsilon }_x,{\epsilon }_U)=\max \left\{\frac{{\epsilon }_x}{\left|\right|{\mathit{x}}^{(i+1)}-{\mathit{x}}^{(i)}\left|\right|},\frac{{\epsilon }_U}{|U_P({\mathit{x}}^{(i+1)})-U_P({\mathit{x}}^{(i)})|}\right\}$$

(5)

with ε_x and ε_U referring to the user-defined termination thresholds. The optimization procedure has reached convergence if the following holds: ||x⁽ⁱ⁺¹⁾ − x⁽ⁱ⁾|| < ε_x (the design shift between iterations is small) OR ||d⁽ⁱ⁾|| < ε_x (the TR size is sufficiently reduced) OR |U_P(x⁽ⁱ⁺¹⁾) − U_P(x⁽ⁱ⁾)| < ε_U (the change of the merit function value between iterations is minor). The factor Q⁽ⁱ⁾ serves for adjusting the value of the model discretization level r⁽ⁱ⁺¹⁾ for the next algorithm iteration according to

$$r^{(i+1)}=\left\{\begin{array}{l}{r}_{\min }\hspace{0.33em}\hspace{0.33em}\mathrm{if}\hspace{0.33em}\hspace{0.33em}{Q}^{(i)}({\epsilon }_x,{\epsilon }_U)\le M\\ \max \left\{r^{(i)},r_{\min }+\left(r_{\max }-r_{\min }\right){\left[Q^{(i)}({\epsilon }_x,{\epsilon }_U)-M\right]}^{\frac{1}{\alpha }}\right\}\end{array}\right.$$

(6)

In (6), M governs the onset of the model resolution increase (with respect to the algorithm convergence) and α is a shape parameter. By setting M = 10^–2 and α = 3 (as in Section 3), the model resolution starts to increase (relatively rapidly) two decades prior to convergence, which is beneficiary for computational efficiency.

Nevertheless, Formula (6) does not guarantee that the final iterations are performed using the highest model resolution (which is mandatory from the standpoint of reliability). Thus, a safeguard mechanism must be implemented, which works as follows: in the final iteration, if r⁽ⁱ⁾ < r_max, then the termination condition is ignored. Consequently, for the next (supplemental) iteration, the model resolution is set to r⁽ⁱ⁺¹⁾ = r_max and the TR size is set as d⁽ⁱ⁺¹⁾ = M_d d⁽ⁱ⁾ ε_x/||d⁽ⁱ⁾||, where the multiplier M_d determines the increase in the TR size to ensure sufficient space for design tuning after shifting to the maximum resolution. Here, we adopt M_d = 10.

To achieve additional speedup, response gradients are evaluated at a resolution r_FD = max{r_min, λr⁽ⁱ⁾}, which is lower than the current resolution used for simulation of the model outputs. The factor λ assumes positive values below 1; in our work, we set λ = 2/3.

Given a typical time evaluation ratio between the highest- and lowest-fidelity model to be about three, one can estimate the expected reduction of the computational cost of the optimization process at a level of about fifty percent. This is because most of the operations will be performed using lower-fidelity EM simulations, yet the last few iterations executed using the high-fidelity model will contribute to perhaps half of the total cost. That half, as being spanned over 1/5 to 1/4 of the overall iteration span, allows us to estimate the total cost as being half of that corresponding to the high-fidelity only version of the algorithm. This is, clearly, a very rough estimate, which highly depends on several factors, including the said time evaluation ratio.

2.4. Miniaturization Framework

The operational flow of the optimization-based multi-fidelity miniaturization algorithm discussed here is presented in Figure 1, whereas its pseudocode is presented in Algorithm 1. The algorithm exploits two main components: the trust region algorithm of Section 2.2 and the multi-fidelity model arrangement formulated in Section 2.3. The algorithm control parameters are gathered in

Table 1. Control parameters of the proposed algorithm.

Parameter	Purpose	Default Value
rmin	Governing EM-model discretization level (minimum value)	Problem specific 1
rmax	Governing EM-model discretization level (maximum value)	Problem specific 1
M	Launching the discretization level increase	10–2
α	Adjustment of EM-simulation model resolution	3
λ	Setting discretization level for FD	2/3
Md	TR radius increase (near convergence)	10
εx, εU	Algorithm termination	10–3

¹ Established through a visual inspection of the family of circuit responses.

.

Algorithm 1: Operation of the proposed multi-fidelity size reduction algorithm.

1. Set the iteration counter i = 0, and r(i) = rmin; 2. Evaluate component response R(x(i)) at the discretization level r(i); 3. Evaluate component sensitivities JR(x(i)) at the discretization level rFD; 4. Construct a linear model $L_{}^{(i)}(x)=R(x^{(i)})+J_R(x^{(i)})\cdot (x-x^{(i)})$; 5. Obtain the design x(i+1) by solving (4); 6. Evaluate component response R(x(i+1)) at the discretization level r(i); 7. Update trust-region size vector d(i); 8. If UP(x(i+1)) < UP(x(i)),       compute r(i+1) using (6);       Set i = i + 1; end 9. If ||x(i+1) – x(i)|| < εx OR ||d(i)|| < εx OR | UP(x(i+1)) – UP(x(i))| < εU if r(i) < rmax       Set r(i) = rmax and modify d(i); go to 3; else       Go to 10; end else       Go to 3; end 10. END.

We employed CST Microwave Studio for evaluation of the computational models of the considered devices. Hence, the model discretization is parametrized by LPW (lines per wavelength), utilized in CST to govern the mesh density. The boundary resolution levels r_min and r_max were decided upon through the grid convergence studies, as presented in Section 3. The maximum resolution level r_max is the resolution increasing above, which leads to no meaningful changes of the component characteristics, whereas r_min is assessed as the lowest resolution for which the evaluated responses outputs are still adequately rendered.

3. Results

This section provides the results obtained using the introduced size-reduction algorithm with multi-resolution EM-simulations for four microwave passive devices: a three-section impedance transformer and three branch-line couplers. The design goals for the transformer are footprint minimization and in-band matching enhancement. For the couplers, we have three design objectives: (i) footprint minimization, (ii) minimization of matching and isolation and (iii) enforcement of an assumed power split (equal in the case of two couplers, and unequal for the third one).

Figure 2 shows the geometries of four microwave devices utilized here as verification case studies: a three-section impedance transformer comprising three compact microstrip resonant cell (CMRC) sections (Circuit I), a compact branch-line coupler (Circuit II), a branch-line coupler with microstrip cells (Circuit III) and a branch-line coupler with unequal power division (Circuit IV).

Table 2. Details of microwave structures used as verification cases.

	Case Study
	Circuit I	Circuit II	Circuit III	Circuit IV
Substrate	RF-35 substrate (εr = 3.5, h = 0.762 mm)	RO4003 (εr = 3.38, h = 0.76 mm)	FR4 (εr = 4.4, h = 1.0 mm)	FR4 (εr = 4.4, h = 1.0 mm)
Design parameters	x = [l1.1 l1.2 w1.1 w1.2 w1.0 l2.1 l2.2 w2.1 w2.2 w2.0 l3.1 l3.2 w3.1 w3.2 w3.0]T	x = [g l1r la lb w1 w2r w3r w4r wa wb]T	x = [G g1 g2 g3 w1 w3 L1 L2]T	x = [W w1r w2r w3 w4 L L1r L2r L3 L4 L5r s]T
Other parameters	–	L = 2dL + Ls, Ls = 4w1 + 4g + s + la + lb, W = 2dL + Ws, l1 = lbl1r, Ws = 4w1 + 4g + s + 2wa, w2 = waw2r, w3 = w3rwa, w4 = w4rwa, wc = 1.9 mm	L = 4w1 + 10w3 + + 15g3 + 2L2, W = 4w3 + 2L1 + + G + 2g1 + 2g3	w1 = w1rw2, w2 = w2r(W-2w3), l1 = L1r(L–2s–2l4), l2 = L2r(L–l1)/2, L5=L5r(L–2(W0–l4/2)–mx), mx=|l4−l3|/2+(l4+l3)/2
Operating parameters	F = [1.75 4.25] GHz	f0 = 1.5 GHz	f0 = 1.0 GHz	f0 = 2.0 GHz
Design goals
F1	Minimization of footprint area
F2	Minimization of matching |S11| within bandwidth F	Minimization of matching |S11| and isolation |S41| at f0
F3	–	Equal power split at f0: |S31| − |S21| = 0 at f0		Unequal power split at f0: |S31| − |S21| = 3 dB at f0
Objective function (cf. (3))	$U_P(x)=A+{\beta }_{}{\left(\frac{\left|S_{11}\right|+20}{20}\right)}^2$ β = 300	$U_P(x)=A+{\beta }_1{\left(\frac{\left|S_{11}\right|+20}{20}\right)}^2+{\beta }_2{\left(\frac{d_s-d_s{}_{\max }}{d_s{}_{\max }}\right)}^2$
		β1 = 10,000, β2 = 30	β1 = 1000, β2 = 30	β1 = 10,000, β2 = 100
		dsmax = 0.1	dsmax = 0.1	dsmax = 3.0
Low-fidelity model
rmin	14	16	15	16
Simulation time [s] #	80.3	130.0	215.6	188.5
High-fidelity model
rmax	28	30	28	26
Simulation time [s] #	160.4	237.4	960.3	283.6
Time evaluation ratio	2.0	1.8	4.5	1.5
Initial design	x(0) = [3.58 0.19 0.79 0.38 0.3 3.75 0.24 0.33 0.39 1.46 3.9 0.18 0.23 0.28 1.0]T	x(0) = [0.59 0.7 6.7 8.3 0.84 0.91 0.72 0.13 3.3 0.63]T	x(0) = [1.0 1.0 0.6 0.25 2.4 0.25 9.0 3.75]T	x(0) = [15.0 0.63 0.93 3.45 3.0 12.4 0.42 0.81 1.50 1.0 0.9 0.5]T

^# EM-simulations were performed on an Intel Xeon 2.1 GHz dual-core CPU with 128 GB RAM.

gathers all the necessary information pertaining to all circuits: the geometry parameters (the relative and unit-less parameters are indicated by the subscript r; the remaining ones are absolute and expressed in mm), the substrate they are implemented on, the design goals, the objective function formulation and variable-fidelity simulations setup.

Table 2 also provides the values of the penalty coefficients (cf. (3)), which determine the contribution of the penalty terms to make them commensurable to that of the main objective (here, footprint miniaturization). The said values have been set up for each verification case individually. The computational models are evaluated using the time-domain solver of CST Microwave Studio and I dependence of the simulation time on the parameter LPW is presented in Figure 3. The proposed framework utilizes the default control parameter values provided in Table 1.

Our procedure is benchmarked against the conventional single-fidelity trust-region procedure with numerical derivatives to verify the acceleration rate achieved due to the involvement of variable-resolution models, as well as to investigate possible design quality degradation. The following performance factors are taken into account: the footprint of the circuit at the optimal design, along with the computational cost of rendering it. As far as multi-fidelity algorithm is concerned, the actual model simulation times for each resolution level are assessed as the equivalent number of simulations of the highest resolution r_max.

Table 3. Numerical results.

Circuit	Algorithm	Cost 1	Cost Savings 2	Footprint Area A [mm2] 3
I	Conventional TR search	158	–	30.0
	Multi-fidelity (this work)	93	41.1	32.2
II	Conventional TR search	67	–	182.0
	Multi-fidelity (this work)	39	41.8	205.5
III	Conventional TR search	73	–	407.1
	Multi-fidelity (this work)	45	38.4	409.8
IV	Conventional TR search	152	–	143.1
	Multi-fidelity (this work)	87	50.3	131.9

¹ Number of equivalent high-fidelity EM simulations. ² Relative computational savings in percent with respect to the reference algorithm. ³ Obtained footprint area.

gathers the optimization results obtained for all circuits using the introduced algorithm and the conventional TR algorithm utilized here as a reference routine. The results comprise the expenditures of the optimization procedure expressed as the equivalent number of high-fidelity circuit analyses (evaluated using the time evaluation curves of Figure 3), along with the savings with regard to the TR search. Moreover, Table 3 provides the footprint of all the verification structures. Figure 4, Figure 5, Figure 6 and Figure 7 present the responses of the respective circuits at the initial and optimized designs, as well the evolution of circuit size throughout the algorithm runs.

Comparison of the proposed miniaturization framework based on multi-fidelity simulations with the conventional single-fidelity trust-region gradient based algorithm allows us to draw the following conclusions: our approach allows for achieving significant miniaturization rates equal to around 38, 25, 22 and 38 percent (31 percent on average) for Circuits I through IV, respectively, with respect to the initial (and already compact) structure size, whereas for the benchmark TR algorithm, we have 42, 34, 22 and 33 (33 on average). Thus, the size of the optimized designs with respect to the area of the initial design for the proposed and benchmark procedure, are comparable. In the case of Circuits I through III, the footprints of the optimal designs are only 7, 11 and 1 percent larger than those rendered by the conventional TR algorithm, whereas the area of the Circuit IV is eight percent smaller. For the sake of comparison, the footprints of the initial and optimized designs are shown in Figure 8.

The said miniaturization rates are accompanied by a considerable computational savings of around 43 percent on the average (see Table 3). This means that incorporating multi-resolution EM simulations allows for accelerating the optimization-based miniaturization process almost twice on the average at the cost of slightly degraded miniaturization rates. Measuring in absolute numbers, the average CPU cost corresponds to around sixty high-fidelity EM simulations, meaning that the typical execution time only takes around three hours.

4. Conclusions

The paper proposed a novel framework for optimization-based EM-driven size reduction of microwave circuits. Our approach exploits multi-fidelity EM simulations, which are embedded into the core gradient-based optimization algorithm. The management of the circuit discretization level during the optimization run is contingent upon its convergence status: from the lowest one, used when the procedure is launched, to the highest resolution utilized near reaching optimum. Consequently, a significant speedup of the miniaturization procedure been obtained in comparison to a single-fidelity version with similar miniaturization rates. The performance of the proposed size-reduction framework has been comprehensively verified using four microwave devices: an impedance transformer and three branch-line couplers, all optimized for a minimum size. Additionally, minimization of matching within the frequency band of interest has been carried out in the case of the transformer, whereas the couplers have been optimized for best matching and isolation. The savings, with respect to a single-fidelity procedure, have been equal to 41, 42, 38 and 50 percent, across the benchmark set. In the proposed approach, optimal designs feature truly compact sizes: 32, 205, 410 and 132 mm² (in comparison to 52, 275, 525 and 213 mm² of the initial design). It should be emphasized that size reduction of microwave components has become critical for a number of applications, including the Internet of Things. The proposed approach offers a design enhancement solution that is fast to execute, fully automated and complements traditional design methods (here, the initial development of compact circuit topology). These features make it an attractive tool, especially in an industrial context, but also in academic research.