A 130-to-220-GHz Frequency Quadrupler with 80 dB Dynamic Range for 6G Communication in 0.13-μm SiGe Process

Abstract

This paper presents a broadband frequency quadrupler (FQ) implemented with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doublers (×2) operate at an input frequency of 32.5–55 GHz and 65–110 GHz, respectively. To properly drive the two doublers with enough input power and bandwidth, two transformer coupled power amplifiers (PAs) have been adopted. The former power amplifier is based on a neutralized capacitor structure and the latter is based on a transformer topology. A nonlinear device model and a systematic methodology to generate maximum power at second harmonic are proposed. By manipulating the device nonlinearity and optimizing the magnetically and capacitively coupled resonator (MCCR) matching networks, optimum conditions for harmonic power generation are provided. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and a high energy efficiency η of 3.7% at 210 GHz.

1. Introduction

Due to the progress of SiGe BiCMOS technologies, the working frequency of semiconductor devices is increasing, 6G sub-THz circuits can be implemented based on these devices. Compared to GaAs and GaN processes, the SiGe BiCMOS technologies are capable for higher integration and lower power consumption, which is crucial for portable devices with compact size. Various solid-state circuits have been implemented in SiGe technologies [1,2,3,4], such as the CML divider (Current Mode Logic divider) [5], transimpedance amplifier [6], voltage-controlled oscillators (VCOs) [7], bandpass filter [8], and switch [9]. Including the above various blocks based on the SiGe BiCMOS process, they have been widely used in various sub-THz systems, including radar receivers [10], 5G transceiver [11], and high-resolution imaging device [12].

A wideband signal source with high dynamic range and stability is essential for these systems. Due to high frequency effects, including substrate loss and serious parasitic effects, and the decrease of transistor’s ft/fmax, it is difficult to realize a broadband high frequency signal source with a low phase noise and high dynamic range. To overcome the above disadvantages, accurately modeling for transistors and passive devices is important. In this paper, the device modeling and circuit analysis are analyzed to realize optimum matching networks and to optimize the second harmonic output power.

There are three methods to generate a wideband sub-THz signal. One method involves a sub-THz wideband VCO. However, the phase noise of the sub-THz VCO is seriously degraded due to the above high frequency effects and the frequency is modulated with temperature. To maintain the frequency, the phase-locked loop (PLL) is necessary, and the power consumption is large. The second method involves a narrowband VCO with relatively good phase noise. However, several PLLs must be utilized to realize a large frequency range. Thus, the power consumption is large. Instead of utilizing several PLLs to generate an ultra-wideband frequency, a frequency multiplier generating Nth harmonic by only low frequency PLL is a good solution [13,14,15,16,17,18]. Traditionally, a power amplifier can generate the desired Nth harmonic multiplied signal with undesired harmonics removed via a filter. Another technique is the linear superposition (LS) technique, which adds up the multiple-phase waves to construct the harmonic output. However, the efficiency (η) of these methods is low and the bandwidth is limited.

In this paper, two PAs with different bandwidths have been used to drive the frequency doublers, which enable the broadband response up to 220 GHz. The broadband signal generator in 0.13-μm silicon-germanium (SiGe) technology has used magnetically and capacitively coupled resonator (MCCR) matching networks. Thus, the second harmonic matching power is enlarged. We report the design and measurement results of the wideband FQ circuits with a bandwidth of 90 GHz and a peak output power of 2.5 dBm in a commercial 130-nm SiGe BiCMOS technology. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and η of 3.7% at 210 GHz. In Section 2, the adopted 130-nm SiGe BiCMOS technology and device model are briefly discussed. Section 3 presents a working principle of the doubler, matching network and design of the FQ at 130–220 GHz, including the PAs and two wideband doublers. The measurement results of the FQ are presented in Section 4 and are also compared with prior state-of-the-art works. Finally, the conclusion is given in Section 5.

2. The Process of the 130-nm SiGe BiCMOS Technology and Device Modeling

It can be seen from the back-end-of-the-line (BEOL) cross section in Figure 1 that the thickness of the top two-layer metals is the thickest among all available metal layers. The process is highly suitable for various mm-wave and THz circuits. The EM (Electromagnetic) simulation environment in HFSS (High Frequency Structure Simulator) software is further supported by the process. The main material of the top two layers is copper which has low resistivity and can be utilized for a passive-device design. The metal layers enable the customized realization of a high-quality inductor, transformer, and transmission line, such as a microstrip and coplanar line.

To reduce the losses of metal interconnections of the double balanced mixer and improve the current carrying capacity of the connecting line at Sub-THz range, the top two metals, which have higher current densities and lower sheet resistance, are adopted. The connecting metals and vias should reduce the parasitic effects between multi-layer metals. Therefore, the connection between the active devices and passive devices are shown in Figure 2. The proposed connection can significantly improve the RF (Radio Frequency) performance. In addition, compared to a standard CMOS process, a SiGe process provides high-performance hetero-junction bipolar transistors (HBTs) that exhibit ft/fmax of 300/500 GHz and breakdown voltages of BVCEO = 1.5 V and BVCBO = 5 V, respectively.

The device model of the HBTs is shown in Figure 3. $g_m$ is the transconduance of the devices, and $C_{b^{\prime }c}$ is the capacitance between the collector and the base. Due to $C_{b^{\prime }e}$, there is a crossover between the input and output of the transistor, which shows the miller effect and reduces the stability of the transistor. Then, we can formulate the equations from the small signal model diagram:

The model includes the intrinsic parameters of HBT devices without the parasitic parameters of interconnections. The intrinsic parameters of a small signal equivalent circuit model can be directly extracted by de-embedding and using the Y-parameter. The Y-parameter matrix of the intrinsic model can be calculated as follows [19,20,21]:

$${\mathrm{Y}}_{11}=\frac{g_{b^{\prime }e}+j\omega C_{b^{\prime }e}+j\omega C_{b^{\prime }c}}{1+r_{b{b}^{\prime }}\left(g_{b^{\prime }e}+j\omega C_{b^{\prime }e}+j\omega C_{b^{\prime }c}\right)}$$

(1)

$${\mathrm{Y}}_{12}=-\frac{j\omega C_{b^{\prime }c}}{1+r_{b{b}^{\prime }}\left(g_{b^{\prime }e}+j\omega C_{b^{\prime }e}+j\omega C_{b^{\prime }c}\right)}$$

(2)

$${\mathrm{Y}}_{21}=\frac{g_m-j\omega C_{b^{\prime }c}}{1+r_{b{b}^{\prime }}\left(g_{b^{\prime }e}+j\omega C_{b^{\prime }e}+j\omega C_{b^{\prime }c}\right)}$$

(3)

$${\mathrm{Y}}_{22}=g_{ce}+j\omega C_{b^{\prime }c}+j\omega C_{cs}+\frac{\left(g_m-j\omega C_{b^{\prime }c}\right)j\omega C_{b^{\prime }c}{r}_{b{b}^{\prime }}}{1+r_{b{b}^{\prime }}\left(g_{b^{\prime }e}+j\omega C_{b^{\prime }e}+j\omega C_{b^{\prime }c}\right)}.$$

(4)

The proposed FQ utilizes two cascaded doublers to obtain conversion power gain, however it will be limited by the cut-off frequency ft, which is described by current amplification factor $\left|\beta \right|$ decreasing to 1 for the common emitter configuration. In order to improve the gain, the active devices and passive devices are both optimized. Passive device modeling is an important part for FQ design because these devices are utilized for the input/output and inter-stage matching. Generally, the manufactory provides some standard models of the capacitors, inductors, and transmission lines. However, the required accurate frequency of these models is up to 20 GHz and these models cannot meet the requirements of the proposed Sub-THz circuit design. The connecting lines between the HBTs contribute inductance and capacitance whose patterns are determined by the layout of the chip. Thus, it is essential to customize design and model passive devices and connecting lines based on the microwave circuit for optimum matching among the HBT.

3. The Proposed FQ Circuits

3.1. The Working Principle of the Frequency Doubler

The working principle of the doubler is using a nonlinear device. Making the input sine wave pass through the nonlinear device, and the output waveform will be distorted to produce various harmonics. Then, the filter circuit is used to extract the required harmonic to obtain the required terahertz signal. A simple nonlinear network is formed by a two terminal nonlinear capacitor, which is formed by the collectors of the SiGe devices. Taking the varactor as an example, the nonlinear characteristics of diode junction capacitance is briefly described. If the epitaxial layer of the diode is uniformly doped, then the junction charge function is where $C_{j0}$ is the zero-bias junction capacitance, V is the junction voltage, and the diffusion potential is the difference of the work function between the anode metal and the semiconductor of the diode, then the small signal junction capacitance is:

$$C\left(V\right) =-2C_{j0}\varnothing \sqrt{1-\frac{V}{\varnothing }} .$$

(5)

Among them, if $C_{j0}$ is the zero bias junction capacitance, V is the junction voltage, and the diffusion potential is the difference of the work function between the diode metal and the semiconductor, then the small signal junction capacitance is:

$$C\left(V\right) =\frac{dQ\left(V\right)}{dV}=C_{j0}{\left(1-\frac{V}{\varnothing }\right)}^{-\frac{1}{2}}.$$

(6)

If the epitaxial layer of HBTs’ collector is non-uniformly doped and has certain regularity, the expression of junction capacitance can be obtained by changing the index of the denominator of Formula (5). γ is strongly related to the doping concentration distribution of the epitaxial layer, which is not suitable for a large reverse voltage range when the doping is very uneven and can be expressed by different parameters:

$$C\left(V\right) =\frac{dQ\left(V\right)}{dV}=C_{j0}{\left(1-\frac{V}{\varnothing }\right)}^{-\gamma }.$$

(7)

Suppose that the varactor diode external excitation is $V=V_O+V_{s}cos\omega t$. By substituting it into the general expression of varactor junction capacitance, we can get Formula (8):

$$C\left(t\right)=C_{j0}{\left(1-\frac{V_O+V_{s}cos\omega t}{\varnothing }\right)}^{-\gamma }.$$

(8)

The corresponding junction capacitance curve with nonlinearity is shown in Figure 4. As shown as in Figure 5, the nonlinear capacitors can be formed by connecting the col-lectors of the two HBTs with the differential voltage source [19]. If the frequency doubling is required, the HBTs’ collector generally needs to be applied with a bias voltage to make the HBTs work in the nonlinear state, and the output current will generate high-order harmonics. The excitation signal is provided by the front-end stage with differential signals $V_{i^{+}},V_{i^{-}}$. The charge of the two terminal nonlinear capacitors can be expanded in power series:

$$Q=a_0+a_1{V}_i+a_2{V}_i^2+a_3{V}_i^3+\cdots .$$

(9)

Assuming $V_{i^{+}}=V_{+}cos\left(\omega t\right),V_{i^{-}}=V_{-}cos\left(\omega t\right)$, then:

$$Q_A=a_0+\frac{1}{2}{a}_2{V}_{+}^2+\left(a_1{V}_{+}+\frac{3}{4}{a}_3{V}_{+}^3\right)cos\omega t+\frac{1}{2}{a}_2{V}_{+}^{2}cos2\omega t+\cdots$$

(10)

$$Q_B=a_0+\frac{1}{2}{a}_2{V}_{-}^2+\left(a_1{V}_{-}+\frac{3}{4}{a}_3{V}_{-}^3\right)cos\omega t+\frac{1}{2}{a}_2{V}_{-}^{2}cos2\omega t+\cdots .$$

(11)

When the excitation of the nonlinear network is a single tone cosine signal, Formula (11) shows that the circuit response contains the dependent nonlinearity. By using the filter circuit and impedance matching circuit, the specific harmonic components can be extracted from each harmonic. $Q=Q_B+Q_A$ is in some symmetrical circuit topologies and only contains even terms, then the circuit response will only produce second harmonics.

The passive devices realized filter utilizes the transformer. The magnetic field of the transformer is mainly limited in the primary coil and secondary coil, so the surrounding ground has little influence on the electromagnetic field. At the same time, only a small part of the magnetic field passes through the silicon substrate, so most of the energy of the transformer is transferred from the primary coil to the secondary coil through coupling. The differential structure of the transformer ensures there is a better common mode signal suppression and reduces the impact on the power supply and ground. The bias voltages of doublers are fully designed to generate the highest power of second harmonic by maximizing the second harmonic current and impedance at this frequency.

3.2. The Matching Network Analysis and Power Amplifier Driver

Figure 6 is the block diagram of the input buffer circuit and frequency multiplication circuit. The collectors of the SiGe HBTs are connected to the output matching networks, which is convenient for high power heat dissipation. If the collector of SiGe has the square law Q-V characteristic (such as the abrupt junction varactor), the circuit can be set up to allow the second harmonic current to return to the varactor and mix with the fundamental current again. The circuit can make full use of the energy of the second harmonic and improve the efficiency of harmonic frequency doubling. The specific matching circuit is the transformer. For example, in a low-frequency circuit, the transformer is shorted to ground and in terahertz frequency, the harmonics are completely amplified by inductors of the transformer.

To improve the bandwidth of the doublers, transformers are utilized. A transformer is widely used in sub-THz circuits. Its main advantages are as follows. The electromagnetic field of the transformer is very clear, which makes the inductance value of the primary coil and secondary coil and the coupling coefficient have good predictability even at the millimeter wave frequencies. There are three kinds of coupling and tuning mechanisms: magnetic coupling, electrical coupling, and electromagnetic coupling. For each coupling mode, the parameter that is generally concerned is trans-resistance Z, that is, the ratio coefficient of the output voltage to the input current.

The amplitude mismatch of an electromagnetic coupling resonator is related to a single coupling variable $k_M$ (magnetic coupling coefficient) or $k_C$ (electrical coupling coefficient), Figure 7 shows the model of the magnetic-capacitive coupled resonator (MCCR) which consists of two coupled RLC resonators by mutual inductance M and coupling capacitance C_c. Then the magnetically coupling coefficient is $k_M=M/\sqrt{L_1{L}_2}$ and the capacitive coupling coefficient is defined as $k_C=C_c/\sqrt{\left(C_1+C_c\right)\left(C_2+C_c\right)}$. To achieve the widest matching bandwidth, several key parameters need to be co-optimized, such as the resonator frequency ${\omega }_i=1/\sqrt{L_i\left(C_i+C_c\right)}$ and the quality factor $Q_i={\omega }_{i}R\left(C_i+C_c\right),i=1,2$ of the two tanks. The input of the BJT (Bipolar Junction Transistor) is a current which will be transferred to a voltage by trans-impedance Z₂₁ of the MCCR network. Thus, the impedance Z₂₁ can indicate the bandwidth of the matching network. Figure 8 shows the calculated Z₂₁ of MCCR with different ω₂/ω₁ ratios. It can be observed that the widest 3-dB bandwidth amplitudes of Z₂₁ is achieved when the resonant frequencies of the two resonators are close. Based on above analysis, the two pole frequencies ${\omega }_{P1}\approx {\omega }_0/\sqrt{\left(1-k_M\right)\left(1+k_C\right)},{\omega }_{P2}\approx {\omega }_0/\sqrt{\left(1+k_M\right)\left(1-k_C\right)}$ can be optimized to achieve a bandwidth of 90 GHz.

A stack transformer [22] passive structure is used to implement the MCCR with a very compact area. The pole frequencies of MCCR are determined by the two coupling coefficients k_M and k_C. They are symmetric and the two factors can be tuned by changing the width of the coupled metal lines. The passive structure with the MCCR 3D EM model is shown in Figure 9, which consists of matching networks for the input buffer, doubler, buffer, doubler, and output buffer. To accurately design the size of the n-p-n transistor, a small signal model of devices is shown in Figure 5 and its key parameters can be calculated from the S-parameter. To realize the maximum output power of the second-harmonic signal, a harmonic impedance matching technique is utilized. Instead of matching the gain of the stage, the sourcepull and loadpull of the transistors are operated to extract the best matching impedance. An improved and complete method for the high-frequency large signal modeling of SiGe HBTs is simulated to gain the optimized impedance for the circuit design. Harmonic impedance matching is utilized for the doubler design because the input matching of the doubler is based on the sourcepull impedance of fundamental frequency and its output matching is based on loadpull impedance of second harmonic frequency.

The MCCR networks are designed in top-metal 1, 2 to reduce the losses and easily control the coupling coefficients k_M and k_C. The 20-μm n-p-n device using a C-B-E-B-C layout configuration is optimized to reduce the parasitic layout and its ft/fmax is 250/300 GHz when biased at the optimal current density.

3.3. The Proposed Driver Circuit and QA Circuit

Figure 10 shows the block diagrams of developed broadband FQ. The chains employ similar building blocks, such as the input balun (32.5–55 GHz), input amplifier, inter-stage buffer, output amplifier, and D-band FQ ×4 (130–220 GHz) with wideband frequency doublers ×2. The two PAs are required to drive the frequency doubler with enough power in the operating wideband.

In the first input buffer stage, a broadband buffer has been adopted as the amplifying stage. The instability of the power amplifier is induced by the feedback capacitor C_gd, especially for a relatively low frequency because the SiGe transistors have a large gain at a low frequency. The input balun provides differential signals (32.5–50 GHz), which are fed into the input driver. Adopting the neutralization technique, the C_gd can be reduced and the stability can be improved. A second harmonic amplifier has also been used to improve the desired frequency power and to suppress unwanted harmonics.

The quadrupled signals are further amplified by either broadband PAs to have an output power in the range of 5–9 dBm. The transformer can achieve perfect DC isolation, which greatly simplifies the design of the multi-stage power amplifier. The circuit schematic of the proposed quadrupler is shown in Figure 10 and the measurement diagram of the proposed chip is shown in Figure 11. The second harmonic impedance for Q_2a, Q_2b and Q_4a, Q_4b are biased at a low voltage level (0.8–0.9 V), thus the nonlinearity of the transistors is strong, and it can generate large second harmonic signals.

After the second harmonic extracted, the second harmonic signal will be differential by balun. The single-ended doubler employs the device layout where the base and collector are extended lengthwise through the M2-M6 layers before connecting via stacks leading to the MCCR network. Then the MCCR network can realize power matching, dc biasing, and wideband. The emitter, base, and collector resistances and base-emitter and base-collector capacitances can be extracted from the model for small signal matching. Based on these measurement results and theory optimizations, the sizes of the HBT devices and the coupled MCCR can be determined. These sizes of the HBT devices are shown in

Table 1. The sizes of the HBT devices.

Stage of n-p-n	Size of n-p-n Transistor
	M	Emitter Width (nm)—70
1	6	Emitter Length (nm)—900
2	6	STI (nm)—440
3	4	baspolyx (nm)—300
4	4	bipwinx (nm)—70
5	4	bipwiny (nm)—100
6	4	empolyx (nm)—150
		empolyy (nm)—180
Active transistors design for quadrature

.

The conventional ESD (Electro-Static Discharge) protection circuit is mainly composed of diodes, which introduces a large parasitic capacitance to the ground, usually between 0.5–2 pF. This capacitor has a great loss at the millimeter wave frequency, which makes the conventional ESD circuit unable to be used at the millimeter wave frequency. The single to double transformer can well realize ESD protection of a millimeter wave circuit. Based on the above advantages, transformers are widely used in millimeter wave frequency.

4. Measurement Results

The quadrupler signal generator chip has an area of 0.34 mm² as shown in Figure 12. The circuit was characterized on wafer using a ground signal ground (GSG) probe with a waveguide transition system to VDI mixer. The matching calibration is realized by on-wafer open, short, and through devices. For power calibration, the frequency dependent probes and waveguide losses at the input and output were de-embedded. In the input, a Keysight UXA E9040B analog signal generator with mixers (E8257DV05, 06) provides the input signal from a low frequency up to 220 GHz as shown Figure 13. The power calibration and spectrum measurements are utilized to characterize the fourth harmonic of the proposed quadrupler. The output measurement setup has harmonic mixers (N9029AV05, 06) with a Keysight UXA signal analyzer N5247B spectrum analyzer, which realizes frequency detection up to 220 GHz. The harmonic mixer setup down-converted the RF signal into a single-tone signal and showed it in the spectrum analyzer corresponding to the output frequency of the quadrupler.

At a bias condition of VDD = 1.6 V, Vb1 = 0.85 V, Vb = 0.9 V, the input buffer, quadrupler, and output amplifier draw 10 mA, 6 mA, and 26 mA from the 1.6-V supply, respectively. The output frequencies of 140 GHz and 210 GHz are shown in Figure 14 with output calibration. The phase noise at 156 GHz and 220 GHz is −97 dBc/Hz, which shows the good quality of the output signals as shown in Figure 15.

The output dynamic range of the quadrature defined as the maximum ratio of the largest desired signal to the smallest desired fourth harmonic. In a 130–220-GHz range, the dynamic range of the quadrature signal is above 80 dB and the unwanted harmonic leakage is well below −20 dBc with respect to the fourth harmonic. Figure 16 exhibits the relationship between the input and output power at different frequencies. The output power becomes saturated as the input power increases. The input signal power is from −30 to −5 dBm and the output signal yields an 80-dB dynamic range as illustrated in Figure 16. The maximum gain with buffer is 16 dB with a −15 dBm input at 210 GHz. The phase noise is also measured, and it is increased by 20 dB at 230 GHz with a 1-MHz frequency offset after calibration. At 1.6 V, the presented circuit achieves an efficiency of 3.7% (including all buffers) at 210 GHz. Figure 17 shows the phase noise measurement results for different frequencies.

Table 2. The comparison with other papers.

Reference	Method	Technology	Freq. (GHz)	N	Gain (dB)	Pout (dBm)	PDC (mW)	Input Buffers	Output Buffers	η (%)
[23]	LS	90 nm CMOS a	322–326	4	N	−46	12	N	N	0.0002
[24]	PCPP b	0.13 μm SiGe	121–137	×4	0.6	−2.4	35.2	Y	N	1.6
[25]	Cascaded Doubler	0.12 μm SiGe	70–110	×4	−4.5	−4.5	240	N	N	0.3–0.8
[26]	Injection-locked	0.13 μm SiGe	148–183	×4	5	−4	49	N	N	0.8
[27]	Cascaded Doubler	0.13 μm SiGe	99–132	×4	N	8.5	79.2	N	N	8.8
[28]	PCPP b	0.13 μm SiGe	248–262	×4	N	−8.4	22.4	N	N	0.65
[29]	PP c	0.13 μm SiGe	152–220	×4	N	−1	45	N	Y	1.8
[30]	Cascaded Doubler	0.13 μm SiGe	100–184	×4	25	5@130	42	N	N	7.5
[31]	PP	0.13 μm SiGe	190–255	×4	−24.4	−16.4	48	N	N	0.048
This work	MCCR + HIM	0.13 μm SiGe	130–220	×4	16	1.86@210 GHz	42	Y	Y	3.7@210 GHz

^a. CMOS: Complementary Metal Oxide Semiconductor. ^b. PCPP: Phase-Controlled Push-Push. ^c. PP: Push-Push

summarizes the performance of the 130–220-GHz frequency quadrupler, and the results are compared with different state-of-the-art frequency quadruplers in paper [19,20,21,22,23,24,25,26,27]. The quadrupler presented in this paper delivers relatively the highest output power and widest bandwidth. Meanwhile, it achieves high gain without using supplementary input drivers. Each passive MCCR network is optimized to achieve the widest bandwidth and the measurement results show that it can achieve a bandwidth that is over 90 GHz and an 80-dB dynamic range, which is the largest among all circuits.

In conclusion, a 130–220-GHz signal generator in a 0.13-μm SiGe technology based on MCCR matching networks and harmonic impedance matching technique is proposed. The MCCR based passive matching networks and the active devices are all analyzed and co-optimized to extend the bandwidth. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range.

5. Conclusions

This paper presents a broadband FQ fabricated with a standard 130-nm SiGe BiCMOS process. Two broadband push-push frequency doubler (×2) operating at 32.5–55 GHz and 65–110 GHz are employed. To properly drive such doublers, with a sufficient input power and bandwidth, two different power amplifiers (PAs) have been adopted: The former is based on a cascaded configuration and the latter is based on a stacked topology. A nonlinear device model and a systematic methodology to generate maximum power at any desired harmonic is proposed. By manipulating the device nonlinearity and optimizing the embedding networks, optimum conditions for harmonic power generation are provided. A novel broadband signal generator in 0.13-μm silicon-germanium (SiGe) technology with MCCR matching networks and a harmonic impedance matching technique is proposed. The measurement results show that the proposed quadrupler provides a 90-GHz bandwidth with an 80-dB dynamic range and η of 3.7% at 210 GHz. This high-performance frequency FQ can be applied in 6G communication and other sub-THz communication systems.

The efficiency of the current quadrupler is not high enough, which can be improved in the future. Currently, many communication circuit designs are integrated in a CMOS technology [32,33]. The proposed FQ is utilized by a SiGe process, which have a high voltage, and it cannot be integrated with advanced CMOS. Researchers can consider using a CMOS process to complete the relevant design.