Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging

Abstract

Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies.

1. Introduction

For about seven decades, semiconductor integrated circuit technologies, mainly in the Si complementary metal oxide semiconductor (CMOS) platform, have been continuously advancing, driven by Moore’s Law [1,2,3,4,5]. However, simple CMOS scaling is rapidly approaching its physical limit, raising a big question: “What will future chips look like ten years from now?” The mainstream consensus is that heterogeneous integration technology opens a viable pathway for continuous advances to deliver smart future chips in the age beyond Moore’s Law. It is known that the information technology (IT) era, mostly enabled by Moore’s Law, has been technology-driven and computing-centric, where conventional “IC functions” include computing, storage, connectivity, and networking. It is also clear that the upcoming internet-of-everything (IoET) age must deal with complex human–technology interfaces that demand not only high system performance but also rich functional diversities, which in turn require various “non-IC functions” including sensing, actuation, control, photonics, quantum, and bio-inspired functionalities [6,7,8,9,10,11,12,13,14,15,16,17,18,19,20]. Smart future chips will hetero-integrate different devices made in dissimilar materials in different technologies into heterogenous superchips by holistic co-design. Such heterogeneous devices include chiplets, which are loosely defined as chips in the same substrate (e.g., Si) of different functions (e.g., analog, digital, radio frequency/RF, high-voltage/HV, and high-power/HP, etc.) and dielets, which refer to device dies made in different materials for very different functional modalities (e.g., sensors, micro-electromechanical systems/MEMSs, photonics, compound semiconductors, bio-medical devices, etc.). HI technologies will address several key limitations in pursuing advanced microsystem chips. First, the size of CMOS chips is limited by manufacturability, including photolithography field and yield. Second, sophisticated ICs at advanced technology nodes become economically unpractical due to prohibitively high engineering design costs, e.g., up to USD 1.5 billion at a 3 nm CMOS node [21]. Yet, while some circuitry benefits dramatically from using few nm technologies (e.g., GPU, CPU, artificial intelligence/AI accelerators, etc.), many others can sufficiently use low-cost legacy IC technologies (e.g., I/O, power management IC/PMIC). Third, many critical devices (e.g., sensors, MEMSs) and circuits (e.g., RF, HP, HV) deliver the best functions in different materials (non-Si or non-CMOS). On the other hand, it is intuitive that high performance benefits most from monolithic integration at the single-chip level, e.g., system-on-a-chip (SoC), in order to ensure high data flow bandwidth that decreases dramatically when crossing physical device boundaries (e.g., die-to-die, chip-to-board). Therefore, HI technologies that can de-aggregate a prohibitively large SoC chip into chiplets/dielets (delivering the best functions in their native materials and at suitable technology nodes) that will then be re-aggregated into re-constituted SoIC chips on one wafer/substrate (re-constituted artificial wafer/chip) to deliver microsystem superchips of extreme performance and rich functionalities are being actively pursued. Heterogeneous integration hence opens a door to smart future chips to enable the emerging IT-to-IoET transition [22,23,24,25].

It is important to know that advanced packaging becomes essential to delivering smart future chips by unlocking the full potential of HI technologies at the SoIC level, i.e., utilizing the best individual device functions in their native formats. Traditional electronic packaging simply seals an IC die into an enclosure and then assembles many components (active circuits and passive elements, e.g., resistors, inductors, capacitors, sensors, transformers, etc.) onto a printed circuit board (PCB) to form a system on a PCB. Advances in packaging benefited from the development of materials and fabrication, which led to the system-in-package (SiP) that assembles device dies onto a miniatured PCB (e.g., laminates) to form a compact SiP. Therefore, 2D/2.5D/3D packaging becomes available along with continuous technology advances, such as new packaging substrates, ball bonding, through-silicon vias (TSV), Si interposers, micro bumps, copper pillars, Cu–Cu bonding, Si bridges, integrated passive devices, flip chips, stacking, ball grid arrays (BGAs), wafer-level packaging (WLP), redistribution layers (RDLs), etc. [25]. Most recent advances in packaging technologies, which make HI-based SoIC superchips possible, include ultra-fine pitch interconnect fabrics and chip-on-wafer-on-substrate (CoWoS) packaging that smartly leverage matured and advanced IC fabrication technologies of IC-scale critical dimensions (down to a few μm and moving into the nm domain) that support hetero-integrating chiplets/dielets onto IC substrates to achieve wafer-level chip-scale heterogeneous integration of microsystems [26,27,28]. One of the most successful SoIC examples is the new Nvidia Blackwell GB200 superchip (integrating 208B transistors in a 4 nm CMOS) that stitches two B200 GPU cores (four dies), one Grace CPU die, and NVSwitch high-bandwidth interface dies (10 Tb/s) together in CoWoS packaging to deliver a record 20 petaflops in AI computing [28].

Reliability is a major barrier to realizing HI-enabled SoICs in terms of both performance and costs [27,29,30,31]. In particular, ESD is the most important reliability problem for heterogeneous integration technologies and ESD protection design becomes extremely challenging for realizing SoIC superchips [29,32,33]. The main reason is that SoIC chips can be extremely complicated in two senses, as indicted in Figure 1 [34]. First, an HI-enabled smart future chip may comprise many functional domains, such as energy and power (including power management IC, i.e., PMIC), logic computing (including CPU, GPU, and AI engines), memory stack (including high-bandwidth memories, i.e., HBM), analog/mixed-signal (AMX)/RF, sensors and actuators, photonics (including laser), imagers (e.g., CMOS imagers), chemical, medical and bio-inspired, and emerging nanotechnology devices, etc. Second, HI packaging has complex hierarchical structures in the context of materials, technologies, device structures, microsystem architectures, and packaging platforms. Specifically, the complexity of HI and SoIC directly translates into complications in ESD phenomena, hence making ESD protection design much more challenging. This article discusses a few key challenges faced by HI SoICs associated with advanced packaging.

2. Holistic ESD Protection for SoICs

Performance, reliability, and costs are the three core attributes for any IC. While high performance and dense integration are the true beauty of CMOS ICs, low-cost manufacturing makes chips affordable, leading to the huge success of ICs with massive societal impacts. On the other hand, it is excellent reliability that makes chips a wide-spread commodity today. ESD failure is one of the most devastating IC reliability problems, which causes USD billions of losses annually, substantially affecting the microelectronics industry, which has a revenue of USD ~600 billion (USD ~1123 billion expected for 2033) [35,36]. On-chip ESD protection is hence required for all ICs, echoing the industry saying: “No chip can be sold without ESD protection”. Fundamentally, the ESD phenomenon occurs when two objects of different potentials are brought within touching distance (or in close proximity). The static charges stored inside will exchange in between, generating very fast, very strong voltage (up to 10 s of kV) and current (up to 10 s of A) pulses that can readily damage ICs [37,38]. ESD protection uses a controlled switch device connected at a pad-on-chip, as depicted in Figure 2a, which stays OFF during normal IC operations and will be turned ON by an incoming ESD pulse to form a low-R conduction path to discharge the ESD transient into the ground (GND) [38]. Typically, a complex ESD protection network is needed on a chip to handle random ESD stressing on any pads and deal with different ESD zapping polarities, as illustrated in Figure 2b. An ESD protection device is typically characterized by a set of ESD-Critical Parameters describing its ESD discharging behaviors, which include ESD triggering voltage, current, and time (V_t1, I_t1, and t₁); holding voltage and current (V_h, I_h); discharging resistance (R_ON); and thermal breakdown voltage and current (V_t2, I_t1). These ESD-critical parameters must be carefully designed for any ESD protection structures to ensure compliance with the ESD Design Window, i.e., confined within the window as depicted in Figure 3 [32,39]. ESD protection structures inevitably introduce parasitic effects, including capacitance (C_ESD), leakage current (I_leak), and noises and noise coupling, which affect IC performance. Additionally, ESD protection structures are large; therefore, they will consume the Si die area and make the chip layout difficult. These unwanted features are collectively called ESD Design Overhead Effects and can seriously affect ICs; hence, a major ESD design challenge is how to minimize ESD design overhead effects [40]. Hard ESD failures include thermal damages (i.e., hot spots) induced by large current pulses and voltage breakdown caused by high electric field density. It is noteworthy that microelectronics system products generally require comprehensive ESD protection at all chip, module (packaging), and system (PCB) levels to handle random failures and prevent high system costs.

For heterogeneous SoIC superchips in advanced packaging, the following ESD protection challenges emerge. First, holistic cross-layer cross-domain ESD protection becomes essential for SoICs, differing from on-chip ESD protection for single chips. It is recommended, and likely will become mandatory in the near future, to have on-chip ESD protection for each chiplet/dielet and extra on-substrate ESD protection in packaging. On-chip ESD protection protects chiplets over their lifetime from manufacturing to assembly to usage. In-packaging ESD protection will be needed to protect the SoIC superchip during its lifetime, where it usually suffers from rough usage conditions in end-users’ hands, and the costs of ESD failures can be much higher than for a single chip. This is similar to how system vendors always require multi-level ESD protection (on-chip/on-board/in-system) for their system products regardless of on-chip ESD protection. In addition to the consideration of high system costs, scientifically, a reconstituted SoIC superchip will make in-packaging ESD phenomena much more complicated, as much is currently unknown or just emerging, consequently requiring investigation. Second, cross-layer ESD protection design for SoICs will be challenging and will need new ESD design methods. For example, on-chip ESD protection design requires the careful design of all ESD-critical parameters in order to comply with the ESD design window that is defined by the given IC technology. However, SoIC involves many different chiplets/dielets designed for different functions, made in different materials, using different IC technologies, and likely from different vendors; hence, when designing add-on in-packaging ESD protection, its ESD-critical parameters (e.g., V_t1, V_h) may be different for different die interfaces in order to ensure proper local/die ESD triggering while avoiding possible latch-up. For instance, the supply voltage (V_DD, V_SS) and breakdown voltage (BV_G, BV_DS) will be very different for different technologies (Si CMOS, SOI, BCDMOS, FinFET, GAA, nano sheet, SiGe, GaAs, GaN, HV, etc.) at different nodes (from legacy 180 nm to mature 28 nm to advanced 3 nm). A holistic ESD design approach is hence required for SoICs, considering all of the different chiplets and packaging features. Third, complex die-to-die interactions must be included for in-packaging add-on ESD protection designs, which are much more complicated than the inter-domain interactions on a single SoC chip. Fourth, advanced packaging features, such as wafer/substrate carriers, may be leveraged in designing add-on ESD protection. For example, add-on ESD protection structures may be embedded in the carrier substrate (much like the technique used for integrated passive devices) or in a local Si bridge, hence saving the area budget. In another example, highly efficient vertical ESD protection devices may be designed and implemented in advanced packaging, e.g., vertical ESD diodes in TSV holes in a substrate [40]. In addition, TSV-based local GND can be used where copper posts serve as excellent local thermal conductors to avoid ESD-induced local overheating [41]. Fifth, a Si interposer used in advanced packaging can be used to host add-on ESD protection structures in the SoIC package. Furthermore, in case all chiplets are in-house designed, it will be possible that a full SoIC/packaging ESD protection network may be built inside the Si interposer, as depicted in Figure 4, which will dramatically alleviate the design burden of ESD protection on each die, i.e., reducing or eliminating ESD protection devices on a die, which will be a paradigm shift in ESD protection designs [40,42]. Sixth, careful design balance must be considered both to ensure robust ESD protection and to retain the highest SoIC performance offered by chiplets. Special design consideration will be given to ensure high data bandwidth between dies that may be readily affected by both the interferences of different die/ESDs and add-on ESD protection in packaging. Seventh, it should be recognized that traditional in-Si PN-junction-based active ESD devices, e.g., diodes, BJTs, FETs and SCRs, etc., do not seem to be naturally suitable for add-on ESD protection in SoICs, which calls for innovation in ESD protection in packaging. One such novel ESD protection concept is a nano crossbar ESD switch device as depicted in Figure 5 [43]. In principle, this is a phase-changing type of ESD switch structure comprising an insulator sandwiched between two electrodes (Cu as the Anode, A, and W as the cathode, K). During normal IC operations, the ESD device stays OFF without affecting ICs. Under ESD stressing, the strong transient electric field will induce a phase change in the insulator, causing the switch to turn on and discharge the incident ESD pulse, hence providing ESD protection. This nano crossbar ESD protection device was proven in concept experimentally [44]. Figure 6 shows measured ESD discharging I-V characteristics for a prototype device under TLP testing, which clearly shows a symmetric ESD discharging I-V curve. A nano crossbar ESD array can be used to boost the ESD current handling capacity, showing excellent ESD robustness of I_t2 ~ 8.11 A in a 5 × 5 array [44]. It is worth noting that this new nano crossbar ESD switch device can be built at the far back end of line (BEOL; not inside Si) of SoICs, which is very friendly to in-packaging ESD protection. Eighth, cross-layer/domain co-simulation is highly required to optimize, validate, and predict overall ESD protection in SoICs. Unfortunately, both CAD tools and simulation methodologies for holistic ESD protection at the SoIC level are still in the R&D phase now. Nineth, a new ESD test standard and method will be needed for accurately characterizing holistic ESD protection designs, for example, when using human body model (HBM) zapping and transmission-line pulse (TLP) testing. A critical question is where and how to stress a SoIC.

3. CDM ESD Protection for SoICs

Charged device model (CDM) ESD protection is an emerging challenge for HI-based SoICs in advanced packaging. Classic on-chip ESD protection uses a pad-based ESD protection network to achieve ESD protection, as depicted in Figure 2b, which works well for HBM ESD scenarios. Principally, HBM ESD is an external-oriented ESD event where incident ESD pulses (charges) come from external charges onto a pad, and an ESD device-at-pad will be triggered to shunt the incoming charges into the ground (GND), hence providing ESD protection. Clearly, an ESD device-at-pad acts as a doorkeeper that stops the “intruder” (charges) from getting into the IC core via the pad. As such, pad-based ESD protection has been very efficient in preventing ESD damages to the IC core, which also works well for other external-oriented ESD events, e.g., the machine model (MM) and IEC model [38]. Historically, CDM ESD protection has also been following the classic pad-based ESD protection method for decades. However, it has been commonly known that CDM ESD protection often fails in protecting ICs in the field, particularly for those large, complex chips in advanced technologies, even when using CDM ESD protection structures that are validated by testing. Such randomness and uncertainty in CDM ESD failures make CDM ESD protection design appear mysterious in practical IC designs, causing a major headache to the industry. A recent study suggests that pad-based CDM ESD protection is theoretically incorrect because CDM ESD is an internal-oriented ESD phenomenon that is entirely different from an external-oriented HBM ESD event [45]. In CDM ESD events, charges are induced into an IC core, and this is inevitable during its lifetime [38,40]. When a pad is grounded, the charges inside an IC will be discharged into the GND via the grounding pad, hence providing CDM ESD protection. Accordingly, a very fast TLP (VFTLP) technique was developed to characterize CDM ESD protection [46,47,48], similar to using TLP testing to evaluate HBM ESD protection designs [49,50,51]. However, the CDM-induced charges are allocated (stored) randomly inside an IC core, and the total amount also varies randomly over time. As depicted in Figure 7, it seems to be intuitive that as the internally stored charges find their way to discharge at a grounded pad, a large volume of charges must run through the internal circuit randomly; therefore, it is highly possible that the substantial internal CDM ESD currents, and the voltage induced, can readily reach certain thresholds that cause internal CDM ESD damages. Hence, CDM ESD failures may occur internally and randomly regardless of how effectively pad-based CDM ESD protection is designed [47]. Simply put, CDM ESD phenomena are internal-oriented, where the ”bad” charges are hidden inside an IC; hence, a guard (ESD device) at the door (pad) assigned to fend off any “intruders” will not protect the IC. Upon this new understanding, a novel internal-distributed CDM ESD protection concept was recently reported where, as shown in Figure 8, CDM ESD devices of smaller sizes (than those used at the pads) are allocated intelligently to certain internal circuit nodes, based upon possible internal charge allocation scenarios (i.e., the CDM ESD risk levels). Therefore, during the IC’s lifetime and at any time, as local charge storage reaches a pre-set threshold, the local ESD device will be turned on to shunt the local charges directly to a local GND (instead of a global GND as in typical ICs), therefore providing CDM ESD protection. Since such internal charges do not have to route through any internal paths to be discharged in a global GND via a ground pad, any internal CDM ESD failures can be prevented [40]. This is a very new CDM ESD research discovery, which can also actually be applied to HI-based SoICs in an advanced package, albeit making CDM ESD protection design for SoICs much more complicated. This is because an SoIC has very complicated internal structures (i.e., different devices/dies made in dissimilar materials using different technologies), which apparently will make internal charge storage and allocation much more complicated compared to a single-die SoC. Furthermore, the structural complexity of advanced packaging, e.g., 3D CoWoS packaging as shown in Figure 1, will naturally create more charge storage complexity inside a packaged SoIC, leading to much more complicated charge allocation variation and randomness, which in turn will make random internal CDM ESD failures more likely in SoICs. It will hence be very challenging to design good CDM ESD protection for SoICs. One research direction will be to apply the internal-distributed CDM ESD protection concept to SoICs, where pad-based ESD protection structures at each die (chiplets) may be revised to serve as “internal-distributed” (each die is internal to the SoIC) CDM ESD protection for SoICs. Obviously, one should be expecting to use the at-pad ESD devices on a die as is, because these ESD devices follow the classic pad-based ESD protection mechanism (e.g., ESD device sizes and local ESD design windows) and hence are not specially designed to address the local charge allocations smartly. On the other hand, extra add-on ESD devices are needed for some nodes/boundaries inside the SoIC as per the understanding of all chiplets/dielets used, as well as the SoIC and packaging architecture details. This apparently brings more design complexity to CDM ESD protection for SoICs. Furthermore, when designing add-on in-packaging ESD devices for internal nodes in SoICs, it will be very inefficient, and likely unpractical, to use traditional PN-based active devices (e.g., diodes, FETs, SCRs). Innovations in ESD protection mechanisms and device structures will be highly desirable for adding internal CDM ESD devices in SoICs. For example, the in-BEOL nano crossbar ESD array structure discussed earlier (Figure 5) seems to be a viable candidate for SoICs because it does not use any in-Si PN junctions and can be fabricated in any BEOL-like stacks, e.g., in the top passivation layer or in the middle interposer/substrate (Figure 1); therefore, it is naturally suitable for heterogeneous SoICs in advanced packaging. Accurate CDM ESD testing is another emerging challenge for SoICs. Traditionally, zapping and VFTLP testing have been widely used for CDM ESD characterization, where each pad will be stressed by CDM ESD pulses [46,47,48]. Figure 9 explains the typical field-induction CDM (FICDM) ESD testing method, where an IC die is placed on top of an insulator plate. In the CDM ESD charging phase, an HV field is applied to induce charges into the IC die. In the CDM ESD discharging phase, a pogo pin is switched to touch one pad (grounding), causing internal charges to discharge into the GND. The DUT (IC) will then be evaluated for possible ESD failure [46]. There exist two main defects in this FICDM testing method. First, the testing model was developed for pad-based ESD protection assuming that charges are coming from external charges; however, in reality, CDM ESD is internal-oriented and discharging comes from internal charges. Therefore, the existing industrial CDM ESD test standard may be theoretically wrong, likely contributing to CDM ESD failure randomness. Second, internal charge storage/allocation plays a key role in CDM ESD events where charge induction occurs during the lifetime of an SoIC and rather randomly. However, the standard FICDM method relies on a short field induction procedure to charge an IC, during the period the induced charges simply do not have enough time to be distributed the same way as in real-world scenarios; therefore, the complexity and randomness of internal charge allocations cannot be modeled by FICDM, likely contributing to CDM ESD test uncertainties. While the pad-zapping method may not be useful for CDM ESD characterization at the chip level, VFTLP may be used to stress individual ESD devices that are designed as internal-distributed CDM ESD protection units. Although such testing may reveal how well an individual CDM ESD device is designed (e.g., response time, current-handling capability, ESD triggering voltage, etc.), such testing cannot be used to characterize full-chip CDM ESD protection [40]. Interestingly, following the same consideration, VFTLP testing may be used for at-pad CDM ESD stressing for each die that is ”internal” to the SoIC, possibly revealing how an at-pad ESD device on a die may contribute to internal “local” CDM ESD protection for SoICs in the context of “internal”-distributed CDM ESD protection for the SoIC in advanced packaging. Clearly, CDM ESD protection for SoICs in advanced packaging will be very complicated and challenging, calling for active research.

4. SoIC ESD Modeling and Simulation Challenges

Obviously, ESD protection designs for SoICs in advanced packaging must be simulation-based to ensure design successes. While similar to CAD-aided on-chip ESD protection designs for single-chip ICs, the heterogeneity and complexity of SoICs require comprehensive co-development (materials and technologies), co-design (devices, circuits, and packaging), and co-optimization (microsystem performance) by holistic co-simulation in cross-layer (die-substrate-board), cross-domain (materials-technology-function) approaches. Several emerging challenges call for R&D efforts to develop new ESD protection simulation design methodologies for SoICs. First, ESD modeling is a foundational technical challenge. Historically, the success of IC design entirely relies on circuit simulation enabled by comprehensive and accurate compact models (e.g., BSIM modeling for SPICE simulation). For on-chip ESD protection design for a single IC, limited success in ESD device modeling facilitates ESD protection simulation at the circuit level [52]. Nevertheless, accurate ESD device modeling remains a major technical barrier for ESD protection circuit simulation for a single IC. This is because ESD protection involves very complex multi-coupling effects, i.e., the electro-thermal-transient-materials-process-device-circuit-layout coupling effect [39,53]. ESD device behavior modeling has been successfully used for ESD protection design simulation, where accurate ESD device models can be developed from ESD test data, but only for given ESD devices [54,55]. The development of physics-based compact ESD device models has been hindered by many technical complexities. For example, fast ESD stressing leads to highly localized internal hot spots that are random and have unknown sizes, hence accurately modeling the internal thermal boundary conditions is impractical from an engineering perspective, resulting in inaccuracies in simulating the internal thermal failures of ESD protection structures. This ESD modeling challenge is greatly exacerbated in SoICs. Heterogeneity and integration, the two key advantages of SoICs, introduce complicated, tightly coupled internal physical boundaries between dissimilar materials and individual dies. Internal electrostatic characteristics are complicated by structural complexity. Poor thermal conductivity and complex thermal interfaces due to die-to-die and insulator interfaces can significantly worsen internal overheating, generating more hot spots. These problems are made much worse in advanced packaging due to the unique features, e.g., 3D stacking, interposers, Si bridges, vertical interconnects and ultrafine pitch, etc. ESD behavior modeling may not be practical for SoICs because counting on SoIC terminal behaviors (from testing) will lead to gross ESD design conservation at the microsystem superchip level. Furthermore, the physical packaging model must be integrated into SoIC ESD modeling, which adds more technical complexity. Therefore, ESD modeling at the SoIC level must be holistic, covering all details within the packaging, which will be a huge technical challenge. Second, SoIC-level ESD design simulation is a huge emerging design challenge. For single-chip ICs, on-chip ESD protection designs have greatly benefited from three simulation successes. The first success is using the TCAD-based mixed-mode ESD simulation design method to address the complex electro-thermal-transient-materials-process-device-circuit-layout coupling effects. This method has been commonly used by the industry [53]. The second success is related to the ECAD-based ESD protection circuit simulation method, using ESD behavior models or ESD compact models, although with limitations (i.e., using the exact ESD device tested) [52]. The third success is rather limited, where new CAD algorithms were developed to support full-chip ESD physical design verification that allows auto-extraction of ESD devices from a chip layout, making ESD-function-based physical design validation possible [39,56,57]. However, repeating such single-chip ESD simulation successes at the SoIC level will be extremely challenging, if ever possible. First of all, TCAD numerical ESD simulation, which is very successful for on-chip ESD protection design at the single-chip level, may be impractical at the SoIC level because no existing TCAD tool can support numerical ESD simulation at the SoIC level, and the complexity and scale for possible ESD field simulation of SoICs in packaging are unrealistic in computing. Next, when considering circuit/schematic-level ESD design simulation at the SoIC scale, both SoIC ESD behavior modeling and ESD compact modeling for each die (and further down to devices) are very questionable; hence, schematic-level ESD protection circuit simulation for SoICs will be very challenging. Furthermore, full-package SoIC ESD physical design verification will be needed to ensure ESD protection design success, for which both new CAD algorithms and software must be developed to enable auto-extraction of ESD devices, parasitic ESD structures, equivalent ESD-critical parameters, and ESD netlists for SoICs in packaging. In short, design optimization, validation, and prediction of ESD protection for SoICs in advanced packaging require innovation in ESD co-simulation that must be holistic across different materials and functional domains, as well as different physical layers. This will be a grand design-for-reliability challenge for chiplets-based hetero-integrated smart future SoIC microsystem superchips.

5. Summary

The ending of Moore’s law leads to heterogeneous integration and advanced packaging technologies to enable chiplet-based SoIC microsystem superchips with superior performance and diverse functionality. ESD design-for-reliability is a major technical challenge for smart future SoIC superchips due to complexity associated with rich heterogeneity and dense integration. This perspective article discusses several key emerging challenges for holistic ESD protection designs for SoICs in advanced packaging. It concludes that the success of ESD protection for SoICs requires comprehensive co-development, co-design, and co-optimization by holistic co-simulation across all layers and domains for SoICs in advanced packaging.