A 12-Bit SAR ADC with Binary Search Calibration Algorithm for a Split Capacitor

Abstract

This paper proposes a 12-bit SAR ADC capable of calibrating a split capacitor using a binary search technique for bio-signal processing applications. The proposed SAR ADC employs a calibration logic circuit to calibrate a split capacitor vulnerable to process variations and mismatches. The proposed foreground calibration process involves four iterations through the binary search algorithm. In this manner, the calibration speed can be increased by up to 3.75 times compared with that of the linear search calibration. The proposed SAR ADC was implemented with a CMOS 28 nm 1-poly 8-metal process. The effective layout, excluding bonding pads, occupied 939 × 450 $\mathsf{\mu }$m. Measurement results illustrated a power consumption of 30.7 $\mathsf{\mu }$W (analog power: 16.1 $\mathsf{\mu }$W and digital power: 14.6 $\mathsf{\mu }$W), INL/DNL of −1.8/1.7 LSB, and −0.7/0.7 LSB, respectively, ENoB of 10.3-bit, and a FoM of 53.7 fJ/step.

1. Introduction

Wearable devices are receiving significant attention. Research on low-power, high-resolution ADCs (Analog Digital Converters) is currently underway for bio-signal processing.

Bio-signals consist of EEG (electroencephalography), ECG (electrocardiography), and EMG (electromyography) signals. EEG, ECG, and EMG signals have a bandwidth of 0.1–100 Hz, 0.05–500 Hz, and 10 Hz–5 kHz, respectively. In addition, the voltage range of the bio-signals is small ($\mathsf{\mu }$V 100 mV) [1]. Due to the frequency and voltage range of EEG, EMG and ECG signals, the ADC should maintain a minimum 8-bit resolution and a 10 kHz sampling rate specification to be able to handle bio-signal processing. And this ADC should consume minimal power for portability and for embedded application in other electronic systems, which inherently results in the adaption of the SAR (Successive Approximation Register) ADC.

Recent research has been focused on developing low-power ADCs [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24]. In addition, when designing a low-power ADC, foreground and background calibration are performed to improve performance [7,8,12]. Foreground calibration is performed after bit conversion. Foreground calibration consumes less power with a slow sampling rate due to the calibration phase. On the other hand, background calibration conducts calibration and bit conversion at the same time. Background calibration offers a faster sampling rate than foreground calibration, but its calibration logic circuit is complex and consumes a lot of power. TS SS (Two-Step Single-Slope) ADCs are also being studied because of thier low power and high resolution [8]. A TS SS ADC uses a linear search algorithm based on a digital counter in bit conversion, which results in a slow sampling rate with low power consumption. Since it employs a digital counter and a ramp generator, this ADC is suitable for bio-signal processing requiring minimal power consumption and high resolution. The ramp output of a TS SS ADC is applied to the R-DAC (Resistor Digital to Analog Converter), and the output of the R-DAC is divided into two parts: coarse and fine conversions. Employment of an R-DAC causes process variation and high power consumption. Coarse conversion of the TS SS ADC operates at the time of bit conversion, and the fine conversion follows the coarse conversion. The coarse conversion has a higher weight factor of R-DAC than that of the fine conversion.

The authors of [7] performed background calibration on a split capacitor by adjusting a 7-bit assist DAC in the LSB (Least Significant Bit) part of the C-DAC (Capacitor Digital to Analog Converter). A 7-bit assist DAC in [7] is connected to the output of the main C-DAC. The error detection register inside the ADC detects an error in the voltage generated by the mismatch. After that, the value stored in the error detection register is reflected by the 7-bit assist DAC. The error value is reflected through a feedback loop in the output of the C-DAC, canceling the error in the C-DAC. This allows the output of the C-DAC to be corrected. However, the ADC in [7] suffers from high INL (Integral Non-Linearity) and low ENoB (Effective Number of Bit). Likewise, 1.5-bit redundancy in [8] is designed so that the weight of the bits is duplicated. A calibration signal is generated from the duplicated bits and is applied to the digital calibration logic, which allows the DAC to offset the error. The ADC employing 1.5-bit redundancy exhibits low power, but poor INL and ENoB. Through calibration, the output waveform of the lamp is adjusted so that the output of the DAC approaches the ideal slope. However, paper [8] suffered from poor INL and papers [7,8] had slow sampling rates. Especially, ref. [8] consumed 62 $\mathsf{\mu }$W and had an ENoB of 9.8-bit.

The main idea of [9] is to present a practical low-power solution through a low-power sensor interface design in RFID (Radio-Frequency Identification) applications, thereby improving sensor data collection and performance of RFID systems. However, this research suffered from a low sampling speed of 6.25 kS/s and a low ENoB of 9.7-bit. Further, the main idea of [10] is to provide a hybrid design tool for automating and optimizing the design of SAR ADC in IoT applications. The ADC in [11] encloses a charge pump circuit and a phase frequency detector to eliminate the offset of the comparator. A phase difference occurs in the two differential outputs of the comparator due to the offset error of the comparator. This phase difference is detected by the phase frequency detector and the output of the phase frequency detector is applied to the charge pump. The output value of the charge pump is fed back to the comparator, eliminating the offset of the comparator. This calibration technique is valid for a high sampling rate, but suffers from high INL and low ENoB. Overall, refs. [9,10,11] without a calibration circuit showed low ENoB and poor INL. In [12,25], the calibration circuit employed a linear search technique where the size of the split capacitor is sequentially increased. However, the linear search technique requires a considerable amount of calibration time to find the proper split capacitor that matches the operating conditions. Additionally, if an incorrect split capacitor is calibrated due to comparator offset and external noise, the performance of the SAR ADC is further deteriorated. In [12], an ENoB of 11.5-bit, DNL (Differential Non-Linearity)/INL of ±1 LSB and −2.6/2.1 LSB, and FoM (Figure of Merit) of 155 fJ/step was achieved, indicating poor linearity and FoM performance.

Overall, the ADC presented in [7,8,9,10,11] showed high INL, slow sampling rates, and low ENoB. ADCs employed by bio-signal processors and wearable devices should be capable of providing low INL, a reasonably fast sampling rate (>10 kHz), and high ENoB. There is a need for different design techniques to provide low INL, a fast sampling rate, and high ENoB to ADCs processing EEG, ECG, and EMG bio-signals.

This paper presents a 12-bit SAR ADC that employs a binary search algorithm-based split capacitor calibration technique. The proposed SAR ADC uses the binary search technique four times to calibrate the split capacitor, enabling faster and more accurate calibration compared with the conventional linear search method. The architecture and the proposed design methodology is discussed in Section 2, measurement results are presented in Section 3, and conclusions are drawn in Section 4.

2. Materials and Methods

A block diagram of the proposed 12-bit SAR ADC with split capacitor foreground calibration based on a binary search algorithm is shown in Figure 1. The proposed ADC is composed of a C-DAC in differential mode, calibration switch control logic, a comparator connected to a pre-amplifier, 12-bit SAR logic, a reset generator, and an output register with the calibration split capacitor array. The calibration switch control logic contains the calibration logic and 2-CLK (Clock Signal) divider. The P and N nodes represent the upper and lower C-DAC, respectively.

Employment of a C-DAC is necessary for low-power application of the proposed 12-bit SAR ADC because it takes advantage of low-power consumption due to no dc current flow and low speed because of the charging and discharging capacitor array. In order to further reduce power consumption of the proposed ADC, total capacitance of the C-DAC should be minimized because power consumption is proportional to total capacitance of the C-DAC. Instead of utilizing the conventional binary weighted capacitor array in the C-DAC, a 6-bit MSB C-DAC and 6-bit LSB C-DAC with a split capacitor for foreground calibration, as shown in Figure 1, is employed to minimize total capacitance of the C-DAC in the proposed ADC. There are two types of calibration algorithm applicable to a split capacitor array, namely linear search algorithm and binary search algorithm. The plot shown in Figure 2 compares a number of capacitors from the binary search technique and that of the linear search technique as a function of the calibration cycle, where each cycle requires two CLKs. Calibration employing the linear search technique is capable of adding a split capacitor of 2$C_{\min }$ for a 4-cycle. On the other hand, employing the proposed binary search technique, a split capacitor of up to 15/2$C_{\min }$ may be added for a 4-cycle. A total of 15 calibration cycles are required to add a split capacitor of 15/2$C_{\min }$ with the linear search technique, so that it takes about 3.75 times longer than the binary search method. Therefore, the binary search method reduces the time required for foreground calibration, thereby increasing the sampling rate. As a result, the proposed ADC employs the binary search calibration algorithm.

The split capacitor array $C_{B,N}$ consists of a split capacitor of $4C_{\min }$, $2C_{\min }$, $1C_{\min }$, and $\frac{1}{2}{C}_{\min }$, where $\frac{1}{2}{C}_{\min }$ is the minimum unit capacitor (2fF) of the split capacitor array, as in Figure 1. The split capacitor array with calibration signal, CAL[4:1], is placed between the MSB and LSB blocks of the C-DAC.

A flowchart of the calibration algorithm is shown in Figure 3. The total LSB capacitance, $C_{\mathrm{Total},\mathrm{LSB}}$, connected in parallel within the C-DAC is given as,

$$C_{\mathrm{Total},\mathrm{LSB}}=C_u·\sum _{i=0}^6{2}^i$$

(1)

where $C_u$ is the unit capacitor of theC-DAC. Moreover, the split capacitor before calibration is initialized to become $C_{B,\mathrm{initial}}$. As the split capacitor becomes N-times calibrated, it becomes $C_{B,N}$ as,

$$C_{B,N}=C_{B,\mathrm{initial}}+C_{min}·\sum _{j=1}^{N}CAL(5-j)·2^{-j+3}$$

(2)

Since the total capacitance on the LSB node and split capacitor array of C-DAC can be obtained by a serial summation of $C_{\mathrm{Total},\mathrm{LSB}}$ and $C_{B,N}$ as ‘$\alpha C_u$’, it can be expressed as,

$$\alpha C_u=C_{\mathrm{Total},\mathrm{LSB}}+C_{B,N}$$

(3)

where $\alpha$ is a constant. The final goal of the calibration is to make ‘$\alpha$’ to be equal to unity [25].

A timing diagram for the proposed binary search-based split capacitor calibration is shown in Figure 4. When the reset signal, RST, becomes high at the first clock, the internal signal of the calibration switch control logic, CAL_DURING, becomes high, and calibration proceeds.

The first-phase calibration $(\mathrm{N}=1)$ presented in Figure 5 is performed through two clocks. As the 1st CLK is on the rising edge, the common-mode control signal, VCM CONTROL, becomes high, so that VOUT${}_{\mathrm{P}}$ and ${VOUT}_{\mathrm{N}}$ are connected to VCM, where VCM is the common mode voltage. As CAL4 is set to ‘1’ (CAL4 = 1), as shown in red box of Figure 6, the switch of the split capacitor array associated with $4C_{\min }$ turns on. In addition, $\mathrm{CAL}$[3:1] becomes low, ${\mathrm{P}}_{\mathrm{M}}$ and ${\mathrm{N}}_{\mathrm{L}}$ signals become low, and ${\mathrm{P}}_{\mathrm{L}}$ and ${\mathrm{N}}_{\mathrm{M}}$ signals become high. Hence, ${\mathrm{P}}_{\mathrm{L}}$ and ${\mathrm{N}}_{\mathrm{L}}$ signal the control capacitor of the LSB block, while ${\mathrm{P}}_{\mathrm{M}}$ and ${\mathrm{N}}_{\mathrm{M}}$ signal the control capacitor of each $\mathrm{B}7$.

The charges in the $\mathrm{C}$-DAC at the $\mathrm{P}$ and $\mathrm{N}$ nodes, $Q_P$ and $Q_N$, are determined by,

$$Q_P=\alpha C_u(VCM-VDD)+C_u(VCM-VSS)$$

(4)

$$Q_N=\alpha C_u(VCM-VSS)+C_u(VCM-VDD)$$

(5)

As the 2nd CLK is on the rising edge, VCM_CONTROL signal becomes low, as illustrated in Figure 7. Therefore ${VOUT}_{\mathrm{P}}$ and ${VOUT}_{\mathrm{N}}$ are floated, and ${\mathrm{P}}_{\mathrm{L}},{\mathrm{P}}_{\mathrm{M}},{\mathrm{N}}_{\mathrm{L}}$, and ${\mathrm{N}}_{\mathrm{M}}$ signal become toggled.

In the 2nd CLK falling edge, ${VOUT}_{\mathrm{P}}$ and ${VOUT}_{\mathrm{N}}$ signals are compared to determine the output signal of the comparator, COMP, so that the mismatch in split capacitors can be detected. In the timing diagram given, VOUT${}_{\mathrm{P}}$ is less than VOUT${}_{\mathrm{N}}$, and the COMP signal becomes low. Reflecting the COMP signal, CAL4 becomes low at the 3rd CLK.

According to charge conservation, $Q_P$ and $Q_N$ are described as,

$$Q_P=\alpha C_u\left({VOUT}_{\mathrm{P}}-VSS\right)+C_u({VOUT}_{\mathrm{P}}-VDD)+62C_u\left({VOUT}_{\mathrm{P}}-VCM\right)$$

(6)

$$Q_N=\alpha C_u\left({VOUT}_{\mathrm{N}}-VDD\right)+C_u({VOUT}_{\mathrm{N}}-VSS)+62C_u\left({VOUT}_{\mathrm{N}}-VCM\right)$$

(7)

Since (4) should be equal to (6) and (5) should be equivalent to (7),

$${VOUT}_{\mathrm{P}}=\frac{-\alpha +65}{\alpha +63}VCM$$

(8)

$${VoUT}_{\mathrm{N}}=\frac{3\alpha +61}{\alpha +63}VCM$$

(9)

As VCM_CONTROL signal becomes high, it is set back to VCM during the 3rd CLK. CAL4 and CAL3 become low and high, respectively, to reflect the value of COMP during the previous 2nd $\mathrm{CLK}$ in the timing diagram. Split capacitor $2C_{min}$ that is half the weight of the split capacitor $4C_{min}$ in the previous step is added.

If ${VOUT}_{\mathrm{P}}$ becomes larger than ${VOUT}_{\mathrm{N}}$ during the 2nd $\mathrm{CLK}$, then COMP $=1$, and CAL4 and CAL3 stay high, as presented in Figure 8. Otherwise, CAL4 stays low and CAL3 becomes high.

This calibration process is repeated four times ($\mathrm{N}=4$ and 8-CLK). VOUT ${\mathrm{V}}_{\mathrm{P}}$ and ${\mathrm{VOUT}}_{\mathrm{N}}$ become closer to the VCM, so that $C_{\mathrm{Total},\mathrm{LSB}}+C_{B,N}$ becomes closer to $C_u$. As the calibration is finished, CAL_DURING signal goes low, CAL_DONE signal becomes high, ${\mathrm{P}}_{\mathrm{M}}$ and ${\mathrm{N}}_{\mathrm{L}}$ signals become low, and ${\mathrm{P}}_{\mathrm{L}}$ and ${\mathrm{N}}_{\mathrm{M}}$ signals become high. Further, the foreground calibration is followed by the 12-bit data conversion.

Table 1. The operational table of the binary search calibration algorithm in terms of CAL[4:1], COMP, $▵C_{B,N}$, and calibration times (t1∼t4).

	$\mathbf{t}1$	$\mathbf{t}2$	$\mathbf{t}3$	$\mathbf{t}4$
$\mathrm{CAL}4$	1	0	0	0
$\mathrm{CAL}3$	0	1	1	1
$\mathrm{CAL}2$	0	0	1	0
$\mathrm{CAL}1$	0	0	0	1
$\mathrm{COMP}$	0	1	0	1
$▵C_{B,N}$	$4C_{min}$	$2C_{min}$	$3C_{min}$	$\frac{5}{2}{C}_{min}$

illustrates one example of operation of the binary search calibration algorithm in terms of CAL[4:1] and $▵C_{B,N}$ during the calibration times (t1∼t4), where $▵C_{B,N}$ is the calibration capacitor $C_{B,N}$. As CAL[4:1] becomes ‘1000’ with the COMP signal as ‘0’ during t1, $▵C_{B,N}$ becomes $4C_{\min }$. Since the COMP signal becomes low, CAL4 becomes ‘0’ to reflect the previous COMP signal, CAL3 becomes ‘1’, and $▵C_{B,N}$ changes from $4C_{min}$ to $2C_{min}$ during t2. Since the COMP signal stays high during t2, CAL3 remains ‘1’ and CAL2 sets to ‘1’, resulting in $▵C_{B,N}$ of $3C_{min}$ during t3. Since the COMP signal moves from low to high during t3 to t4, CAL2 changes from ‘1’ to ‘0’ and CAL1 sets to ‘1’, so that $▵C_{B,N}$ becomes $\frac{5}{2}{C}_{\min }$. Final CAL[4:1] and $▵C_{B,N}$ become ‘0101’ and $\frac{5}{2}{C}_{min}$, respectively.

The block diagram of the calibration switch control logic circuit presented in Figure 9 contains the calibration logic and a 2-CLK divider. The circuit diagram of the calibration logic consists of an 8-bit shift register and a 4-bit LFSR (Linear Feedback Shift Register), as illustrated in Figure 10.

The CAL_DONE signal is generated by the AND gate output of C0_BEFORE and $\mathrm{C}0$ from the calibration logic. As the CAL_DONE signal stays low and the CAL_DURING signal becomes high at the same time, the calibration process takes place. During the foreground calibration process, CAL[4:1] signals are determined to reflect the output of the comparator. These 4-bit calibration signals are used to control the split capacitor array.

The 2-CLK divider, as presented in Figure 11a, is implemented utilizing one JK flip-flop. It divides the CLK signal to generate ${\mathrm{P}}_{\mathrm{L}},{\mathrm{P}}_{\mathrm{M}},{\mathrm{N}}_{\mathrm{L}},{\mathrm{N}}_{\mathrm{M}}$ signals. The CAL_DURING signal from the calibration Logic becomes $\mathrm{K}$ input of the JK flip-flop within the 2-CLK divider.

The multiplexer to control the switch with VCM_CONTROL signal is shown in Figure 11b. The CAL_DONE signal and the ${\mathrm{P}}_{\mathrm{L}},{\mathrm{N}}_{\mathrm{M}}$ signals become the input signals of the multiplexer to generate the VCM_CONTROL signal with the CAL_DURING signal.

The proposed binary search calibration is influenced by process variation, as given by (10), where $\sigma$ is the standard deviation of the process variation. $C_{B,\mathrm{initial}}$ is designed to be $2\sigma$ smaller than the ideal split capacitor. According to the binary search algorithm, $C_{B,N}$ can be increased up to $C_{B,max}$, as given by (11).

$$C_{B,\mathrm{initial}}=\frac{64}{63}{C}_u-2\sigma$$

(10)

$$C_{B,\max }=C_{B,\mathrm{initial}}+\frac{15}{2}{C}_{\min }$$

(11)

The Monte Carlo simulation of the theoretical split capacitor $C_{B,N}$ in the process is illustrated in Figure 12. As the initial and maximum values of the variable split capacitor given by (10) and (11) are projected onto the graph, the process compensation range can be obtained approximately by $-2\sigma$ to $\sigma$.

The plots of the ENoB distribution from Monte Carlo simulation for the before and after calibration conditions are compared in Figure 13. The mean value of ENoB before calibration becomes 10.6-bit and the mean value of ENoB after calibration becomes 11.3-bit. The distributions of the ENoB before and after the calibration are relatively left-leaning and right-leaning, respectively. It is confirmed that the performance of ENoB is improved through the proposed binary search calibration algorithm.

3. Results

The proposed SAR ADC is implemented by a 28 nm 1-poly 8-metal CMOS (Complementary Metal Oxide Semiconductor) process. The chip photograph of the proposed SAR ADC with an area of $1110\times 600\mathsf{\mu }\mathrm{m}$ is shown in Figure 14. The effective layout excluding bonding pads occupies $939\times 450\mathsf{\mu }\mathrm{m}$. The 12-bit C-DAC, split capacitor array, and analog blocks of the comparator are located in the lower part of the layout. The digital blocks, including the C-DAC switches, calibration switch control logic, reset generator, SAR logic, and output register, are placed in the upper part. The design of the chip ensures physical and electrical separation between the analog and digital blocks of the chip.

A photograph of the PCB (Print Circuit Board) with the proposed ADC is presented in Figure 15. The PCB includes three SMA connectors for the differential input signals (VINP and VINN) and the clock signal (CLK), and five connectors (analog power nodes (AVDD (Analog Power Supply Voltage) and AVSS (Analog Ground)), digital power nodes (DVDD (Digital Power Supply Voltage) and DVSS (Digital Ground)), and VCM (common-mode node)). Three test pins to monitor three signals, namely RST, CAL_DONE, and ${\mathrm{P}}_{\mathrm{L}}{\mathrm{P}}_{\mathrm{M}}$, are placed adjacent to the proposed ADC chip for signal integrity purposes. The 12-bit digital output pins are placed on the upper portion of the PCB.

The measured waveforms of the CLK, RST, CAL_DONE, and ${\mathrm{P}}_{\mathrm{L}},{\mathrm{P}}_{\mathrm{M}}$ signals are illustrated in Figure 16. As the RST signal becomes high, the binary search calibration algorithm performs for $8\mathrm{CLKs}$, the CAL_DONE signal becomes high at the end of the 8th $\mathrm{CLK}$, and the 12-bit data conversion operation is performed for 14 CLKs. During the calibration process, the frequency of the ${\mathrm{P}}_{\mathrm{L}},{\mathrm{P}}_{\mathrm{M}}$ signal is reduced to half with respect to that of the clock signal during calibration time and becomes high during the conversion time. Figure 17 presents the measured waveform of the RST and COMP signals. As the COMP signal stays high during the calibration time ($8\mathrm{CLKs}$), the CAL[4:1] signal becomes ‘1111’ and $▵C_{B,N}$ becomes $\frac{15}{2}{C}_{min}$. These measurement results prove the proper functionality of the binary search calibration algorithm described in Table 1.

The INL and DNL before calibration shown in Figure 18 are measured to be $-2.7/2.5\mathrm{LSB}$ and $-1.4/1.5\mathrm{LSB}$, respectively. On the other hand, the INL and DNL after calibration shown in Figure 19 are measured to be −1.8/1.7 LSB and $-0.7/0.7$ LSB, respectively. Hence, the binary search calibration algorithm enhances the performance of the linearity of the proposed ADC by approximately 1 bit. The measured SNDR (Signal-to-Noise Distortion Ratio) and ENoB before calibration from FFT (Fast Fourier Transform) shown in Figure 20 are $59.24\mathrm{dB}$ and 9.5-bit, respectively. After calibration, SNDR and ENoB are measured to be $64.05\mathrm{dB}$ and 10.3-bit, respectively, as presented in Figure 21. The analog and digital power consumption are measured to be 16.1 and $14.6\mathsf{\mu }\mathrm{W}$, respectively, resulting in a total power dissipation of 30.7 $\mathsf{\mu }\mathrm{W}$.

As the clock frequency varies from $100\mathrm{kHz}$ to $20\mathrm{MHz}$ with the input frequency fixed to $1\mathrm{kHz}$, as shown in Figure 22, the measured ENoB remains at 10.3-bit up to $2\mathrm{MHz}$ and degrades to 8.8-bit afterwards. Figure 23 illustrates that the measured ENoB remains at 10.3-bit up to $20\mathrm{kHz}$ of the input frequency and decreases to 8.2-bit with the clock frequency fixed to $454\mathrm{kHz}$.

A comparison of the static/dynamic performance parameters of the ADC between the proposed work and the conventional ones is made in

Table 2. Performance comparison of the proposed ADC.

	[7]	[8]		[9]	[10]	[11]	[12]		This Work
Process	$180\mathrm{nm}$	$130\mathrm{nm}$		$140\mathrm{nm}$	$40\mathrm{nm}$	$180\mathrm{nm}$	$350\mathrm{nm}$		$28\mathrm{nm}$
Architecture	SAR	TS SS		SAR	SAR	SAR	SAR		SAR
Resolution [bit]	12	12		12	12	12	14		12
Supply voltage [V]	1.2	$3.3/1.2$		1.2	1.0	1.8	1.8		1.0
Sampling rate	$1\mathrm{M}$	$100\mathrm{k}$		$6.25\mathrm{k}$	$1\mathrm{M}$	$200\mathrm{k}$	$100\mathrm{k}$		$454\mathrm{k}$
Calibration	after	before	after	$\mathrm{X}$	$\mathrm{X}$	$\mathrm{X}$	before	after	before	after
ENoB [bit]	10.3	6.2	9.8	9.7	9.9	9.5	9.0	11.5	9.5	10.3
DNL [bit]	N/A	$-1/1.4$	$-1/0.8$	$-1/1.4$	$-1/1.6$	$-1/1.3$	$-1/9$	$-1/1$	$-1.4/1.5$	$-0.7/0.7$
INL [bit]	N/A	$-51/42.3$	$-3.3/4.8$	$-3/3$	$-2.6/4.3$	$-3.45/3.6$	$-18/18$	$-2.6/2.1$	$-2.7/2.5$	$-1.8/1.7$
Power [W]	$103\mathrm{u}$	$62\mathrm{u}$		$0.8\mathrm{u}$	$16.7\mathrm{u}$	$72\mathrm{u}$	$43.4\mathrm{u}$		$30.7\mathrm{u}$
FoM * $[\mathrm{fJ}/\mathrm{step}]$	81.7	696		66	18.1	477	155		53.7

* FoM = [Power] / ($2^{\left[\mathrm{ENoB}\right]}$× [Sampling rate]).

. The authors of [8,12] employed the linear search algorithm and showed a comparable enhancement of INL/DNL and ENoB compared with the proposed work with the binary search algorithm. However, the proposed ADC with faster sampling rate performed with a lower power consumption and FoM. The works of [7,9,10,11] with the resolution of 12-bit and a SAR architecture the same as the proposed one exhibited comparative static/dynamic performances to the proposed one, except for calibration circuitry.

4. Conclusions

This paper proposes a 12-bit SAR ADC with foreground calibration using the binary search algorithm for biomedical signal processing. By incorporating calibration switch control logic into the conventional SAR ADC, the capacitance of the calibration split capacitor is determined within 8 clock signals by the binary search algorithm. The proposed binary search calibration algorithm with 4-bit resolution (CAL[4:1]) and a $▵C_{B,N}$ of $\frac{1}{2}{C}_{min}\left(2\mathrm{fF}\right)$ is approximately 3.75 times faster than the conventional linear search calibration one. The proposed binary search calibration algorithm aims to ensure that the calibrated split capacitance closely matches the desired value, thus achieving optimal performance in the SAR ADC. Since a differential mode is employed in the C-DAC circuit, the linearity and ENoB performance of the proposed ADC are superior to those of the conventional single-ended mode. The proposed SAR ADC is implemented by a CMOS $28\mathrm{nm}$ 1-poly 8-metal process with a supply voltage of $1\mathrm{V}$. The effective layout area excluding bonding pads is $939\times 450\mathsf{\mu }\mathrm{m}$. Measurement results of the proposed ADC after calibration show a power consumption of $30.7\mathsf{\mu }\mathrm{W}$ (analog and digital power of 16.1 and $14.6\mathsf{\mu }\mathrm{W}$, respectively), INL of $-1.8/1.7\mathrm{LSB}$, DNL of −0.7/0.7 LSB, ENoB of 10.3-bit, and FoM of 53.7 $\mathrm{fJ}/$step. The proposed 12-bit ADC with the binary search algorithm is applicable to low-power bio-signal processing and IoT platforms.