Optimized High-Voltage Analog Switch and Its Control Circuit Based on Silicon-on-Insulator Technology

Abstract

In recent years, high-voltage analog switches have been widely used in various fields. To handle complex use scenarios, high-voltage analog switches need to achieve the goals of low on-resistance, high isolation performance, high response speed, and high voltage withstand range. Traditional high-voltage analog switches have issues such as low integration, large area, and slow response speed. This paper uses a super junction MOSFET (SJ-MOS) with a 0.18 μm SOI process and a solid-state relay (SSR) structure to implement a high-voltage analog switch. A gate drive circuit suitable for low gate-source breakdown voltage is proposed to maintain the gate-source voltage, achieving a low on-resistance of 24 Ω and high isolation. Compared with traditional high-voltage analog switches, it achieves higher performance with a smaller area.

1. Introduction

Analog switches, with their advantages of easy integration and isolation properties, are widely used for voltage and current signal transmission. In recent years, they have found extensive applications across various fields, including clinical ultrasound imaging systems, power management systems, motor drivers, battery management systems, and automatic testing systems [1,2,3,4].

In the design and application of electronic systems, switches serve as one of the core components of circuits, with their performance and characteristics directly influencing the efficiency and accuracy of signal processing. Particularly, switches that are structurally similar to low-voltage analog switches are widely utilized for signal path selection and switching due to their unique performance advantages. It is noteworthy that the variation range of analog signals is a critical parameter in practical operations, requiring strict control within the voltage limits that MOS transistors can endure to ensure the circuit’s stable operation and long-term reliability. Consequently, the introduction of high-voltage analog switches has become a crucial solution [5,6]. These switches significantly enhance the circuit’s adaptability to complex signal environments by expanding the voltage range for signal processing, thus providing robust support for the high-performance operation of electronic systems [7,8,9,10].

The high-voltage analog switch control circuit proposed in this paper is designed for PCB board automatic test equipment (ATE). The typical measurement scenario for PCB ATE systems is shown in Figure 1, where the number of test probes connected to the device under test (DUT) can range from hundreds to thousands, and each probe requires two switches. Hence, in practical applications, the widespread deployment of high-voltage analog switch ICs, predominantly employed as signal transmission gateways to individual transducers or for discrete operational purposes, often involves thousands of units that must be independently managed. This vast array of switches inherently poses formidable challenges related to power consumption and space utilization, necessitating innovative strategies for effectively controlling and optimizing their high-voltage operation. Orchestrating seamless control of high-voltage analog switches with stringent power efficiency constraints, purely via electronic methodologies, holds paramount importance for the viable implementation of this circuitry in real-world settings. This endeavor necessitates a holistic approach that meticulously accounts for every switch attribute that could potentially impact the precision of ATE (automatic test equipment) measurements, ensuring that accuracy remains paramount amidst the complexity.

The innovative high-voltage analog switch control circuit, which we introduce in this paper, is ingeniously crafted atop the robust SOI (silicon on insulator) technology platform [11,12,13]. This strategic foundation not only shuns the specter of latch-up effects but also bolsters the circuit’s resilience and reliability [14,15,16]. By leveraging the exceptional high-voltage tolerance inherently possessed by the drain–source junction of the SJ-MOS (Super Junction MOSFET) transistor, our design enables a safely tolerable voltage differential of up to 300 V across the two data transmission terminals of the analog switch. This capability significantly expands the circuit’s operational envelope, catering to a wider range of demanding applications.

Moreover, cognizant of the pressing need for minimal power consumption in practical applications, we have devised a gate-source voltage control mechanism for the high-voltage analog switch that operates with unparalleled energy efficiency. This breakthrough addresses the long-standing challenge of isolating control logic from transmission signals in conventional designs, thereby enhancing signal integrity and reducing crosstalk. The result is a circuit that guarantees unparalleled transmission accuracy, coupled with exceptional circuit reliability, making it an ideal candidate for integration into a myriad of precision-critical systems and applications.

2. Traditional High-Voltage Analog Switch

Traditional high-voltage analog switches, as indispensable core control components in electronic devices, have a fundamental mission of precisely switching and effectively isolating signals under high-voltage environments. In particular, high-voltage analog switches based on solid-state relay (SSR) architecture have emerged as the preferred solution for scenarios requiring stringent high-voltage withstand capabilities, leveraging their unique advantages of no mechanical contacts, ultra-long service life, and exceptional reliability. These switches elegantly employ a pair of vertically mirrored NMOS transistors (such as LDMOS) with superior high-voltage tolerance, enabling flexible switching and precise control of the switch’s state through meticulous regulation of the transistors’ gate-source voltages [17].

However, despite the numerous attractive advantages presented by this design concept in theory, traditional high-voltage analog switch circuits still face non-negligible challenges in practical applications. A primary challenge lies in maintaining the stability of the gate-source voltage, which serves as the cornerstone for ensuring stable switch operation. Unfortunately, fluctuations in input signals directly impact the voltage at the shared source of the two MOS transistors, subsequently causing variations in the gate-source voltage. This not only affects the switch’s conduction efficiency but also potentially threatens the safety margins of the MOS transistors’ voltage withstand capabilities.

To overcome this challenge, designers have to construct complex control circuits that dynamically adjust the gate voltage within safe limits, undoubtedly increasing circuit design complexity and manufacturing costs. Moreover, to achieve both high voltage withstand and stable performance, traditional high-voltage analog switches often necessitate the selection of high-quality components and intricate circuit layouts, further escalating product costs and posing significant challenges for subsequent maintenance and repair work.

For bidirectional high-voltage analog switches catering to high-voltage withstand requirements, the current mainstream adopts the SSR structure, centered on a pair of carefully designed, vertically symmetric, and high-voltage-tolerant NMOS transistors (e.g., LDMOS). During signal transmission, ensuring the stability of the gate-source voltage to maintain the switch’s conduction state and prevent voltage excursions beyond process limits emerges as a central challenge in circuit design.

Although there are various implementation approaches for traditional high-voltage analog switch control circuits, each method is accompanied by non-negligible defects, posing numerous challenges in practical applications. For instance, one of the traditional control methods demonstrated in Figure 2 achieves physical isolation between the control circuit and the switch body through optocouplers, thereby establishing comprehensive electrical isolation between low-power input and high-power output circuits. While this solution effectively isolates the circuits, the complexity of optical components poses challenges to circuit design, not only elevating design difficulty but also reducing integration, as well as increasing the complexity and cost of system design.

On the path of pursuing integration optimization, we have to turn to pure circuit strategies to achieve precise control of high-voltage switches. As shown in Figure 3, a gate-source voltage maintaining circuit based on Zener diodes has been proposed and applied in practice [18]. However, the limitation of this method lies in the inherent current demand of Zener diodes, which inevitably introduces the challenge of current leakage [19]. This not only disturbs the purity of analog signals in the control module but also, during drastic dynamic signal changes, may couple the analog signals back to the control loop, thereby weakening the overall system performance.

To overcome this bottleneck, researchers have taken an alternative path by leveraging the exceptional voltage endurance between gate and source exhibited by field MOS. Through meticulous adjustment of the oxide layer thickness beneath the gate, they successfully developed field MOS devices capable of enduring gate-source voltage differences as high as 300 V [20,21], as depicted in Figure 4. This innovation has extended the analog switch architecture originally designed for low-voltage environments into the high-voltage domain. Nonetheless, amidst the excitement, challenges must be addressed: While field MOS boasts superior voltage endurance, its relatively high on-state resistance compels designers to increase chip area to reduce resistance, exacerbating parasitic capacitance accumulation and subsequently slowing down switching speeds. Furthermore, during turn-off instants, the issue of DC leakage in the common source discharge path becomes particularly pronounced due to limited response speeds.

Given these technical bottlenecks, we urgently need a gate drive solution that can dynamically track changes in source voltage to ensure a constant gate-source voltage, catering to the stringent requirements of high-voltage operating environments. Additionally, considering the critical role of MOS transistors in this scenario, the optimization of their drain-source voltage withstand capabilities, on-resistance, and parasitic capacitance becomes a core consideration in design. After comprehensive consideration of various factors, we have decided to employ SOI (silicon-on-insulator) technology to realize this design. This technology, through oxide buried layers and deep trench isolation techniques, minimizes area while ensuring dual advantages of high breakdown voltage and low leakage current, effectively avoiding the potential latch-up effect in traditional CMOS processes.

However, it is worth noting that despite the numerous advantages offered by SOI technology, it does not inherently achieve high voltage withstand between the gate and source. Therefore, the issue of gate-source voltage withstand must be taken into account during design, as SOI technology itself does not directly address this challenge. Consequently, we must replan and design aspects such as circuit layout, material selection, and process parameter adjustment, aiming to further enhance the performance and reliability of the overall circuit while maintaining high-voltage stability.

3. Voltage Holding Structure for Analog Switch Control

The gate drive circuit proposed in this paper for maintaining the gate-source voltage uses SJ-MOS based on SOI technology. It achieves high-voltage analog switch gate-source voltage holding under low gate-source voltage withstand conditions without relying on Zener diodes, avoiding DC leakage.

As depicted in Figure 5, the proposed gate-source voltage holding circuit includes a high-voltage analog switch and its turn-on and turn-off control circuits. The control signals 1 and 2 are a pair of in-phase control signals generated by a level shifter, with control signal 1 having a logic high of VPP and a logic low of VPP-5V, while control signal 2 has a logic high of 0 V and a logic low of VNN. The Zener diode in the circuit does not work during the switch-on process and is only used for protection.

3.1. Switch-On Control

For the switch-on control part, MP1 and MP2 form a current mirror, and MP3 and MP4 control the circuit operation. When control signal 1 is at a logic low level, the common source potential VCS of the analog switch MOS transistor is sampled through the MP6 source follower, and the forward conduction voltage drop VD of the diode is utilized to achieve voltage boosting. The voltages at nodes V₁ and V₂ are obtained, and their values are determined through calculations based on the threshold voltage of SJ-PMOS:

$$V_1=V_{CS}+V_{THP}+3V_D$$

(1)

$$V_2=V_{CS}+V_{THP}+5V_D$$

(2)

When the common gate voltage VCG of the analog switch MOS transistor is lower than V₂ by a threshold voltage of SJ-NMOS, the current mirror charges the capacitor C1 through MN1. Similarly, when VCG is higher than V₁ by a threshold voltage of SJ-PMOS, C1 discharges through MP5. Therefore, the upper and lower limits of V_CG are:

$$V_{CS}+V_{THP}+5V_D-V_{THN}\le V_{CG}\le V_{CS}+2V_{THP}+3V_D$$

(3)

where $V_{THP}$ is the threshold voltage of SJ-PMOS and $V_{THN}$ is the threshold voltage of SJ-NMOS

$$V_{THP}+5V_D-V_{THN}\le V_{GS}\le 2V_{THP}+3V_D$$

(4)

Under the SOI process, $V_D$ is about 0.8 V, $V_{THP}$ is about 1.3 V, and $V_{THN}$ is about 0.8 V. The expected gate-source voltage limits are $4.5\mathrm{V}\le V_{GS}\le 5\mathrm{V}$. According to the conduction characteristics of SJ-MOS, the on-resistance remains constant when the gate-source voltage exceeds a certain value (about 3 V). Therefore, fluctuations within this range will not cause nonlinear effects on signal transmission.

3.2. Switch-Off Control

For the switch-off control part, MN5 and MN6 form a current mirror, and MN3 and MN4 control the circuit operation. When the gate-source voltage of SJ-MOS is less than 1 V, it can be considered completely off. When control signal 2 is high, the common gate and source of the switch MOS transistor discharge to VNN (−5 V power supply) through MN5 and MN6, reducing the gate-source voltage below the off threshold, achieving switch-off. Additionally, applying a fixed potential to the common source during switch-off can further improve isolation performance.

The switch-off process includes two states: gate-source voltage reduction to switch-off and discharge of the common gate and source. The size of MN6 is larger than MN5, ensuring that the common gate voltage drops faster than the common source during switch-off, allowing the gate-source voltage to quickly drop below the conduction threshold. When the gate-source voltage is below the conduction threshold, the switch is off, but the common gate and source still contain significant charges. From switch-off to discharge, the Zener diode protects against reverse bias voltage during discharge.

3.3. Simplified Application Diagram: Four-Wire Measurement

This paper employs the four-wire resistance measurement method to evaluate the device under test (DUT), with the circuit application diagram being depicted in Figure 6. This diagram illustrates how the four-wire measurement is performed utilizing four probes, with switches PF1, NF2, PS3, and NS4 in the conductive (ON) state and the corresponding switches NF1, PF2, NS3, and PS4 in the non-conductive (OFF) state. The resistance calculation equation of the DUT is as follows:

$$R_{DUT}={\displaystyle \frac{dV}{I_m}}, \mathrm{excluding} \mathrm{contact} \mathrm{resistance} \mathrm{Rc}$$

(5)

where dV represents the voltage difference across the device under test (DUT), and Im is the current flowing through the DUT.

The four-wire resistance measurement method, also known as Kelvin resistance measurement, is a resistance measurement technique specifically designed for high precision and stability. This method ingeniously utilizes four wires to construct the measurement system, with two wires dedicated to injecting a constant current into the resistance under test (current-carrying wires), ensuring a stable and undisturbed current flow. The other two wires precisely capture the voltage drop across the resistance due to the flowing current (voltage-sensing wires), achieving a complete separation between current supply and voltage detection. The essence of this design lies in effectively eliminating interference factors that may be introduced during the test process, such as contact resistance and lead resistance, significantly enhancing measurement accuracy, particularly adept at capturing minute resistance value changes ranging from a few milliohms to several hundred ohms [22]. Additionally, the four-wire method demonstrates outstanding resistance to external interferences, including temperature variations and electromagnetic interferences, which are effectively suppressed, thereby ensuring the stability and reliability of measurement results. As a result, it has become an indispensable high-precision resistance measurement tool in fields such as scientific research and industrial inspection.

4. Simulation and Measurement Results

4.1. Simulation Result and Analysis

After completing the design of the high-voltage analog switch and its control circuit, simulations were conducted to verify and analyze the switch’s transient response, AC impedance, off isolation, and on-resistance characteristics. During the simulation, as mentioned in the previous chapter, control signals 1 and 2 are a pair of in-phase control signals generated by a level shifter. Control signal 1 has a logic high of VPP and a logic low of VPP-5V, whereas control signal 2 has a logic high of 0 V and a logic low of VNN.

4.1.1. Transient Response

The transient response simulation was conducted using a 0.18 μm SOI process, with settings of VPP = 260 V, VNN = −5 V, a corner of TT, and a temperature of 27 °C.The rising and falling edges of the periodic signal Ctrl are configured at ±5 V/ns, with a period of 100 μs. It passes through the level shifter circuit to generate control signals 1 and 2 for the control circuit. Figure 7 illustrates the output variation of the gate-source voltage (VGS) of the high-voltage analog switch during the inversion of the Ctrl signal. As evident from the labeled region A in Figure 7, when Ctrl transitions from 0 V to 5 V, the response time of the switch’s VGS is 0.23 μs, and the establishment time is approximately 0.17 μs, indicating that the full turn-on time of the switch is roughly 0.40 μs. Conversely, when Ctrl transitions from 5 V to 0 V, the VGS response time of the switch is 0.17 μs, with a full turn-off response time of 0.31 μs, and the discharge time between the gate and source electrodes is approximately 2.50 μs. It can be inferred that the proposed high-voltage analog switch in this paper exhibits excellent voltage withstand capability, and the gate drive circuit designed to maintain a constant VGS demonstrates superior response speed and stable control capability under high-voltage conditions.

4.1.2. AC Impedance Testing

In this study, we meticulously selected a sine wave with a peak-to-peak voltage of 2 V as the test signal. Under the condition of a technology corner (TT) and a temperature of 27 °C and VPP = 260 V and VNN = −5 V, we conducted simulation tests on the AC impedance characteristics of the device under test, which comprises a parallel connection of a 1 MΩ resistor and a 1 nF capacitor. For this specific configuration, we performed detailed simulation analyses at two critical frequency points, namely 10 MHz and 25 KHz, with the results being presented in Figure 8 and Figure 9, respectively. From these figures, we can intuitively observe that the efficient gate drive circuit designed in this paper, intended to maintain a constant gate-source voltage (VGS) for high-voltage analog switches, is capable of stably sustaining VGS at a predetermined level (4.5 V ≤ VGS ≤ 5 V), even at a test frequency of 10 MHz, thereby ensuring the accuracy and reliability of the test results. Furthermore, considering the frequency range of AC impedance characteristic tests in practical application scenarios, the highest test frequency involved usually does not exceed 25 KHz. Based on this premise, the innovative analog switch and its accompanying control circuit presented in this paper not only fully meet the expected design specifications but also exhibit exceptional adaptability and performance in practical applications, thoroughly validating the advancement and practicality of their design concepts.

4.1.3. Off Isolation

When integrating multiple switches within a single IC, it is important to ensure that when the switch is off, no AC signal at one terminal couples to the other, facilitating adequate isolation between circuits. This is crucial to prevent interference with adjacent switches and block signal input when the switch is off. The test setup for simulation of off-isolation is shown in Figure 10. With the switch turned off, an AC signal was applied at terminal T1 and the response at T2 was measured. The off isolation was then calculated using the equation:

$$\mathrm{O}\mathrm{f}\mathrm{f} \mathrm{i}\mathrm{s}\mathrm{o}\mathrm{l}\mathrm{a}\mathrm{t}\mathrm{i}\mathrm{o}\mathrm{n}=20\log {\displaystyle \frac{VT2}{VT1}}$$

(6)

where VT1 and VT2 represent the voltage values at the terminals of switches SWA and SWB, respectively.

The off isolation simulation targeted VPP voltage values of 50 V, 100 V, 150 V, and 300 V, using a corner of TT and a temperature of 27 °C, with VNN set to −5 V. The results of this simulation are presented in Figure 11.

It can be seen that when the VPP voltage is set at 50 V, 100 V, 150 V, and 300 V, respectively, the isolation curves for the switch in its off state nearly coincide completely. Especially when the signal frequency is below 10 MHz, the isolation is identical and indistinguishable, demonstrating excellent adaptability and stability. Overall, the curves illustrate in detail that, with the switch closed, applying an AC signal at terminal T1 and measuring the response at T2 results in excellent isolation across the entire depicted frequency range, with the worst-case scenario being −72 dB.

Generally, as the frequency increases, the isolation characteristics tend to degrade gradually. This phenomenon is primarily attributed to the significant impact of parasitic parallel capacitors. The results presented in the figure clearly indicate that the isolation characteristics meet the design requirements outlined in this paper.

4.1.4. On-Resistance

The transient response simulations were carried out under the condition of a technology corner (TT) and a temperature of 27 °C. To objectively verify the switch-on characteristics, independent transient simulation tests were performed on the circuit separately at different voltage and current levels. The following sections present and discuss the tests and results. The simulation test for on-resistance is shown in the following Figure 12. Identical symbols were used for each switch to ease test setup. Given that the main switch devices MNA and MNB have the same size in topology, it is expected that they will all have approximately the same on-resistance. The on-resistance was then calculated using the equation:

$${\mathrm{R}}_{ON}={\displaystyle \frac{VD-VS}{I_m}}={\displaystyle \frac{VDS}{I_m}}$$

(7)

Figure 13 displays the simulated results for various voltages and currents. Specifically, Figure 13a illustrates the simulated waveforms of the switch’s on-resistance when Im is set to 2 mA, VNN is −5 V, and the voltage VPP is varied at 40 V, 150 V, 200 V, and 300 V, respectively. On the other hand, Figure 13b presents the simulated waveforms of the switch’s on-resistance when VPP is fixed at 150 V, VNN is −5 V, and Im is varied at 4 mA, 6 mA, 8 mA, and 10 mA, respectively.

As depicted in Figure 13a, it is clear that regardless of the voltage variations, the switch’s on-resistance remains approximately constant at around 24 ohms, which aligns with our expectations. These results indicate that the switches maintain a consistent on-resistance across a wide range of voltage values. Similarly, the results in Figure 13b show that under varying current conditions, the switch’s on-resistance remains steady at approximately 26 ohms. This demonstrates that the switches exhibit robust and consistent performance with a constant on-resistance across a broad spectrum of voltage and current values.

Table 1. Comparison table of on-resistance values at different voltages.

Parameters	Value
VPP (V)	40 V	150 V	200 V	300 V
VDS (mV)	48.678	48.673	48.667	48.658
Im (mA)	2.0	2.0	2.0	2.0
Ron (Ω)	24.339	24.337	24.334	24.329

and

Table 2. Comparison table of on-resistance at different current levels.

Parameters	Value
VPP (V)	150 V	150 V	150 V	150 V
VDS (mV)	103.988	156.119	208.365	260.725
Im (mA)	4.0	6.0	8.0	10.0
Ron (Ω)	25.997	26.020	26.046	26.073

provide numerical comparisons of the on-resistance values at various voltages and current levels, respectively. From Table 1, it is evident that the maximum on-resistance recorded during the simulation, which is 24.339 Ω, is virtually indistinguishable from the minimum on-resistance of the switch, which is 24.329 Ω. This demonstrates a remarkable stability in the on-resistance values. Similarly, in Table 2, the difference between the maximum and minimum on-resistance values is 0.07 ohms. Overall, the proposed switch exhibits robust and consistent performance in terms of its on-resistance.

4.2. Measurement Results

The high-voltage analog switch chip presented in this paper was implemented using a 0.18 μm SOI process. Figure 14 clearly displays the layout of the high-voltage switches that comprise the 16-channel probe system, including both PF and NF switches, as well as PS and NS switches, together with their associated gate control circuits and level shifters. The layout measures 6766 μm × 6703 μm, and within it, the positions of these high-voltage switches and their circuit control modules are symmetrically arranged. Furthermore, Figure 15 presents micrographs of the high-voltage switches, along with their gate control circuits and level shifters.

After the successful tape-out of the chip designed in this paper, we meticulously selected three chips (IC #1, IC #2, and IC #3) as test subjects, with a primary focus on validating the voltage withstand capabilities of their switching components. By conducting rigorous voltage withstand tests in the off state and using a high precision tester for precise data acquisition, we meticulously plotted a characteristic curve graph that clearly illustrates the relationship between the Vpp (peak-to-peak voltage) and the quiescent current Ipp, as depicted in Figure 16. This graph visually demonstrates that at an operating Vpp voltage of 283 V, the Ipp remains at an acceptable level of approximately 25 nA. However, as the Vpp voltage nears 300 V, the quiescent current Ipp rapidly increases, indicating the critical voltage threshold.

From the above results, it is evident that the proposed IC realizes a wider analog signal range and significantly improves the high-voltage withstand characteristic of the switching components. This advancement ensures that the analog switch can successfully operate under the demanding conditions of a high voltage of 300 V, demonstrating its robustness and reliability for applications requiring high voltage tolerance.

Given the nearly identical characteristics of the three chips, we have selected IC #2 as the representative sample for subsequent transient response and switch on-resistance measurement tests, with all test results being derived from IC #2.

Figure 17 demonstrates the transient response test results of the high-voltage analog switch. The switch-on time is the sum of the switch response time TPLH and the voltage rise time TR, while the switch-off time is the sum of the switch response time TPLH and the voltage fall time TF. The test data from Figure 17 have been sorted into Table 2, which separately records the test data for switches PF0 and PS0 on Probe0 under low-voltage and high-voltage conditions. As evident from

Table 3. Test results of switch-on and switch-off times.

	Probe	TPLH (µs)	TR (µs)	TPHL (µs)	TF (µs)
Low Voltage	PF0	0.74638	0.275515	1.131	8.123
	PS0	0.698264	0.258005	0.790759	8.584
High Voltage	PF0	0.85028	1.89	3.518	53.345
	PS0	0.804665	1.905	3.64	55.376

, under low-voltage conditions, the actual switch-on times for PF0 and PS0 are 1.02 µs and 0.96 µs, respectively, and the switch-off times are 9.25 µs and 9.37 µs, respectively. Comparatively, under high-voltage conditions, the actual switch-on times for PF0 and PS0 are 2.74 µs and 2.71 µs, respectively, while the switch-off times are 56.86 µs and 59.01 µs, respectively. In actual testing, due to the transmission delays inherent in level shifters and triggers, the switch transient response durations (time taken for switch-on or switch-off) are correspondingly longer than the simulation values.

Figure 18 presents a schematic diagram of the test circuit for the on-resistance of the switches, and the test results of the 16-channel probe are shown in Figure 19. The results indicate that the maximum on-resistance value of the switch PF is 53.00 Ω, the minimum is 50 Ω, and the average on-resistance value is 51.38 Ω. For the switch NF, the maximum on-resistance value is 52.30 Ω, the minimum is 49.9 Ω, and the average on-resistance value is 51.11 Ω. Because each individual switch consists of two SJ-NMOS transistors of the same size (refer to the topology in Figure 12), the actual test values of the on-resistance are close to twice the calculated results from Figure 12.

Table 4. Comparison table of high-voltage analog switches.

Title 2	This Work		[14]	[16]	[18]	[23]
	Sim	Test
Process (µm)	0.18 SOI	-	BCD-SOI	0.35 SOI	SOI	0.35
Breakdown voltage (BV)	300	300	250	300	100	120
Ron (Ω)	24	51.11 (2*Ron)	25	-	18	700
Off isolation (dB)	−72@100 MHz	-	−50@1 MHz	-	−50@5 MHz, 10 Vp-p	−34

presents a comparison between the presented high-voltage analog switch and the current state-of-the-art devices of a similar type. The SOI process (CMOS-SOI) employed in this work demonstrates significant advantages over the BCD-SOI process described in [14] in terms of power consumption, switching speed, and integration density. Additionally, the 0.18 μm process adopted here offers a higher integration density compared with those utilized in [20,23]. The withstand voltage capability of this work reaches 300 V, equivalent to that reported in [20] and higher than those mentioned in [14,18,23]. The on-resistance value of this work is close to those cited in [14,18], but lower than that in [23]. Furthermore, the isolation performance of this work can achieve −72 dB at 10 MHz, significantly outperforming other referenced comparisons. The testing, conducted with a variety of signal sources, has confirmed that the design meets the requirements for high isolation performance, low on-resistance, rapid response, and a broad withstand voltage range.

5. Conclusions

This paper proposes a high-voltage analog switch and its control circuit, which adopts a current-mode controlled gate-source voltage-maintaining circuit based on the 0.18 μm SOI process to achieve stable control of the gate-source voltage of the analog switch MOS transistor under low gate-source voltage withstand conditions. The simulation results exhibited optimal isolation across the entire frequency range displayed, with the worst-case scenario exhibiting −72 dB at 10 MHz. Furthermore, even when operating at 10 MHz, the gate-source voltage consistently remained within the range of 4.5 V to 5 V.

Additionally, based on the SOI process, the contradiction between the internal resistance and area of the high-voltage analog switch is resolved, achieving a 24 Ω low on-resistance, fast response, and a high-voltage analog switch with a 300 V withstand voltage range. Despite a 6% deviation between the simulated and tested results of on-resistance, which is attributed to the cumulative effects of precision limitations in manufacturing equipment (such as photolithography machines, etching machines, and ion implantation machines) and precise control of parameters (including temperature, pressure, and time) during the chip manufacturing process, we have confirmed that the IC developed in this paper features a simple structure and stability, rendering it suitable for automated test equipment (ATE) on PCB boards and other high-voltage signal transmission applications.