A 1.2 V, 92 dB Dynamic-Range Delta-Sigma Modulator Based on an Output Swing-Enhanced Gain-Boost Inverter

Abstract

This article presents a third-order, feedforward, single-bit Delta-Sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter for low-voltage low-power applications such as wearable devices, mobile health, and the Internet of Things (IoTs). The proposed output swing-enhanced structure addresses the output-swing reduction in the conventional structure while achieving high DC gain and large output swing simultaneously. Implemented in a 180 nm CMOS process, the entire chip is comprised of a delta-sigma modulator, an oscillator, and a current reference. It achieves 86.1 dB peak SNR and 92 dB dynamic range (DR) with 1.95 kHz signal bandwidth. The whole chip dissipates 54.5 μW, leading to a 167.6 dB Schreier Figure of Merit (FoMs).

1. Introduction

High-resolution analog-to-digital converters (ADCs) are in high demand and are widely used in various mixed-signal systems. In the past decade, the Internet of Things (IoTs), portable devices, and mobile health have developed rapidly. Most of the converters in these applications are charged by batteries or energy harvesters, which offer a limited supply voltage and total power consumption. Therefore, to ensure the high performance and long lifespan of the entire system, low-voltage, low-power ADC design is also essential [1,2,3,4,5].

A widely used architecture for energy-efficient applications is the discrete-time delta-sigma modulator (DTDSM), which achieves high resolution by oversampling and noise-shaping. It is also more insensitive to common circuitry non-idealities. Energy efficiency reflects the overall performance of DTDSM in terms of resolution, power consumption, and bandwidth. Figure of Merit (FoM) is adopted to measure the specific energy efficiency of DTDSM. There are two expressions of FoM: Walden FoM (FoMw) and Schreier FoM (FoMs). For DTDSM, the system noise is mainly thermal noise, which means FoMs is more suitable [6].

In DTDSM, the operational transconductance amplifier (OTA) is typically one of the most power-hungry blocks. Meanwhile, the DC gain of the OTA has a significant impact on the overall performance of the DTDSM. In low-voltage design, threshold voltage does not scale proportionally to the supply voltage to reduce the leakage current of MOS transistors, which limits many classic topologies of OTAs. With the decrease in the power supply voltage, the signal swing of each node in DTDSM becomes smaller, leading to a tight output voltage margin of the integrator. This makes the design of the output swing of the OTA more challenging. Hence, low-voltage high-performance OTA design becomes the bottleneck.

Several topologies have been studied. In [7], a modified recycling folded-cascode OTA is proposed, which is limited by output swing and slew rate. In [8,9], bulk-driven OTAs are proposed, which suffer from linearity degradation and lower frequency response. As an alternative approach to address these issues, inverter-based OTAs have garnered significant attention due to their simple structure, high slew rate, and subthreshold operating characteristics [10,11,12]. However, low DC gain is the major drawback of this structure. Therefore, researchers have also proposed a number of ways to improve it. In [13], a current-starved cascode inverter-based OTA is designed, achieving high DC gain. However, the use of the tail current source limits the output swing. In [14], a three-stage cascade inverter-based OTA is mentioned. It achieves high DC gain but comes with large power consumption and additional Miller compensation circuits. A ring amplifier structure was introduced in [15], but the main issue lies in its poor linear operation in closed-loop circuits. In [16,17], a conventional gain-boost inverter is proposed; it overcomes the low DC gain but results in poor output swing. The structure also requires two threshold voltages of MOS transistors, which limits the subsequent application.

Hence, in order to achieve high DC gain and large output swing simultaneously, this article presents an output swing-enhanced gain-boost inverter. Using the proposed structure, a third-order, feedforward, single-bit DTDSM is also designed. In our previous work [18], the concept of the proposed output swing-enhanced gain-boost inverter was introduced, and the modulator with the simulation results was briefly described. In this article, the principle of the proposed inverter-based OTA is described in an elaborate analysis followed by circuit implementation in detail. The DTDSM is designed and fabricated in a 180 nm CMOS process. It achieves an 86.1 dB peak signal-to-noise ratio (SNR) and a 92 dB dynamic range (DR) in a 1.95 kHz bandwidth while consuming 54.5 μW under a 1.2 V supply, leading to a 167.6 dB FoMs.

The rest of this paper is organized as follows. Section 2 introduces the principle of the gain-boost inverter, including the conventional structure and the proposed output swing-enhanced structure. Section 3 describes the topology design of the proposed DTDSM. Section 4 presents the implementation of the entire circuit, including the third-order, feedforward, single-bit DTDSM, the oscillator, and the current reference. Section 5 reports the measurement results. Section 6 concludes the paper.

2. The Gain-Boost Inverter

2.1. The Conventional Gain-Boost Inverter

Figure 1a shows the conventional gain-boost inverter in [16,17]. Based on the simple cascode inverter shown in Figure 1b, the conventional gain-boost inverter introduces two gain-boost modules (transistors M5~M8). The two modules build up two feedback loops together with transistors M3 and M4, respectively. The DC gain of the conventional gain-boost inverter can be expressed as follows:

$$\begin{array}{c}{A}_{\mathrm{v}}=\left(g_{\mathrm{m}1}+g_{\mathrm{m}2}\right)\left[g_{\mathrm{m}5}\left(r_{\mathrm{o}5}\left|\right|r_{\mathrm{o}7}\right)g_{\mathrm{m}3}{r}_{\mathrm{o}3}{r}_{\mathrm{o}1}\left|\right|g_{\mathrm{m}6}\left(r_{\mathrm{o}6}\left|\right|r_{\mathrm{o}8}\right)g_{\mathrm{m}4}{r}_{\mathrm{o}4}{r}_{\mathrm{o}2}\right]\end{array}$$

(1)

The DC gain of the simple cascode inverter can be expressed as follows:

$$\begin{array}{c}{A}_{\mathrm{v}}=\left(g_{\mathrm{m}1}+g_{\mathrm{m}2}\right)\left(g_{\mathrm{m}3}{r}_{\mathrm{o}3}{r}_{\mathrm{o}1}\left|\right|g_{\mathrm{m}4}{r}_{\mathrm{o}4}{r}_{\mathrm{o}2}\right)\end{array}$$

(2)

Comparing Equations (1) and (2), it can be found that the introduction of the gain-boost modules increases the output impedance. Consequently, the DC gain of the conventional gain-boost inverter is also enhanced.

However, to make M5 and M6 operate in the saturation region, V_A and V_B must be larger than V_th5 and V_th6 (threshold voltage of M5 and M6). In a 180 nm CMOS process, the typical value of V_th is approximately 400~600 mV. In this case, the output swing of the conventional gain-boost inverter can be expressed as follows:

$$\begin{array}{c}{V}_{\mathrm{output}\mathrm{swing}}=V_{\mathrm{DD}}-V_{\mathrm{sat}3}-V_{\mathrm{sat}4}-V_{\mathrm{A}}-V_{\mathrm{B}}\end{array}$$

(3)

V_sat1 and V_sat2 represent the drain-source saturation voltage of M1 and M2, with values approximately equal to 3~4 V_T (thermal voltage, with a value of 27 mV). The output swing of the simple cascode inverter can be expressed as follows:

$$\begin{array}{c}{V}_{\mathrm{output}\mathrm{swing}}=V_{\mathrm{DD}}-V_{\mathrm{sat}1}-V_{\mathrm{sat}2}-V_{\mathrm{sat}3}-V_{\mathrm{sat}4}\end{array}$$

(4)

Comparing Equations (3) and (4), it can be found that the output swing of the conventional structure is determined by V_A and V_B, resulting in a severe output-swing reduction.

To ease this reduction, the conventional gain-boost inverter uses low-V_th devices for M5 and M6, but this approach cannot solve the reduction in principle and will increase process complexity.

2.2. Proposed Output Swing-Enhanced Gain-Boost Inverter

Figure 2a depicts the proposed output swing-enhanced gain-boost inverter. There are three merits that come with this structure, as follows:

• The gain-boost modules used in the proposed gain-boost inverter have a folded-cascode structure, rather than common-source structure used in the conventional gain-boost inverter. The DC gain of the proposed structure can be expressed as follows:

$$\begin{array}{c}\begin{array}{c}{A}_{\mathrm{v}}=\left(g_{\mathrm{m}1}+g_{\mathrm{m}2}\right)\left[A_{\mathrm{v}1}{g}_{\mathrm{m}3}{r}_{\mathrm{o}3}{r}_{\mathrm{o}1}\left|\right|A_{\mathrm{v}2}{g}_{\mathrm{m}4}{r}_{\mathrm{o}4}{r}_{\mathrm{o}2}\right]\\ A_{\mathrm{v}1}=g_{\mathrm{m}5}\left(r_{\mathrm{o}11}\left|\right|g_{\mathrm{m}9}{r}_{\mathrm{o}9}{r}_{\mathrm{o}5}\left|\right|r_{\mathrm{o}7}\right)\\ A_{\mathrm{v}2}=g_{\mathrm{m}6}\left(r_{\mathrm{o}12}\left|\right|g_{\mathrm{m}10}{r}_{\mathrm{o}10}{r}_{\mathrm{o}6}\left|\right|r_{\mathrm{o}8}\right)\end{array}\end{array}$$

(5)

Compared to Equation (1), the folded-cascode structure provides a higher output impedance, so the DC gain of the proposed gain-boost inverter is further enhanced.

• Compared to the conventional structure, M5 changes from NMOS to PMOS, and M6 changes from PMOS to NMOS. At this point, V_A and V_B are free from the restriction of V_th, and the minimum value of V_A and V_B could be V_sat again. As a result, the output swing is enhanced and can be expressed as follows:

$$\begin{array}{c}{V}_{\mathrm{output}\mathrm{swing}}=V_{\mathrm{DD}}-V_{\mathrm{sat}1}-V_{\mathrm{sat}2}-V_{\mathrm{sat}3}-V_{\mathrm{sat}4}\end{array}$$

(6)

Compared to Equation (2), the output-swing reduction is completely overcome.

• The existence of the two branches composed of M9~M12 enables the use of regular-V_th devices throughout the entire structure. If the two branches disappear, as shown in Figure 2b, the drains of M5 and M6 will directly connect to the gates of M3 and M4, respectively. The condition for M3 to M6 to operate in the saturation region is expressed as follows:

$$\begin{array}{c}\mathrm{M}3:V_{\mathrm{X}}-V_{\mathrm{A}}\ge V_{\mathrm{th}3}, \mathrm{M}4:V_{\mathrm{B}}-V_{\mathrm{Y}}\ge \left|V_{\mathrm{th}4}\right|,\mathrm{M}5:V_{\mathrm{DD}}-V_{\mathrm{X}}\ge V_{\mathrm{DD}}-V_{\mathrm{A}}-\left|V_{\mathrm{th}5}\right|, \mathrm{M}6:V_{\mathrm{Y}}\ge V_{\mathrm{B}}-V_{\mathrm{th}6}\end{array}$$

(7)

Equation (8) can be obtained after derivation:

$$\begin{array}{c}\left|V_{\mathrm{th}5}\right|>V_{\mathrm{th}3}, V_{\mathrm{th}6}>\left|V_{\mathrm{th}4}\right|\end{array}$$

(8)

In order to keep M3 to M6 operating in the saturation region and maintain a high DC gain, M5 and M6 need to employ high-V_th devices. The presence of M9–M12 creates a level shift from the source to the drain, separating the gates of M3 and M4 from the drains of M5 and M6. As a result, M5 and M6 can also be guaranteed to operate in the saturated region using regular-V_th devices, which can lower the process complexity of the proposed structure.

Figure 3a shows the frequency-response simulation circuit, and Figure 3b is the frequency-response simulation result of the proposed output swing-enhanced gain-boost inverter. It can be seen that the proposed structure reaches a DC gain of 91 dB with a 2.2 MHz gain bandwidth product (GBW), which meets the modulator’s requirement of DC gain for OTA discussed in Section 3.

Figure 4 shows the simulation result of the output swing versus the DC gain of the conventional structure and the proposed one. As the selected process does not support low-V_th devices, all transistors in the conventional structure use regular-V_th devices. The conventional structure can maintain a DC gain larger than 60 dB over a voltage range of 0.35 V to 0.81 V, resulting in an output swing of 0.46 V. In contrast, the proposed structure can achieve a 0.87 V output swing (from 0.18 V to 1.05 V), representing a 90% improvement.

Table 1. DC gain versus output swing comparison.

	DC Gain/dB	Output Swing/V	Full-Scale Voltage/V	Full-Scale Ratio
Conventional structure (without low-Vth devices)	85	0.46	1.2	38%
Conventional structure in [13] (with low-Vth devices)	83	0.59	1.2	59%
Proposed structure	91	0.87	1.2	73%

compares the proposed structure with the conventional structure using low-V_th devices in [13]. It can be observed that the DC gain is 8 dB higher than the conventional structure, and the output swing realizes a 24% improvement. The supply voltage and power consumption of the proposed structure are 1.2 V and 14.5 μW, respectively.

3. Topology Design of the Proposed DTDSM

To demonstrate the performance advantage of the proposed output swing-enhanced gain-boost inverter, a DTDSM is designed. The main specifications of the proposed modulator are summarized in

Table 2. Main modulator specifications.

Parameters	Value	Unit
Signal bandwidth (BW)	1.95	kHz
Oversampling ratio (OSR)	256	-
Sampling frequency	1	MHz
Full-scale (differential)	1.2	V
Supply voltage	1.2	V

.

The first step is to choose an appropriate topology for the DTDSM. As discussed above, low voltage, low power consumption and high energy efficiency are significant. Compared to the cascade structure, the single-loop structure has lower distortion and is less affected by non-ideal factors of OTAs. In the feedforward structure, the input signal of the first-stage integrator is the difference between the input signal of the modulator and the feedback DAC signal, which is referred to as the residual signal. Compared to the feedback structure, the output swing of each stage of integrator is smaller. Therefore, the feedforward structure is more suitable for low-voltage design. Compared to the nonlinearity caused by a multi-bit quantizer, a single-bit quantizer has inherent higher linearity and a simpler structure, leading to lower power consumption [19]. After comprehensive consideration, this article opts to utilize a single-loop, third-order, feedforward single-bit topology, as illustrated in Figure 5.

Since the finite DC gain of the OTA used in the first-stage integrator will affect the overall performance of the modulator, it is necessary to analyze it. The classic switched-capacitor integrator is shown in Figure 6. The working process is divided into two phases: sampling (when φ1 is high level) and integrating (when φ2 is high level). Taking nth period as the analysis object. During sampling phase, the charge on C_S and C_I can be expressed as:

$$\begin{array}{c}{Q}_{\mathrm{S}1}=C_{\mathrm{S}}{V}_{\mathrm{IN}}\left(n\right), Q_{\mathrm{I}1}=C_{\mathrm{I}}\left(1+\frac{1}{A_{\mathrm{V}}}\right)V_{\mathrm{O}}\left(n\right)\end{array}$$

(9)

During integrating phase, the charge on C_S and C_I can be expressed as:

$$\begin{array}{c}{Q}_{\mathrm{S}2}=\frac{C_{\mathrm{S}}{V}_{\mathrm{O}}\left(n+1\right)}{A_{\mathrm{V}}}, Q_{\mathrm{I}2}=C_{\mathrm{I}}\left(1+\frac{1}{A_{\mathrm{V}}}\right)V_{\mathrm{O}}\left(n+1\right)\end{array}$$

(10)

Since there is no charge leakage during the whole working process, it is obvious that:

$$\begin{array}{c}{Q}_{\mathrm{S}1}+Q_{\mathrm{S}2}=Q_{\mathrm{I}1}+Q_{\mathrm{I}2}\end{array}$$

(11)

After z-transformation, Equation (12) can be obtained as:

$$\begin{array}{c}\frac{V_{\mathrm{O}}\left(z\right)}{V_{\mathrm{IN}}\left(z\right)}=\frac{C_{\mathrm{S}}}{C_{\mathrm{I}}}·\frac{A_{\mathrm{V}}}{A_{\mathrm{V}}+1+C_{\mathrm{S}}/C_{\mathrm{I}}}·\frac{z^{-1}}{1-z^{-1}·\left(1-1/A_{\mathrm{V}}\right)}\end{array}$$

(12)

From the above derivation, it can be seen that the effect of the finite DC gain of the OTA on the integrator includes two parts: gain error and pole shift. Usually, the gain of the OTA is large, so the influence of the gain error is relatively small. However, pole shift affects the pole position of the integrator transfer function; this shift of the pole will introduce the leakage of in-band noise and eventually cause a decrease in the SNR of the modulator.

Through behavioral modeling and simulation, the relationship between the DC gain of the OTA used in the first-stage integrator and SNR can be obtained, as shown in Figure 7. When the DC gain is greater than 60 dB, the SNR of the modulator tends to be stable, so the DC gain of the OTA used in the first-stage integrator of the third-order modulator designed in this paper should larger than 60 dB. According to Figure 2, the proposed output swing-enhanced inverter can achieve a 91 dB peak DC gain, which meets the gain requirement.

The next step is to determine the values of the structure coefficients in Figure 5. The noise-transfer function (NTF) of Figure 5 can be calculated as follows:

$$\begin{array}{c}NTF=\frac{{\left(z-1\right)}^3}{\left(z-0.6694\right)\left(z^2-1.531z+0.6639\right)}=\frac{{\left(z-1\right)}^3}{{\left(z-1\right)}^3+a_1{b}_1{\left(z-1\right)}^2+a_2{c}_1{c}_2\left(z-1\right)+a_3{c}_1{c}_2{c}_3}\end{array}$$

(13)

Since c₁, c₂, and c₃ affect the output swing of each stage of integrator, a parameter scan can be performed on the basis of determining the value of c₁, c₂, and c₃ to finally obtain the values of the rest of the coefficients. Based on the calculation results, the coefficients of the designed modulator are summarized in

Table 3. Coefficients of the designed modulator.

Feedforward Coefficients	Signal Coefficients	Integrator Coefficients
a1 = 4	b1 = 1/5	c1 = 1/5
a2 = 6	b4 = 1	c2 = 1/4
a3 = 5		c3 = 1/6

. All the coefficients are realized in the form of fractions, and the numerator and denominator are integers, which is because the coefficients are realized by the ratio between capacitors in the actual circuit, such as the integrator coefficient corresponding to the ratio of sampling capacitor and integrating capacitor. Thus, capacitance matching can be better achieved by writing these coefficients in the form of easily realized fractions, reducing the error caused by capacitor mismatch.

Figure 8 shows the behavior simulation results of the outputs of each stage of integrator in the modulator under a −3 dBFS sinusoidal input signal. It can be seen that the output swing of the first-stage integrator is limited to 60% of the full-scale voltage. According to Table 1, the proposed gain-boost inverter can maintain a gain of more than 60 dB in the range of 73% full-scale voltage, so it is perfectly suitable for the modulator. Meanwhile, the output swings of the second- and third-stage integrators are relatively small, making the implementation of the second- and third-stage amplifiers easier. This is conducive to reducing the overall power consumption.

4. Circuit Implementation

Despite the third-order, feedforward, single-bit DTDSM, an oscillator and a current reference are also designed to ensure functional integrity.

4.1. Third-Order Delta-Sigma Modulator

As shown in Figure 9, the third-order, feedforward, single-bit modulator is depicted, comprising three inverter-based integrators, a passive adder, and a single-bit quantizer. In order to meet the noise requirements, the sampling capacitor of the first-stage integrator C_S1 can be calculated according to the following formula:

$$\begin{array}{c}{C}_{\mathrm{S}1}=\frac{4kT·{10}^{DR/10}}{OSR·{\left(V_{\mathrm{DD}}/2\right)}^2/2}\end{array}$$

(14)

where k is the Boltzmann constant and T is the absolute temperature. To ensure there is enough of a design margin, the sampling capacitor is set to 4.32 pF. All capacitor values in the circuit were calculated, and they are summarized in

Table 4. Capacitor values in the modulator.

Sampling Capacitors/pF	Integrating Capacitors/pF	Feedforward Capacitors/pF	Common-Mode Capacitors/pF	Compensation Capacitors/pF
Cs1 = 4.32	CI1 = 21.6	CF1 = 0.05	CM1 = 1	Cc1 = 5
Cs2 = 0.125	CI2 = 0.5	CF2 = 0.2	CM2 = 0.16	Cc2 = 1
Cs3 = 0.08	CI3 = 0.48	CF3 = 0.3	CM3 = 0.16	Cc3 = 1
		CF4 = 0.25

. It should be noted that the C_S1 needs 21.6 pF, which occupies the largest area.

4.1.1. Inverter-Based Integrator

The structures of the three inverter-based integrators are all pseudo-differential, as depicted in Figure 9. The first integrator utilizes the proposed gain-boost inverter, as shown in Figure 2a, for optimal performance. To reduce the power dissipation, the second and third integrators adopt the simple cascode inverter, as shown in Figure 1b. An auto-zeroing technique is also introduced [20]. During the φ1 phase, the offset voltage is sampled in capacitor C_c. During the φ2 phase, the input node of the inverter is forced to become a virtual ground, thereby reducing the offset voltage and flicker noise.

To stabilize the output common-mode voltage of integrators at each stage, a low-voltage common-mode feedback (CMFB) loop is formed through capacitor C_M. The advantages of this structure are no additional output load and the restriction of the output swing of the integrator [21].

4.1.2. Bootstrap Switch

In order to improve the linearity of the sampled signal, we utilize a low-voltage bootstrap switches, as depicted in Figure 10 [22], for all switches directly connected to the input signal. By pre-charging capacitor C_boost when the switch is off, the gate-source voltage of M1 can be maintained at a constant V_DD when the switch is on. Therefore, the switch-on resistance of M1 can be expressed as follows:

$$\begin{array}{c}{R}_{\mathrm{on}}=\frac{1}{{\mu }_{\mathrm{n}}{C}_{\mathrm{ox}}\left(W/L\right)\left(V_{\mathrm{DD}}-V_{\mathrm{th}1}\right)}\end{array}$$

(15)

This is independent from input signal V_in. Figure 11 shows the output spectrum of the bootstrap switch. It can be calculated that the SFDR and THD are 97.3 dB and 94.4 dB, respectively.

4.1.3. Single-Bit Quantizer

The comparator is mainly divided into static and dynamic structures. The static structure has a constant current, while the dynamic structure is controlled by the clock, resulting in lower power consumption compared to the static structure. This article focuses on the low-power design of the comparator. Therefore, the two-stage single-bit dynamic comparator shown in Figure 12 is utilized. The first stage is a StrongARM dynamic amplifier [23], and the second stage is an SR latch. When the control signal ENN is set to a low level, the comparator is reset, and the quantization result remains unchanged. When ENN is set to a high level, the comparator initiates the quantization operation. The difference between the differential input pairs is amplified rail-to-rail by the positive feedback loop composed of M3-M6. The quantization result is latched by the second stage.

4.2. Oscillator

The oscillator provides a stable control-clock signal for the entire modulator. For this design, the oscillator needs to meet requirements for low voltage and low power. Therefore, the relaxation oscillator shown in Figure 13 is adopted [24]. The structure generates a clock signal of corresponding frequency by repeatedly charging and discharging capacitors C₁ and C₂ and constantly flipping the output of the comparator. The simulation results of the oscillator are shown in Figure 14. A 1.1 MHz clock under 1.2 V supply voltage is realized, and the power consumption is 2.4 μW.

4.3. Current Reference

As depicted in Figure 2a and Figure 9, both the proposed output swing-enhanced inverter and the oscillator require a precise bias current. Therefore, a current reference is also designed, as shown in Figure 15 [25]. To achieve low-voltage operation and low power consumption, all transistors work in the subthreshold region. In this design, the relationship between the threshold voltage and the channel length is used to achieve the subtle difference between V_th1 and V_th2 (the channel length of M1 and M2 is bL and L, respectively). The existence of M4 and M5 forces the current flowing through M1 and M2 to be equal, which makes V_gs2 − V_gs1 equal to V_th2 − V_th1. Therefore, the reference current can be expressed as:

$$\begin{array}{c}{I}_{\mathrm{ref}}=\frac{V_{\mathrm{th}2}-V_{\mathrm{th}1}}{R_1}=\frac{V_{\mathrm{th}0,2}-V_{\mathrm{th}0,1}-\left(a_2-a_1\right)T}{R_1}\end{array}$$

(16)

where V_th0,1 and V_th0,2 represent the threshold voltages of M1 and M2 at 0 K temperature, respectively. Meanwhile, a₁ and a₂ denote the temperature coefficients of the threshold voltages of M1 and M2, respectively. Since a₁ and a₂ are approximately equal and V_th0 is a constant value, the difference eliminates the temperature coefficient of V_th. Therefore, I_ref can be temperature-independent if R1 has a small temperature coefficient.

The third branch, composed of M3 and M6, forces the voltages of nodes A and B to be equal. This guarantees the current accuracy and significantly enhances the line regulation of I_ref through this additional feedback loop.

Figure 16 shows the simulation result of the low-voltage current reference. It can be seen that the current reference achieves a 1 μA current and a 26 ppm temperature drift in the range of −55~125 °C.

5. Results

The proposed chip is implemented in a 180 nm CMOS process. The microphotograph of the chip is presented in Figure 17, with the layout occupying a core area of 0.405 mm² (900 μm × 450 μm).

Figure 18 shows the test board of the DSM. The power supply part includes an ultra-low-noise linear regulator (LT3045, Analog Devices, Norwood, MA, USA) and a high-precision, low-noise reference (AD780, Analog Devices, Norwood, MA, USA), which, in combination with Agilent, generates a 1.2 V supply voltage and a 0.6 V common mode voltage. A single-ended sinusoidal input signal is generated by a signal generator (Keysight 33600A, Keysight, Santa Rosa, CA, USA). The single-ended input to a differential output circuit in the signal input part changes it into a sinusoidal input signal. The single-ended input to differential output circuit is based on a low-noise fully differential amplifier (THS4551, Texas Instrument, Dallas, TX, USA). The digital output is captured and stored in the logic analyzer (Agilent 16810A, Keysight, Santa Rosa, CA, USA) and then sent to a PC for data processing.

The output spectrum of the proposed modulator is displayed in Figure 19, with a 1.1 Vp-p, 1.4 kHz sinusoidal input signal. It can be observed that the noise floor is −120 dB. The SNR is 86.1 dB. Figure 20 illustrates the measured SNR versus the input signal amplitudes normalized by full-scale voltage. It is evident that the modulator achieves a 92 dB DR. The total power consumption is 54.5 μW.

As mentioned above, using FoMs to fairly compare the overall performance of different modulators [6]:

$$\begin{array}{c}\mathrm{F}\mathrm{o}\mathrm{M}\mathrm{s}=\mathrm{D}\mathrm{R}+10\log \frac{\mathrm{BW}}{\mathrm{Power}}\end{array}$$

(17)

where BW represents the signal bandwidth and Power represents the total power consumption of the chip. The proposed modulator achieves a 167.6 dB FoMs. The results in [18] are pre-simulation results. Compared to [18], the FoMs drop is mainly caused by the following reasons:

• The reduction of SNR is due to the transient noise introduced by devices (mainly MOS, capacitors and resistors) and various parasitic parameters introduced by the layout.
• There is increased noise and power consumption introduced by the current reference and oscillators.

The performance of the proposed modulator is also compared with other published modulators with a supply near 1.2 V in

Table 5. Performance summary of the DSMs with a supply near 1.2 V.

References	This Work	2022 [26]	2021 [27]	2019 [28]	2019 [29]	2016 [30]
Architecture	DT	DT	DT	DT	CT	DT
Process/nm	180	180	90	40	65	180
Supply voltage/V	1.2	1	1.2	1	1	1.1
BW/kHz	1.953	0.2	0.25	100	150	0.3
OSR	256	64	500	128	128	128
DR/dB	92	78.2	95.6	86.7	99.3	86
SNR/dB	86.1	75.26	93	89.7	84.2	85.9
Power/μW	54.5	0.8	30	860	20.8	12
FoMs/dB	167.6	162.18	164.8	167.4	167.8	160

. It can be observed that the proposed modulator is competitive in FoMs.

6. Conclusions

In summary, this article presents a third-order, feedforward, single-bit, delta-sigma analog-to-digital modulator (DSM) based on an output swing-enhanced gain-boost inverter. The proposed output swing-enhanced inverter addresses the output-swing reduction issue of the conventional gain-boost inverter in principle. Therefore, high DC gain and a large output swing can be realized simultaneously. Fabricated in a 180 nm CMOS process, the whole chip contains a delta-sigma modulator, an oscillator, and a current reference. The modulator achieves an 86.1 dB peak SNR with a 1.4 kHz sinusoidal input signal. The DR is 92 dB, and the signal bandwidth is 1.95 kHz. The entire chip dissipates 54.5 μW, leading to 167.6 dB FoMs, and shows competitiveness compared with other modulators with a supply near 1.2 V.