A Charge-Sharing-Based Two-Phase Charging Scheme for Zero-Crossing-Based Integrator Circuits

Abstract

As an effort to improve the energy efficiency of switched-capacitor circuits, zero-crossing- based integrators (ZCBI) that consist of zero-crossing detectors and charging circuits have been proposed. To break the trade-off between accuracy and speed, ZCBI typically employs a two-phase charging scheme that relies on an additional threshold for zero-crossing detection. This paper proposes a simpler realization method of the two-phase charging scheme by means of charge sharing. To demonstrate feasibility of the proposed method, we designed and fabricated a second-order delta-sigma modulator in 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The measurement results show that the modulator exhibits a peak signal-to-noise-and-distortion ratio (SNDR) of 46.3 dB over the bandwidth of 156 kHz with the power consumption of 684 µW. We also designed the same modulator in 65-nm CMOS technology and simulation results imply that the proposed circuit is able to achieve a much better energy efficiency in advanced technology.

1. Introduction

In conventional switched-capacitor integrators, the negative feedback around an operational transconductance amplifer (OTA) with a high DC gain forces the two input terminals to have the same potential, controlling the charge transfer from the sampling capacitor to the feedback capacitor. In advanced technology with a reduced supply voltage, however, achieving the high DC gain is not straightforward. In addition, conventional OTAs are not power efficient due to their typical class-A operation [1,2,3,4]. As an alternative, zero-crossing-based integrator (ZCBI) circuits have been proposed (Figure 1a) [5,6,7,8,9,10,11,12,13,14,15,16], where zero-crossing-detectors (ZCD) and current sources are used to control the charge transfer.

As the timing diagram in Figure 1b shows, the finite delay of the ZCD causes an overshoot at the input of ZCD and consequently at the integrator output. If the current source charges the load with the constant current I, the overshoot voltage at the output of the integrator is given by

$$V_{\mathrm{OVS}}=\frac{I\times t_{\mathrm{d}}}{C_{\mathrm{LD}}},$$

(1)

where $t_{\mathrm{d}}$ is the delay of the ZCD and $C_{\mathrm{LD}}$ is the total capacitance at the output of the integrator [11]. The overshoot voltage manifests itself as a DC offset at the integrator output, which is not detrimental. However, if the charging current is governed by a resistor $R_{\mathrm{S}}$, whether it be the output resistance of a transistor current source or a kind of current source itself, the overshoot voltage has the additional gain error component as expressed in

$$V_{\mathrm{OVS}}=(V_{\mathrm{DD}}-V_{\mathrm{O}})(1-e^{-\frac{t_{\mathrm{d}}}{\tau }}),$$

(2)

where $\tau =R_{\mathrm{S}}{C}_{\mathrm{LD}}$ is the time constant. The gain error term modifies the gain and the pole location of the integrator transfer function. More importantly, the current value at the zero-crossing moment and thus the delay $t_{\mathrm{d}}$ become signal-dependent causing nonlinearity in the overshoot voltage [11]. The nonlinearity due to signal-dependent $t_{\mathrm{d}}$ can be reduced by increasing the time constant, but it comes at the cost of reduced speed of the integrator. The trade-off relationship between speed and accuracy can be alleviated by two-phase charging schemes [5,6,10,11,12,13,14]. In a two-phase charging scheme, the charge transfer phase is divided into two phases: coarse and fine. During the coarse phase, a high current is used to make $V_{\mathrm{X}}$ approach $V_{\mathrm{CM}}$ quickly; then, during the fine phase, a low current is used to reduce the overshoot. Depending on the direction of charging during the fine phase, the two-phase charging scheme can be bidirectional or unidirectional (Figure 2). If the charging scheme is bidirectional, the coarse phase ends when the ZCD detects zero-crossing through the threshold $V_{\mathrm{CM}}$. During the fine phase, the overshoot voltage is compensated for by the low current of the opposite direction. The unidirectional two-phase charging scheme, on the other hand, introduces an additional threshold $V_{\mathrm{th}}$ that is lower than $V_{\mathrm{CM}}$ to decide when to make a transition from the coarse phase to the fine phase. The bidirectional scheme is simpler in a sense that it needs only one ZCD. However, it requires greater headroom to accommodate the large overshoot at the end of the coarse phase. With a low supply voltage, therefore, the unidirectional scheme is preferred over the bidirectional scheme.

In [15], we have shown that charge sharing can be used to implement the unidirectional two-phase charging scheme without an explicit additional ZCD. This paper presents, in more detail, the design of a second-order $\Delta \Sigma$ analog-to-digital convertor (ADC) that employs the proposed two-phase charging scheme and discusses its effectiveness with measurement results. This paper is organized as follows. Section 2 describes the ZCBI structure that employs the proposed two-phase charging scheme. Section 3 presents the circuit implementation of the fabricated second-order $\Delta \Sigma$ modulator and its measurement results. Effectiveness of the proposed scheme is also discussed. In Section 4, conclusions are drawn.

2. Proposed ZCBI Circuit

Unlike the clocked comparator in most ADCs, the ZCD in Figure 1 needs to continuously monitor whether $V_{\mathrm{X}}$ crosses the threshold $V_{\mathrm{CM}}$ or not. Therefore, there is a possibility that the ZCD consumes a great deal of static power. In order to reduce the static power consumption of ZCD, an inverter-based ZCD can be used in lieu of conventional comparator circuits as illustrated in Figure 3[16]. The ZCD consists of an inverter and an auto-zeroing capacitor ($C_{\mathrm{Z}}$). During the sampling phase (${\varphi }_1$ is on), the auto-zeroing capacitor samples the voltage difference between $V_{\mathrm{CM}}$ and the threshold voltage of the inverter. As a result, the inverter output flips when $V_{\mathrm{X}}$ crosses $V_{\mathrm{CM}}$ in the charge transfer phase (${\varphi }_2$ is high). Unfortunately, the inverter output may not be large enough to immediately turn off the current source resulting in a long ZCD delay, especially when the charging current is small. To address this issue, an additional inverter chain is added at the output of the ZCD. However, the inverter chain may increase the effective time delay of the ZCD and it is therefore imperative to make sure that the inverter chain is fast enough to keep the delay as small as possible.

Figure 4 shows our implementation of the inverter-based ZCD, where the inverter is followed by a dynamic buffer. When ${\varphi }_{2\mathrm{rst}}$ goes high for a short period of time at the beginning of the charge transfer phase, ${\mathrm{M}}_2$ is turned on and the gate terminal of ${\mathrm{M}}_3$ is pre-charged to $V_{\mathrm{SS}}$ thus turning on ${\mathrm{M}}_3$. The output node is also reset to $V_{\mathrm{SS}}$ making $V_{\mathrm{X}}$ lower than $V_{\mathrm{CM}}$ in all circumstances. As a result, the inverter output becomes high turning off ${\mathrm{M}}_1$. When $V_{\mathrm{X}}$ crosses $V_{\mathrm{CM}}$, ${\mathrm{M}}_1$ is turned on and it can quickly charge the gate of ${\mathrm{M}}_3$ to turn it off since ${\mathrm{M}}_2$ is already in the off state.

Although the ZCD delay can be reduced to some degree by the use of a dynamic buffer, a two-phase charging scheme still needs to be implemented to break the speed-accuracy trade-off. Figure 5 illustrates the proposed ZCBI circuit that implements a simple unidirectional two-phase charging scheme. The basic idea behind the proposed scheme is to supply a fixed amount of charge during the coarse phase by using a capacitor rather than a current source. It is equivalent to charging by a current source for a fixed duration of the coarse phase. However, the proposed method does not require either an additional ZCD with a different threshold or an additional control signal to make a transition from the coarse to the fine phase. In Figure 5a, $C_{\mathrm{P}}$ is pre-charged to $V_{\mathrm{DD}}$ during the reset phase. When the charge transfer phase starts, $C_{\mathrm{P}}$ is connected to the output node and the charges stored on $C_{\mathrm{P}}$ are shared with other capacitors that are connected to the output node, thus the output voltage being raised instantaneously. After charge sharing, the circuit operates the same way as a conventional two-phase charging scheme in the fine phase. In effect, the charge sharing serves as the coarse phase in a conventional two-phase charging scheme.

For proper operation of the proposed two-phase charging scheme, however, the amount of charge to be shared must be well controlled. If $V_{\mathrm{X}}$ is greater than $V_{\mathrm{CM}}$ at the end of charge sharing, there is no way to discharge the capacitors, ending up with overshoot (Figure 5c). Therefore, the capacitance of $C_{\mathrm{P}}$ should be carefully chosen so that $V_{\mathrm{X}}$ is lower than $V_{\mathrm{CM}}$ under all circumstances when charge sharing is completed. The voltage at the end of charge sharing is expressed as

$$V_{\mathrm{X}}=V_{\mathrm{X}|\mathrm{reset}}+\frac{C_{\mathrm{P}}{C}_{\mathrm{F}}}{C_{\mathrm{P}}{C}_{\mathrm{F}}+C_{\mathrm{L}}{C}_{\mathrm{F}}+C_{\mathrm{S}}{C}_{\mathrm{F}}+C_{\mathrm{S}}{C}_{\mathrm{P}}+C_{\mathrm{S}}{C}_{\mathrm{L}}}{V}_{\mathrm{DD}},$$

(3)

where $V_{\mathrm{X}|\mathrm{reset}}$ is the value of $V_{\mathrm{X}}$ at the end of reset phase and is given by

$$V_{\mathrm{X}|\mathrm{reset}}=\frac{C_{\mathrm{S}}}{C_{\mathrm{S}}+C_{\mathrm{F}}}D{V}_{\mathrm{R}}-\frac{C_{\mathrm{S}}}{C_{\mathrm{S}}+C_{\mathrm{F}}}{v}_{\mathrm{i}}\left[n\right]-\frac{C_{\mathrm{F}}}{C_{\mathrm{S}}+C_{\mathrm{F}}}{v}_{\mathrm{o}}[n-1].$$

(4)

In Equation (4), $D{V}_{\mathrm{R}}$ is the value of the feedback DAC; $v_{\mathrm{i}}$ and $v_{\mathrm{o}}$ are small-signal input and output voltages of the integrator, respectively. Substituting the full-scale value for $D{V}_{\mathrm{R}}$, $v_{\mathrm{i}}$, and $v_{\mathrm{o}}$ gives us the upper bound of $V_{\mathrm{X}|\mathrm{reset}}$, but it is only a loose bound and places more constraint on the size of $C_{\mathrm{p}}$ than required. Alternatively, a more practical value of $C_{\mathrm{p}}$ can be found using the distribution of $V_{\mathrm{X}|\mathrm{reset}}$, which can be obtained as outlined in the next section.

3. Circuit Implementation and Measurement Results

In order to demonstrate feasibility of the proposed technique, a second-order $\Delta \Sigma$ modulator has been fabricated in 180-nm complementary metal–oxide–semiconductor (CMOS) technology. As shown in Figure 6, the modulator is a low-distortion feedforward structure [17] with a 1-bit quantizer. Figure 7 shows the schematic diagram of the modulator. The half-delay integrators are realized with the proposed ZCBI circuits in pseudo differential form, which include switched-capacitor common-mode feedback circuits [18]. The integrator outputs are combined with the modulator input by the adder in front of the 1-bit quantizer. The adder is realized as a switched-capacitor passive adder for low power consumption. The 1-bit quantizer consists of a dynamic latch, which is basically cross-coupled inverters, and ${\mathrm{C}}^2\mathrm{MOS}$ buffers [19]. The internal clock generator (not shown in Figure 7) creates various non-overlapping clock signals. The nominal clock frequency is 10 MHz and the intended oversampling ratio (OSR) is 32. Figure 8 shows the chip micrograph. The modulator core occupies 0.3 mm${}^2$.

Table 1. Summary of design.

Technology	180-nm CMOS
Sampling Frequency	10 MHz
$V_{\mathrm{DD}}$	1.8 V
$V_{\mathrm{CM}}$	0.9 V
$D{V}_{\mathrm{R}}$	0.4 V or 1.4 V
$C_{\mathrm{S},1\mathrm{st}}$, $C_{\mathrm{S},2\mathrm{nd}}$	25 fF
$C_{\mathrm{F},1\mathrm{st}}$, $C_{\mathrm{F},2\mathrm{nd}}$	50 fF, 100 fF
${}^{*}{C}_{\mathrm{Ltot},1\mathrm{st}}$, $C_{\mathrm{Ltot},2\mathrm{nd}}$	300 fF, 500 fF

* $C_{\mathrm{S}}$ and $C_{\mathrm{F}}$ are excluded.

shows the summary of the modulator design.

As described in Section 2, the capacitance for charge sharing should be judiciously chosen for proper operation of the ZCBIs. The modulator in Figure 6 and Figure 7 was simulated with behavioral and transistor-level models for various amplitudes and frequencies of single-tone and multi-tone inputs. Figure 9 shows one instance of the distribution of $V_{\mathrm{X}|\mathrm{reset}}$. In this simulation, $V_{\mathrm{DD}}$ is 1.8 V and $D{V}_{\mathrm{R}}$ is either 0.4 V or 1.4 V. It is shown that $V_{\mathrm{X}|\mathrm{reset}}$ hardly exceeds 0.6 V. Substituting 0.6 V for $V_{\mathrm{X}|\mathrm{reset}}$ in Equation (3) and solving for the condition that $V_{\mathrm{X}}$ is never larger than $V_{\mathrm{CM}}$ at the end of charge sharing yields the constraint on the value of $C_{\mathrm{P}}$. For instance, $C_{\mathrm{F}}$ is $2C_{\mathrm{S}}$ for the first integrator and the condition for $C_{\mathrm{P}}$ is given by

$$C_{\mathrm{P}}\le \frac{11}{9}{C}_{\mathrm{S}}.$$

(5)

The fabricated chip was tested using the measurement setup shown in Figure 10. The PCB includes a single-ended-to-differential conversion circuit, reference voltage generators, and a crystal oscillator for the clock signal. Figure 11a shows the measured power spectral density of the modulator output with a 9.76-kHz 507-mVpp input signal, and Figure 11b shows signal-to-noise ratios (SNRs) and signal-to-noise-and-distortion ratios (SNDRs) for various input amplitudes. From the power spectral density, the second-order noise shaping is clearly seen. Unfortunately, high harmonic tones are also evident. These harmonic components are probably due to a couple of errors in the design: (1) the clock signals for bottom-plate sampling are connected in a wrong way, and (2) the fabricated modulator lacks reference buffers inside the chip. These errors are also believed to have raised the noise floor by about 3 dB. The second-order harmonic is probably due to the unbalanced reference voltages that are externally supplied to the chip. The mismatch between the pseudo-differential signal paths might have also contributed to the even-order harmonics. The measured peak SNR and SNDR are 50.1 dB and 46.3 dB, respectively. The dynamic range is about 56 dB. From process corner simulations, it is expected that the peak SNDR may drop by about 2.4 dB over the process variations. As suggested in Figure 12, the peak SNR and SNDR are also expected to deteriorate as the temperature increases.

The total power consumption is 684 µW from a 1.8-V supply voltage.

Table 2. Power consumption breakdown.

Sub-Block	Power Consumption (µW)	Percentage (%)
1st Integrator	235	34.3
2nd Integrator	229	33.5
Adder	5.6	0.8
Quantizer	5.7	0.8
DAC	0.9	0.1
Clock Genrator	151	22.1
Ref. buffers, etc.	56.8	8.4
Total	684	100

shows the power consumed in each sub-block. The most power-hungry blocks are integrators, and the clock generator also dissipates a considerable amount of power.

Table 3. Performance comparison with other work.

	[11]	[13]	[14]	[16]	This Work
Technology (nm)	45	180	65	160	180	65 ${}^{\left(1\right)}$	65 ${}^{\left(1\right)}$
Supply Voltage (V)	1.1	1.8	1.2	1.0	1.8	1.2	1.2
Sampling Frequency (MHz)	50	2.56	40	0.014 ${}^{\left(2\right)}$	10	10	50
Oversampling Ratio	30	64	8	1	32	32	32
Bandwidth (kHz)	833	20	2500	0.7	156	156	781
Peak SNDR (dB)	47.7	65.3	70.4	N/A	46.3	53.2	53.7
Peak SNR (dB)	52.5	N/A	N/A	81.8	50.1	56.3	56.5
Dynamic Range (dB)	54.3	71	71.3	N/A	56	N/A	56.5
Power Consumption (µW)	630	420	3730	20	684	274	312
${\mathrm{FoM}}_{\mathrm{S}}^{\left(3\right)}$ (dB)	139	142	159	157	130	140.8	148
${\mathrm{FoM}}_{\mathrm{W}}^{\left(4\right)}$ (pJ/conv-step)	1.91	6.98	0.276	1.48	13.2	2.35	0.5

${}^{\left(1\right)}$ Simulation results. Others are from measurements. ${}^{\left(2\right)}$ Self-timed incremental ADC. Translated from the longest conversion time. ${}^{\left(3\right)}$${\mathrm{FoM}}_{\mathrm{S}}=\mathrm{SNDR}\left(\mathrm{dB}\right)+10{log}_{10}(\mathrm{Bandwidth}/\mathrm{Power})$. ${}^{\left(4\right)}$${\mathrm{FoM}}_{\mathrm{W}}=\mathrm{POWER}/(2^{(\mathrm{SNDR}}-1.76)/6.02\times 2\times \mathrm{Bandwidth})$.

summarizes the measured performance in comparison with related works. The figure-of- merit (FoM) of the fabricated modulator is not impressive owing to the aforementioned design errors and the rather high supply voltage. We redesigned the same modulator in 65-nm technology and its performance is also summarized in Table 3. With the lowered supply voltage and improved design, the power consumption is drastically reduced from 684 µW to 274 µW. Furthermore, the sampling frequency can be increased to 50 MHz without degradation of SNR or SNDR, resulting in better FoMs. Even if the SNDR discrepancy of about 5 dB is taken to account between schematic simulation and measurement, the proposed modulator is expected to achieve competitive performance.

4. Conclusions

ZCBI is an attractive alternative to the conventional power-hungry switched-capacitor integrator because the ZCD can be implemented using a simple inverter circuit and auto-zeroing techniques. However, ZCBI is prone to errors caused by the overshoot, and reducing the overshoot results in lower speed in general. In order to break the trade-off between speed and accuracy, a two-phase charging scheme is needed, but it is not straightforward to apply the conventional two-phase charging scheme to the inverter-based ZCD. This paper proposes the use of charge sharing to implement the two-phase charging scheme. The proposed technique is readily applicable to the inverter-based ZCD and is able to reduce the power consumption and the circuit complexity. The proposed charging scheme was applied to a second-order $\Delta \Sigma$ modulator designed in 0.18-µm CMOS technology. The modulator consists of two proposed ZCBIs, a 1-bit quantizer, a 1-bit DAC, and a clock generator. The ZCD for ZCBIs makes use of a dynamic buffer to reduce the delay. Measurement results show that the modulator achieves a 56-dB dynamic range and a 46.3-dB peak SNDR over a 156-kHz in-band bandwidth with a 684-µW power consumption. We also designed the modulator in 65-nm CMOS technology and simulation results suggest that the proposed modulator is likely to achieve better energy efficiency in advanced technology.