A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

Abstract

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power ($P_{sat}$) of 20.7 dBm, a peak PAE of $22.4\%$, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.

1. Introduction

High data rate is one of the key factors for modern 5G communication system design. As conventional UHF band has been occupied, higher frequency bands, such as X-band, are explored by researchers to offer higher data rate communication for 5G applications [1]. Furthermore, X-band has important applications, such as satellite communications and phased-array systems. Thus, X-band communication systems have received a significant attention in recent years [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26].

In the case of X-band PA ICs, many reported designs can achieve watt-level output power, but most of them are implemented with GaAs/GaN process in recent publications [21,22,23,24,25,26], which is not suitable for low cost portable wireless communication systems. For these applications, CMOS technology is the most suitable candidate for high-level integration and low-cost implementation. With the CMOS technology, the device size and the supply voltage are continuously being scaled down to realize better performance with reduced power consumption. However, it creates a challenge for CMOS PA to achieve high output power with compact size, especially for frequencies higher than 6 GHz, such as X-band and millimeter-wave bands.

Most of the reported X-band CMOS PA are implemented with 180 nm CMOS technology [2,3,4,5,6,7,8,10,12,13,18,19], while some others are with 90 [9,11] and 65 nm [20] CMOS technology. On the other hand, the authors of [14,15,16] showed the possibility of using shrinking 45 nm node to implement an X-band PA with reasonable performance. However, these PAs are designed with CMOS SOI process instead of standard CMOS process with complicated power supplies, which notably increase the cost and decrease their possibility to integrate with other blocks of an X-band wireless communication system. The PA reported by [17] is implemented with standard 40 nm CMOS technology, but the PA works on all digital switching mode (class E), which can hardly support modern modulation schemes compared with its counterpart works on linear mode. Furthermore, the PA only supports the lower frequency range (8–9.5 GHz) of the X-band and with a power supply higher than 1 V. The whole list of publications about CMOS PAs covering X-band frequencies is shown in

Table 1. Lists of publications about CMOS power amplifiers covering X-band frequencies.

Reference	Process	Frequency (GHz)	${\mathit{V}}_{\mathit{DD}}$ (V)	Publication Year
[2]	180 nm CMOS	0–14	1.3	2004
[3]	180 nm CMOS	3.1–10.6	1.8	2005
[4]	180 nm CMOS	3–10	2	2006
[5]	180 nm CMOS	3.7–8.8	-	2007
[6]	180 nm CMOS	6–10	1.5	2008
[7]	180 nm CMOS	8.5–10	3.3	2008
[8]	180 nm CMOS	4–17	3.6	2009
[9]	90 nm CMOS	5.2–13	2.8	2010
[10]	180 nm CMOS	7–12	3.6	2010
[11]	90 nm CMOS	5.2–13	-	2010
[12]	180 nm CMOS	6.5–13	3.6	2011
[13]	180 nm CMOS	8.6–10.3	3	2011
[14]	45 nm CMOS SOI	4–50	1.1/6	2012
[15]	45 nm CMOS SOI	9–15	3.6/4.8	2013
[16]	45 nm CMOS SOI	10–32	0.75/1/2	2014
[17]	40 nm	3.5–9.5	1.2	2015
[18]	180 nm	7–10	3.3	2017
[19]	180 nm	3/9	3.6	2018
[20]	65 nm	8–11.4	1.2	2019

.

Some reported two-stage X-band PAs achieved more than 20 dBm output power with 3.6 and 3 V power supplies in [12,13,19], respectively. The power supply voltage in these designs is much higher than 1 V. In addition, a two-way power combining is utilized in these designs, which results in large die size occupation. The CMOS PA reported in [27] uses 1 V power supply and achieves a much higher peak PAE of 34.5%, but it works in switching mode. Thus, it can hardly supports modern modulation schemes, which require high linearity. Two other reported X-band PAs [7,20] achieve high output power utilizing two-stage cascode with TMN architecture. These two PAs achieve peak PAE of 24.5% and 19%, respectively.

In this paper, a two-stage X-band PA in 40-nm standard CMOS technology is presented. With shrinking process node, it can offer better integration capability compared with other X-band CMOS PA designs. Instead of switch mode, the proposed PA works in linear mode. This ensures the proposed PA can support any modulation scheme without limitations [28]. The proposed PA is implemented with a transformer-based matching network (TMN) to provide more degrees of design freedom, while occupying similar chip area as a single inductor [29]. While operating at $V_{DD}=1$ V, the proposed PA has achieved a saturated output power of 20.7 dBm and 22.4% peak PAE at 10 GHz (23.5% peak PAE at 11 GHz). The PA also achieves an EC [20] of 117.5, which is among the best EC performances in recently reported X-band PAs in CMOS technology.

The structure of this article is as follows. Section 2.1 provides the architecture of proposed power amplifier. Section 2.2 discusses design procedure of transistor cells. Section 2.3 discusses matching network design among input GSG pads, transistor cells, and output GSG pads. Section 3 gives a photograph of the fabrication and measured results of the PA. The conclusion and references are in Section 4.

2. PA Design

2.1. PA Architecture

Figure 1 presents the schematic of the proposed PA. The PA consists of a driving stage and a power stage. Both the driving stage and the power stage are biased to linear mode instead of switching mode for better linearity. The driver stage is biased to class A operation for high gain, whereas the power stage is biased to class AB operation for high efficiency. Both the driving stage and the power stage consist of two NMOS transistors and work in differential modes.

For output and inter-stage matching network, a transformer T-model was used to fulfill matching procedure on Smith Chart. The transformer in the output matching network also works as a balun to transform differential input into single-ended output. On the other hand, for input matching network, the resonator-based design procedure was used for wider bandwidth consideration. The transformer in the input matching network works as a balun to transform single-ended input into differential output as well. Furthermore, both the input and output are connected to GSG pads with 100 $\mathsf{\mu }$m pitch in the chip layout.

2.2. Design of Transistor Cells

Transistor size of the power stage should be carefully chosen for PA design, as their size can determine output power and maximum PAE [12]. In this design, the unit transistor size is set to be 3 $\mathsf{\mu }$m × 32 $\mathsf{\mu }$m. Then, DC IV sweep is simulated based on the unit transistor size to determine the biasing voltage for each stage. Here, $V_{b1}$ and $V_{b2}$ in Figure 1 are set for class A and class AB operating condition, respectively. The multiplier of unit transistor cell is determined through several times of iterations of load pull simulations, in order to make the output power higher than 20 dBm. Here, the multiplier is set to be 20 for the transistor size of the power stage. After that, the transistor size of the driving stage is determined to be half the size of the power stage. In other words, the transistor size of the driving stage is 3 $\mathsf{\mu }$m × 32 $\mathsf{\mu }$m × 10 $\mathsf{\mu }$m.

Once the transistor size is fixed, the neutralization capacitors are determined based on $S_{12}$ performance of the differential pairs. The schematic used to tune neutralization capacitors is shown in Figure 2. The capacitor value is used when the best isolation performance is observed, i.e., when the smallest $S_{12}$ value is observed. In this design, the neutralization capacitors of the power stage are set to be $382fF$, and the neutralization capacitors of the driving stage are set to be $193fF$.

When the transistor size and the neutralization capacitors are fixed, both the input and output impedance of each stage can be extracted by load pull simulation, as shown in Figure 3 [30]. In Figure 3, both the input source impedance $R_{in}$ and the output load impedance $R_{out}$ are 50 $\mathsf{\Omega }$.

2.3. PA Matching Network Design

In the proposed design, transformers are used in matching networks. This is for compact size and convenient DC biasing, while occupying similar die area when compared to circuits with inductors [29].

The PA design is based on UMC’s 40-nm CMOS technology, and its metal layer definition is shown in Figure 4. There are two thick metal layer in the top: Al_RDL (2.8 $\mathsf{\mu }$m) and M7 (3.4 $\mathsf{\mu }$m). All other layers (M1–M6) are thin metal layers. In this design, the top two thick metal layers are used for transformer layout, and thin metal layers are only considered as interconnections when the two thick metal layers are not available.

2.3.1. Inter-Stage/Output Matching Network Design

For inter-stage matching network, instead of using optimal impedance obtained from load pull simulation, the conjugate of output impedance of the driving stage is used to simplify the design procedure. Normally, optimal impedance extracted from load pull and conjugate of output impedance are quite close to each other. Furthermore, as transistors of the driving stage are chosen to be half the size of those in the last stage, output power of the driving stage is far from $P_{1dB}$ point. Thus, it is possible to get maximum current and maximum voltage swing simultaneously. In this condition, load pull is not necessary, and using the conjugate of output impedance as matching target for input impedance of the power stage is more desirable.

The schematic about how impedance are extracted for inter-stage matching is shown in Figure 5. Here, $Z_{out1}=10.7-j2.9$$\mathsf{\Omega }$ and $Z_{in2}=1.5-j19.1$$\mathsf{\Omega }$ (extracted under large signal S-parameter simulation). Thus, the inter-stage matching network should match the conjugate of output impedance of the driving stage ($Z_{out1}^{\ast }=10.7+j2.9$$\mathsf{\Omega }$) to the input impedance $Z_{in2}$ of the power stage. The transformer T-model is used for inter-stage matching network design, with the same technique stated in [31]. The proposed T-model and its equivalent transformer with Smith chart demonstration is shown in Figure 6, where the relation between mutual inductance M and coupling factor K is given by Equation (1).

$$K=\frac{M}{\sqrt{L_P\ast L_S}}$$

(1)

As there is only a transformer T-model, the inter-stage matching network can be realized with merely a transformer. In Figure 6, $L_P=674$ pH, $L_S=392$ pH, and $M=243$ pH. The EM setup with layout of the inter-stage transformer is shown in Figure 7. Then, parameters of the transformer are extracted based on s4p file get from EM simulation. Testbench for parameter extraction is shown in Figure 8. Based on S-parameter simulation of the testbench with two extraction ports, the extracted parameter results are given by Equations (2)–(4), where f is the central frequency of 10 GHz.

$$L_P=\frac{Imag\left(Z_{11}\right)}{2\ast \pi \ast f}$$

(2)

$$L_S=\frac{Imag\left(Z_{22}\right)}{2\ast \pi \ast f}$$

(3)

$$M=\frac{Imag\left(Z_{21}\right)}{2\ast \pi \ast f}$$

(4)

The inter-stage transformer is implemented with stacked Al_RDL and M7. M7 is also used as interconnections of the secondary coil, and primary coil is implemented with Al_RDL instead of stacked layers when the interconnections go through. The transformer is enclosed with ground for isolation.

Similar as inter-stage matching network, the output matching network is also designed with transformer T-model, as shown in Figure 9 [31].

Considering the fact that the output matching network is connected with GSG pads (100 $\mathsf{\mu }$m pitch). The parasitic capacitor of the the GSG $C_{pad}$ should be simulated, and considered as part of the $C_s$ in Figure 9. The EM simulation setup with ADS Momentum is shown in Figure 10. With EM simulation, $C_{pad}=43fF$ is extracted. Thus, a parallel capacitor $C_s^{{}^{\prime }}$ is placed next to the output GSG pads, as calculated in Equation (5). In the setup, two ground pads are connected together with a narrow metal track. This ensures parasitic capacitors between both sides of ground pad to signal pad can be accounted for.

$$C_s^{{}^{\prime }}=C_s-C_{pad}$$

(5)

2.3.2. Input Matching Network Design

The input matching network is designed when all the other parts of the PA have been determined. It is designed as a Magnetically Coupled Resonator (MCR), as we discussed in [31]. The MCR design technique gives us flexibility to tune the bandwidth and passband ripple of the matching network with coupling factor of the transformer. The schematic of the input matching network is shown in Figure 11. Similar to the output matching network, parasitic capacitor $C_{pad1}$ of the GSG pads is added as part of the input capacitor.

In Figure 11, $L_1=208$ pH, $L_2=558$ pH, and $K_1=0.27$ pH. Considering the fact that the input balun is with single-ended input and differential output, its transformer parameter extraction method is different from that of the inter-stage transformer. The EM setup with layout of the input transformer is shown in Figure 12. Then, parameters of the transformer are extracted based on s3p file get from EM simulation. Testbench for parameter extraction is shown in Figure 13. Similar to inter-stage transformer, the extracted inductance of primary and secondary coil and mutual inductance are calculated with Equations (2)–(4).

3. Fabrication and Measurement

A chip photograph of the fabricated PA is shown in Figure 14, and the chip size without pads is 0.90 mm × 0.37 mm (1.00 mm × 0.46 mm with pads).

Figure 15 compares the measured gain, output power and PAE performance of the PA versus input power for frequency range 8–12 GHz in steps of 2 GHz. Figure 16 shows measured results of the maximum output power (Pout), output 1 dB gain compression point (OP1dB), and peak PAE from 8 to 12 GHz in steps of 1 GHz of the PA. The PA achieves a peak gain of 25.6 dB, OP1dB of 13.7 dBm, and peak PAE of 22.4% at 10 GHz. The maximum peak PAE of 23.5% is obtained at 11 GHz.

To assess the capability of the transistors in generating output power to the load with a variety of power supply, an EC defined in millisiemens (mS) [20] was used.

$$G_S=P_{out}/V_{DD}^2$$

(6)

The proposed PA is compared with previously published state-of-the-art X-band CMOS PAs, as shown in

Table 2. Summary and comparison of proposed PA and previously published X-band CMOS PA with similar architecture.

Reference	Technology	Frequency, GHz	Technique	${\mathit{P}}_{\mathit{sat}}$, dBm	Gain, dB	${\mathit{V}}_{\mathit{DD}}$, V	PAE, %	EC, mS
[20]	65 nm CMOS	8.0–11.4	Two-stage cascode	20.5	24.4	1.2	24.5	77.9
[12]	0.18 $\mathsf{\mu }$m CMOS	6.5–13.0	Two-stage push-pull	21.5	25.3	3.3	20.3	13.0
[13]	0.18 $\mathsf{\mu }$m CMOS	8.6–10.3	Two-stage with 2-way power combining	24.5	25.0	3.0	24.5	31.3
[7]	0.18 $\mathsf{\mu }$m CMOS	8.5–10.0	Two-stage cascode	23.5	29.0	3.3	19.0	20.6
This work	40 nm CMOS	8.0–12.0	Two-stage TF-coupled	20.7	25.6	1.0	23.5	117.5

. The comparison shows that our work has one of the best EC performances, while still being competitive in terms of output power, gain, and PAE when compared to the previously published works.

4. Conclusions

In this work, an X-band CMOS power amplifier using UMC’s 40-nm standard CMOS technology is presented. The shrinking process node supports higher integration with other building blocks, compared with other X-band CMOS PA designs with larger process node. The PA works in a linear mode to support modern modulation schemes. It consists of a driving stage and a power stage with transformer-based matching networks. Both the driving stage and the power stage are made of differential transistor cells with neutralization capacitors to enhance their stability and gain. The PA is among the designs with the best EC performance when compared with several CMOS X-band PAs with similar architecture. It also attains a saturated output power ($P_{sat}$) of 20.7 dBm, a gain of 25.6 dB, and a peak PAE of $22.4\%$ at 10 GHz under a 1 V supply in 40-nm CMOS.