Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design
Abstract
:1. Introduction
1.1. Motivation
1.2. Our Approach and Contributions
- A high-accuracy surrogate model for circuit optimization with low-computational effort compared with circuit simulations.
- The use of Gaussian processes regression models for high accuracy prediction of device parameters across corners based on the technology characterization.
- A flexible optimization framework easily configurable for different fabrication processes, circuit topologies, and optimization algorithms.
2. Multi-Objective Constrained Optimization for Automatic Circuit Design
2.1. Multi-Objective Optimization
2.1.1. Gradient-Based Optimization Algorithms
2.1.2. Evolutionary Optimization Algorithms
2.2. Analog Circuit Design as an Optimization Problem
3. Proposed Surrogate Model for Optimization-Based EDA Tools
3.1. General Optimization Architecture
- The Gaussian process regression models of parameters of the process technology trained from characterization data.
- The physics-based model of the parameters of the MOS transistor.
- The circuit equations of the performance metrics of the circuit topology.
3.2. Advanced Compact MOSFET (ACM) Model
3.3. Gaussian Process-Based Regression Models of the Process Characterization
3.3.1. Characterization of the Parameters of CMOS Transistors
3.3.2. Gaussian-Processes-Based Regression Models
3.4. Circuit Performance Equation-Based Model
3.5. Process Variations-Aware Automatic Design
4. Experimental Results
4.1. Error of the GPR-Based Surrogate Model
4.2. Experimental Setup
4.3. Active-RC Second Order Filter
4.3.1. Surrogate of the Filter’s Performance Metrics
4.3.2. Results of Filter’s Automatic Design
4.4. Capacitor-Less Low-Dropout (CL-LDO) Voltage Regulator
4.4.1. Surrogate of the LDO’s Performance Metrics
4.4.2. Results of the LDO’s Automatic Design
4.5. Current-Starved Voltage Controlled Oscillator (CSVCO)
4.5.1. Surrogate of the CSVCO’s Performance Metrics
4.5.2. Results of the CSVCO’s Automatic Design
4.6. Summary
5. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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NMOS | PMOS | NMOS | PMOS | NMOS | PMOS | NMOS | PMOS | |
---|---|---|---|---|---|---|---|---|
KernelFunc | Exp. | ArdExp. | ArdExp. | ArdExp. | Exp. | Exp. | Exp. | ArdExp. |
BasisFunc | Linear | None | Constant | None | Constant | Constant | None | None |
FitMethod | Fic | Fic | Sr | Sr | Sd | Sd | Fic | Sr |
ActiveSetMethod | Sgma | Sgma | Random | Random | Entropy | Random | Sgma | Random |
PredictMethod | Exact | Exact | Exact | Exact | Exact | Exact | Exact | Exact |
ResubLoss | 1.37 × 10 | 3.5 × 10 | 6.26 × 10 | 11.52 × 10 | 5.18 × 10 | 2.35 × 10 | 6.29 × 10 | 2.47 × 10 |
Parameter of the Algorithm | SQP | NSGA-II |
---|---|---|
Algorithm implementation | fmincon: sqp [36] | NSGA2 toolbox [25] |
Multi-start/Runs | 10 | 10 |
Stop criteria | Function tolerance = 1 × 10 | Max. generations = 500 |
Max. Fun. evaluations = 8 × 10 | Population size = 30 | |
Other parameters | Max. iterations = 2 × 10 | Dist. index for crossover = 20 |
Constraint tolerance = 1 × 10 | Dist. index for mutation = 20 |
Parameter | Spec | |||||||||
---|---|---|---|---|---|---|---|---|---|---|
Min | Mean | Max | Min | Mean | Max | Min | Mean | Max | ||
[dB] | >40 | 55.54 | 57.59 | 61.35 | 52.21 | 55.69 | 58.58 | 42.47 | 45.65 | 49.24 |
>10 | 19.28 | 20.98 | 31.87 | 13.59 | 15.03 | 16.26 | 11.71 | 12.27 | 13.34 | |
[°] | >40 | 42.17 | 45.49 | 48.16 | 42.31 | 45.75 | 49.21 | 44.62 | 46.91 | 48.68 |
[V] | >0.6 | 1.14 | 1.18 | 1.23 | 1.11 | 1.20 | 1.30 | 0.76 | 0.85 | 0.95 |
[V] | >1 | 1.29 | 1.36 | 1.65 | 1.25 | 1.32 | 1.37 | 1.39 | 1.43 | 1.47 |
[V/s] | >0.4 | 2.13 | 2.38 | 3.63 | 10.40 | 12.24 | 15.06 | 85.84 | 91.49 | 103.63 |
0.56 | 0.66 | 1.15 | 4.73 | 5.53 | 6.41 | 56.02 | 57.15 | 60.07 | ||
[V/] | <2 | 0.89 | 1.04 | 1.22 | 1.22 | 1.34 | 1.41 | 1.05 | 1.11 | 1.18 |
Process | PSR@1 kHz | PSR@10 kHz | PSR@100 kHz | PM | |||||
---|---|---|---|---|---|---|---|---|---|
TSMC 180 nm | 1.8 V | 1.6 V | 100 pF | 533.3 A | 5.3 mA | <−50 dB | <−45 dB | <−25 dB | >45° |
IBM 130 nm | 1.2 V | 1 V | 100 pF | 333.3 A | 3.3 mA | <−40 dB | <−40 dB | <−25 dB | >45° |
TSMC 65 nm | 1.2 V | 1 V | 100 pF | 333.3 A | 3.3 mA | <−40 dB | <−40 dB | <−25 dB | >45° |
Metric | Spec. | Low Load | High Load | ||||
---|---|---|---|---|---|---|---|
Min | Mean | Max | Min | Mean | Max | ||
|PSR@1kHz| [dB] | >40 | 40.26 | 48.81 | 54.40 | 48.62 | 54.08 | 63.18 |
|PSR@10kHz| [dB] | >40 | 40.04 | 45.58 | 50.71 | 44.77 | 48.67 | 54.41 |
|PSR@100kHz |[dB] | >25 | 27.87 | 30.99 | 34.51 | 27.02 | 30.74 | 35.29 |
Phase Margin [°] | >45 | 49.33 | 59.91 | 68.62 | 73.40 | 81.07 | 85.64 |
Metric | Spec. | Low Load | High Load | ||||
---|---|---|---|---|---|---|---|
Min | Mean | Max | Min | Mean | Max | ||
|PSR@1kHz| [dB] | >40 | 40.37 | 48.97 | 59.72 | 45.78 | 56.67 | 74.05 |
|PSR@10kHz| [dB] | >40 | 40.19 | 47.12 | 54.45 | 45.31 | 50.60 | 56.27 |
|PSR@100kHz |[dB] | >25 | 31.54 | 33.75 | 36.49 | 31.71 | 33.93 | 37.06 |
Phase margin [°] | >45 | 50.39 | 53.32 | 55.99 | 70.85 | 73.78 | 77.42 |
Circuit | No. of Design Variables | No. of Constraints | Evaluation Time Surrogate [s] | Evaluation Time Simulation [s] | Evaluation Time Improvement |
---|---|---|---|---|---|
Filter | 9 | 21 | |||
LDO | 10 | 24 | |||
VCO | 7 | 15 | 18 |
Circuit | TSMC180 | IBM130 | TSMC65 | |||
---|---|---|---|---|---|---|
SQP | NSGA-II | SQP | NSGA-II | SQP | NSGA-II | |
Filter | 90.48% | 68.57% | 100.00% | 100.00% | 57.14% | 100.00% |
LDO | 76.67% | 70.00% | 70.00% | 83.33% | 56.67% | 75.45% |
VCO | 60.00% | 66.67% | 70.00% | 93.33% | 86.67% | 60.00% |
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Sanabria-Borbón, A.C.; Soto-Aguilar, S.; Estrada-López, J.J.; Allaire, D.; Sánchez-Sinencio, E. Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design. Electronics 2020, 9, 685. https://doi.org/10.3390/electronics9040685
Sanabria-Borbón AC, Soto-Aguilar S, Estrada-López JJ, Allaire D, Sánchez-Sinencio E. Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design. Electronics. 2020; 9(4):685. https://doi.org/10.3390/electronics9040685
Chicago/Turabian StyleSanabria-Borbón, Adriana C., Sergio Soto-Aguilar, Johan J. Estrada-López, Douglas Allaire, and Edgar Sánchez-Sinencio. 2020. "Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design" Electronics 9, no. 4: 685. https://doi.org/10.3390/electronics9040685
APA StyleSanabria-Borbón, A. C., Soto-Aguilar, S., Estrada-López, J. J., Allaire, D., & Sánchez-Sinencio, E. (2020). Gaussian-Process-Based Surrogate for Optimization-Aided and Process-Variations-Aware Analog Circuit Design. Electronics, 9(4), 685. https://doi.org/10.3390/electronics9040685