On Model Order Reduction of Interconnect Circuit Network: A Fast and Accurate Method

Round 1

Reviewer 1 Report

>For proper notation (page 1, line 16), the IC acronym should be explained (like next in the same sentence).

>The list of references is not formatted correctly.

>The introduction should present other issues related to ICN and model reduction methods.

>The symbols used in mathematical expressions should be carefully described.

>The integral interval (firstly defined in equation (6)) needs additional information (influence on stability and precision of calculations).

>Does the formula (2) takes into account all phenomena observed in circuit? Have you introduced some simplifications?

>Method of T determination should be shortly described (section 4.1).

>Details of algorithm implementation is needed (I have noticed only Python language).

>Have you performed figures using Matplotlib?

>Table 1 shows significant time reduction. Can you asses the error in relation to real solution? Is it acceptable?

Author Response

Please see the Response Letter. Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

General Comments:

This paper deals with the model-order reduction of interconnection circuit networks to facilitate numerical computations and presents a low-order model that can perform fast simulation. Time domain is considered. The main idea is to replace the state function of the original system using Taylor series approximation, where the solution of complex ordinary differential equations of a large interconnection network is transformed into the solution of the (much simpler) linear equations. The topic is important in computer simulation of VLSI circuits and the proposed model is useful.

Specific Comments:

1. Section 4.1: The process of reaching at the optimal value of T is unclear. Please explain it with details.
2. Section 4.2: There should be an optimal order that can balance between running time and error.
3. Performance of the proposed method:

1. There should be a comment (or analysis) on the performance of the proposed method in some other circuits and other numbers of bits.
2. There should be a comparison in performance (error-time tradeoff) with some existing methods.

Author Response

Please see the attachment. Please see the Response Letter.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

The Authors have carefully addressed all of the Reviewers’ concerns. The current version is useful and suitable for publication in MDPI Mathematics.

Author Response

Thank you for your careful review and constructive comments, and thank you again for your approval.