Hardware Limitations of Lightweight Cryptographic Designs for IoT in Healthcare
Abstract
:1. Introduction
2. IoT-Based Healthcare
Basic IoT Protocols
3. Architecture of Lightweight Block Ciphers
Hardware Implementation Analysis of Block Ciphers
4. Architecture of Lightweight Stream Ciphers
Hardware Implementation Analysis of Stream Ciphers
5. Designs of Hash Functions, MACs and Authenticated Schemes
5.1. Hardware Implementation Analysis of Hash Functions
5.2. Hardware Implementation Analysis of MACs and Authenticated Encryption Schemes
6. Comparison Results
7. Conclusions and Outlook
Author Contributions
Funding
Institutional Review Board Statement
Informed Consent Statement
Data Availability Statement
Conflicts of Interest
References
- Fei, H. Security and Privacy in Internet of Things (IoTs): Models, Algorithms, and Implemenations; CRC Press: Boca Raton, FL, USA, 2016; ISBN 9781498723183. [Google Scholar]
- Tsantikidou, K.; Sklavos, N. Vulnerabilities of Internet of Things, for Healthcare Devices and Applications. In Proceedings of the ΙΕΕΕ 8th NAFOSTED Conference on Information and Computer Science (NICS’21), Hanoi City, Vietnam, 21–22 December 2021. [Google Scholar]
- Khan, M.N.; Rao, A.; Camtepe, S. Lightweight Cryptographic Protocols for IoT-Constrained Devices: A Survey. IEEE Internet Things J. 2021, 8, 4132–4156. [Google Scholar]
- Latif, M.A.; Ahmad, M.B.; Khan, M.K. A Review on Key Management and Lightweight Cryptography for IoT. In Proceedings of the 2020 Global Conference on Wireless and Optical Technologies (GCWOT), Malaga, Spain, 6–8 October 2020; pp. 1–7. [Google Scholar]
- Harbi, Y.; Aliouat, Z.; Refoufi, A.; Harous, S. Recent Security Trends in Internet of Things: A Comprehensive Survey. IEEE Access 2021, 9, 113292–113314. [Google Scholar]
- Dutta, I.K.; Ghosh, B.; Bayoumi, M. Lightweight Cryptography for Internet of Insecure Things: A Survey. In Proceedings of the 2019 IEEE 9th Annual Computing and Communication Workshop and Conference (CCWC), Las Vegas, NV, USA, 7–9 January 2019; pp. 0475–0481. [Google Scholar]
- Shah, A.; Engineer, M. A Survey of Lightweight Cryptographic Algorithms for IoT-Based Applications. In Smart Innovations in Communication and Computational Sciences. Advances in Intelligent Systems and Computing; Tiwari, S., Trivedi, M., Mishra, K., Misra, A., Kumar, K., Eds.; Springer: Singapore, 2019; Volume 851. [Google Scholar]
- Thakor, V.A.; Razzaque, M.A.; Khandaker, M.R.A. Lightweight Cryptography Algorithms for Resource-Constrained IoT Devices: A Review, Comparison and Research Opportunities. IEEE Access 2021, 9, 28177–28193. [Google Scholar]
- Dhanda, S.S.; Singh, B.; Jindal, P. Lightweight Cryptography: A Solution to Secure IoT. Wirel. Pers. Commun. 2020, 112, 1947–1980. [Google Scholar]
- Rana, M.; Mamun, Q.; Islam, R. Lightweight cryptography in IoT networks: A survey. Future Gener. Comput. Syst. 2022, 129, 77–89. [Google Scholar]
- Al-Jaroodi, J.; Mohamed, N.; Abukhousa, E. Health 4.0: On the Way to Realizing the Healthcare of the Future. IEEE Access 2020, 8, 211189–211210. [Google Scholar]
- Khanam, S.; Ahmedy, I.B.; Idna Idris, M.Y.; Jaward, M.H.; Bin Md Sabri, A.Q. A Survey of Security Challenges, Attacks Taxonomy and Advanced Countermeasures in the Internet of Things. IEEE Access 2020, 8, 219709–219743. [Google Scholar]
- Cynthia, J.; Parveen Sultana, H.; Saroja, M.N.; Senthil, J. Security Protocols for IoT. In Ubiquitous Computing and Computing Security of IoT. Studies in Big Data; Jeyanthi, N., Abraham, A., Mcheick, H., Eds.; Springer: Cham, Switzerland, 2019; Volume 47. [Google Scholar]
- Jienan, D.; Xiangning, C.; Shuai, C. Overview of Application Layer Protocol of Internet of Things. In Proceedings of the 2021 IEEE 6th International Conference on Computer and Communication Systems (ICCCS), Chengdu, China, 23–26 April 2021; pp. 922–926. [Google Scholar]
- Shahbazi, K.; Ko, S.-B. Area-Efficient Nano-AES Implementation for Internet-of-Things Devices. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2021, 29, 136–148. [Google Scholar]
- Lata, K.; Saini, S. Hardware Software Co-Simulation of an AES-128 based Data Encryption in Image Processing Systems for the Internet of Things Environment. In Proceedings of the 2020 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), Chennai, India, 14–16 December 2020; pp. 260–264. [Google Scholar]
- Gunasekaran, M.; Rahul, K.; Yachareni, S. Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization. In Proceedings of the 2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS), Toronto, ON, Canada, 21–24 April 2021; pp. 1–6. [Google Scholar]
- Cheng, X.; Zhu, H.; Xu, Y.; Zhang, Y.; Xiao, H.; Zhang, Z. A reconfigurable and compact hardware architecture of CLEFIA block cipher with multi-configuration. Microelectron. J. 2021, 114, 105144. [Google Scholar]
- Pyrgas, L.; Kitsos, P. A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT Systems. In Proceedings of the 2019 22nd Euromicro Conference on Digital System Design (DSD), Kallithea, Greece, 28–30 August 2019; pp. 624–627. [Google Scholar]
- Yasir; Wu, N.; Yahya, M.R.; Bi, Q. Area-Efficient Architectures of KASUMI Block Cipher. In Proceedings of the 2018 21st Saudi Computer Society National Computer Conference (NCC), Riyadh, Saudi Arabia, 25–26 April 2018; pp. 1–6. [Google Scholar]
- Madani, M.; Tanougast, C. FPGA implementation of an enhanced chaotic-KASUMI block cipher. Microprocess. Microsyst. 2021, 80, 103644. [Google Scholar]
- Mishra, Z.; Nath, P.K.; Acharya, B. High throughput unified architecture of LEA algorithm for image encryption. Microprocess. Microsyst. 2020, 78, 103214. [Google Scholar]
- Rashidi, B. Flexible structures of lightweight block ciphers PRESENT, SIMON and LED. IET Circuits Devices Syst. 2020, 14, 369–380. [Google Scholar]
- Al-Shatari, M.; Hussin, F.A.; Aziz, A.A.; Witjaksono, G.; Rohmad, M.S.; Tran, X.-T. An Efficient Implementation of LED Block Cipher on FPGA. In Proceedings of the 2019 First International Conference of Intelligent Computing and Engineering (ICOICE), Hadhramout, Yemen, 15–16 December 2019; pp. 1–5. [Google Scholar]
- Ramu, G.; Mishra, Z.; Acharya, B. Hardware implementation of Piccolo Encryption Algorithm for constrained RFID application. In Proceedings of the 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), Jaipur, India, 13–15 March 2019; pp. 85–89. [Google Scholar]
- Mhaouch, A.; Elhamzi, W.; Atri, M. Lightweight Hardware Architectures for the Piccolo Block Cipher in FPGA. In Proceedings of the 2020 5th International Conference on Advanced Technologies for Signal and Image Processing (ATSIP), Sousse, Tunisia, 2–5 September 2020; pp. 1–4. [Google Scholar]
- Yu, X.; Wu, N.; Zhou, F.; Zhang, J.; Zhang, X. A Compact Hardware Implementation for the SCA-resistant PRESENT Cipher. In Proceedings of the IECON 2019—45th Annual Conference of the IEEE Industrial Electronics Society, Lisbon, Portugal, 14–17 October 2019; pp. 5463–5468. [Google Scholar]
- Dalmasso, L.; Bruguier, F.; Benoit, P.; Torres, L. Evaluation of SPN-Based Lightweight Crypto-Ciphers. IEEE Access 2019, 7, 10559–10567. [Google Scholar]
- Pandey, J.G.; Laddha, A.; Samaddar, S.D. A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA. In Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India, 23–25 July 2020; pp. 1–6. [Google Scholar]
- Nallathambi, B.; Palanivel, K. Fault diagnosis architecture for SKINNY family of block ciphers. Microprocess. Microsyst. 2020, 77, 103202. [Google Scholar]
- Taneja, S.; Alioto, M. Deep Sub-pJ/Bit Low-Area Energy-Security Scalable SIMON Crypto-Core in 40 nm. In Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 12–14 October 2020; pp. 1–5. [Google Scholar]
- Madani, M.; Tanougast, C. FPGA implementation of an optimized A5/3 encryption algorithm. Microprocess. Microsyst. 2020, 78, 103212. [Google Scholar]
- Pfau, J.; Reuter, M.; Harbaum, T.; Hofmann, K.; Becker, J. A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8/12/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit/s. In Proceedings of the 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 3–6 September 2019; pp. 294–299. [Google Scholar]
- Li, B.; Liu, M.; Lin, D. FPGA implementations of Grain v1, Mickey 2.0, Trivium, Lizard and Plantlet. Microprocess. Microsyst. 2020, 78, 103210. [Google Scholar]
- Madani, M.; Benkhaddra, I.; Tanougast, C.; Chitroub, S.; Sieler, L. FPGA implementation of an enhanced SNOW-3G stream cipher based on a hyperchaotic system. In Proceedings of the 2017 4th International Conference on Control, Decision and Information Technologies (CoDIT), Barcelona, Spain, 5–7April 2017; pp. 1168–1173. [Google Scholar]
- Madani, M.; Tanougast, C. Combined and Robust SNOW-ZUC Algorithm Based on Chaotic System. In Proceedings of the 2018 International Conference on Cyber Security and Protection of Digital Services (Cyber Security), Glasgow, UK, 11–12 June 2018; pp. 1–7. [Google Scholar]
- Wang, Y.; Wu, L.; Zhang, X.; Xu, K.; Yang, W. A Hardware Implementation of ZUC-256 Stream Cipher. In Proceedings of the 2020 IEEE 14th International Conference on Anti-counterfeiting, Security, and Identification (ASID), Xiamen, China, 30 October–1 November 2020; pp. 94–97. [Google Scholar]
- Yang, Y.; Zhao, W.; Xiong, L.; Wang, N.; Ma, Y. Optimized Implementations for ZUC-256 on FPGA. Wirel. Pers. Commun. 2021, 116, 2615–2632. [Google Scholar]
- Zidaric, N.; Aagaard, M.; Gong, G. Hardware Optimizations and Analysis for the WG-16 Cipher with Tower Field Arithmetic. IEEE Trans. Comput. 2019, 68, 67–82. [Google Scholar]
- Pyrgas, L.; Kitsos, P. An 8-bit Compact Architecture of Lesamnta-LW Hash Function for Constrained Devices. In Proceedings of the 2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Genoa, Italy, 27–29 November 2019; pp. 743–746. [Google Scholar]
- Lara-Nino, C.A.; Morales-Sandoval, M.; Diaz-Perez, A. Small lightweight hash functions in FPGA. In Proceedings of the 2018 IEEE 9th Latin American Symposium on Circuits Systems (LASCAS), Puerto Vallarta, Mexico, 25–28 February 2018; pp. 1–4. [Google Scholar]
- Al-Shatari, M.O.A.; Hussin, F.A.; Aziz, A.A.; Witjaksono, G.; Tran, X.-T. FPGA-Based Lightweight Hardware Architecture of the PHOTON Hash Function for IoT Edge Devices. IEEE Access 2020, 8, 207610–207618. [Google Scholar]
- Abbas, Y.A.; Jidin, R.; Jamil, N.; Z’aba, M.R.; Al-Azawi, S. Small Footprint Mix-Column Serial for PHOTON and LED Lightweight Cryptography. In Proceedings of the 2018 International Conference on Advanced Science and Engineering (ICOASE), Duhok, Iraq, 9–11 October 2018; pp. 70–74. [Google Scholar]
- AlTawy, R.; Rohit, R.; He, M.; Mandal, K.; Yang, G.; Gong, G. Towards a Cryptographic Minimal Design: The sLiSCP Family of Permutations. IEEE Trans. Comput. 2018, 67, 1341–1358. [Google Scholar]
- Carel, G.; Isshiki, R.; Kusaka, T.; Nogami, Y.; Araki, S. Design of a Message Authentication Protocol for CAN FD Based on Chaskey Lightweight MAC. In Proceedings of the 2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW), Takayama, Japan, 27–30 November 2018; pp. 267–271. [Google Scholar]
- Saldamli, G.; Ertaul, L.; Shankaralingappa, A. Analysis of Lightweight Message Authentication Codes for IoT Environments. In Proceedings of the 2019 Fourth International Conference on Fog and Mobile Edge Computing (FMEC), Rome, Italy, 10–13 June 2019; pp. 235–240. [Google Scholar]
- Diehl, W.; Farahmand, F.; Abdulgadir, A.; Kaps, J.-P.; Gaj, K. Face-off between the CAESAR Lightweight Finalists: ACORN vs. Ascon. In Proceedings of the 2018 International Conference on Field-Programmable Technology (FPT), Naha, Japan, 10–14 December 2018; pp. 330–333. [Google Scholar]
- Katsaiti, M.; Sklavos, N. Implementation Efficiency and Alternations, on CAESAR Finalists: AEGIS Approach. In Proceedings of the 2018 IEEE 16th Intl Conf on Dependable, Autonomic and Secure Computing, 16th Intl Conf on Pervasive Intelligence and Computing, 4th Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress (DASC/PiCom / DataCom / CyberSciTech), Athens, Greece, 12–15 August 2018; pp. 661–665. [Google Scholar]
- Khan, S.; Lee, W.-K.; Hwang, S.O. Scalable and Efficient Hardware Architectures for Authenticated Encryption in IoT Applications. IEEE Internet Things J. 2021, 8, 11260–11275. [Google Scholar] [CrossRef]
- Abbas, A.; Mostafa, H.; Mohieldin, A.N. Low Area and Low Power Implementation for CAESAR Authenticated Ciphers. In Proceedings of the 2018 New Generation of CAS (NGCAS), Valletta, Malta, 20–23 November 2018; pp. 49–52. [Google Scholar]
- Kumar, S.; Haj-Yahya, J.; Chattopadhyay, A. Efficient Hardware Accelerator for NORX Authenticated Encryption. In Proceedings of the 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, 27–30 May 2018; pp. 1–5. [Google Scholar]
- Arribas, V.; Nikova, S.; Rijmen, V. Guards in Action: First-Order SCA Secure Implementations of Ketje Without Additional Randomness. In Proceedings of the 2018 21st Euromicro Conference on Digital System Design (DSD), Prague, Czech Republic, 29–31 August 2018; pp. 492–499. [Google Scholar]
Block Ciphers | Device | Structure | Key Size (bit) | Clock Cycles 1 | Area | LUTs | Freq. MHz | Throughput Mbps | Power |
---|---|---|---|---|---|---|---|---|---|
nanoAES [15] | TSMC-65 NM | AES with 8 bit datapath | 128 | 527 | 11.7(x103 μm3) | - | 100 | - | 245.6 μW |
AES-128 [16] | Virtex-5 | Loop unrolled/ FSM-based | 128 | - | - | 20402/ 14798 | 332.34/ 272.33 | 4342/3485 | - |
AES-256 [17] | Virtex7 | Reusing S-box and mix-column blocks | 256 | 74 | - | 1814 | 161 | 278 | 0.58 W |
CLEFIA [18] | Artix-7 | Iterative | 128/192/ 256 | 19/23/ 27 | 506 slices | 1725 | 147 | 990/818 /696 | - |
CLEFIA [19] | ARTIX-7 | 4 bit architecture | 128 | 526 | - | 606 | 115 | 28 | 83 mW |
KASUMI [20] | CMOS 0.18 μm | Low-area S9/S7 s-box | 64 | 16/59 2 | 2487/2294 gates | - | 214 | 32.4/4.6 | - |
KASUMI [21] | Virtex-5 | Simplification/ chaotic generator | 128/ 526 | 8 | 468/1112 slices | - | 644.33/59.45 | 5154.64/475.60 | - |
LEA [22] | UMC 0.09-μm | Unified architecture | 128/192/ 256 | 25/29/ 33 | 11080 GE | - | 740 | 3788 @100KHz | 2.65 mW 3 |
LED [23] | CMOS 180nm | Flexible | 64/128 | 33/49 | 3556 GE | - | 100 | 680.3/ 1010.1 | 8.751 mW 3 |
LED-64 [24] | Kintex7/ Artix7 /Spartan3 | Round-based | 64/64/64 | 32/32/ 32 | 122/91/114 slices | 273/191/ 274 | 485/439/ 167 | 971.58/879.44/ 334.68 | - |
Piccolo-80 [25] | Virtex5/Spartan3 | Compact | 80 | 26 | 194/282 slices | 372/ 535 | 280.9/ 132.25 | 691.54/ 325.54 | 0.699/0.183 W |
Piccolo [26] | Spartan-3 | Iterative/serial 4 bits | 128/128 | 31/496 | 397/265 slices | 757/442 | 81.82/45.85 | 168.9/5.92 | - |
PRESENT-16/64 [27] | Kintex-7 | Optimized threshold design | 80 | 129/- | 197/447 slices | 570/ 860 | 342.83/ 445.33 | 170.09/ 919.39 | - |
PRESENT-80/128 [28] | Kintex-7 | Using 256–150 slice MUXs | 80/128 | - | 68/101– 75/123 slices | 246/205– 271/210 | 639/741– 624/740 | 1319.22/1529.80– 1288.26/ 1527.74 | 40.93/22.88— 42.69/24.87 pJ/bit |
Rectangle [29] | Virtex-5 | Optimized | 80 | 100 | 81 slices | 281 | 390.78 | 250.098 | 721.04 mW |
Rectangle [29] | CMOS 180nm | Optimized | 80 | 100 | 2375.64 GE | - | 200 | 250 | 5.0876 mW |
SKINNY [30] | Virtex-7 | Pipelined with fault detection | 64/128/ 192 | - | - | 2965/ 3802 /5176 | 768/ 691 /597 | 49150/ 44220 /38210 | |
SKINNY [30] | Virtex-7 | Pipelined with fault detection | 128/256/ 384 | - | - | 10407/ 14072 /16926 | 560/ 547 /545 | 71680/ 70020 /69760 | - |
SIMON [31] | Silicon 40 nm | Round-parallel | 64/256 | - | 0.70E6 F/- | - | 530 | 5302/ 132.53 | 0.98 mW |
Stream Ciphers | Device | Structure | Key Size (bit) | Slices | LUTs | Freq. MHz | Throughput Mbps | Power |
---|---|---|---|---|---|---|---|---|
A5/3 [32] | Virtex-5 | One optimized KASUMI cipher block | 128 | 987 | 1877 | 250 | 2000 | 1.46 W |
ChaCha8 [33] | Virtex 7 | Pipeline with DSPs and depth = 1 or 2 | - | 2867/2819 | 4556/5633 | 281.2/356.3 | 134090/169870 | - |
ChaCha8 [33] | Virtex 7 | Pipeline with no DSPs and depth = 1 or 2 | - | 2982/4075 | 9138/10101 | 368.7/356.3 | 175820/169870 | - |
Grain v1 [34] | Spartan-7 | Serial version1/version2 | 80 | 26/35 | 66/76 | 250/313 | 250/313 | - |
Grain v1 [34] | Spartan-7 | Basic/parallel | 80 | 62/111 | 198/361 | 333/250 | 333/4000 | - |
LIZARD [34] | Spartan-7 | Serial v1/v2 | 100 | 60/71 | 106/109 | 100/208 | 100/208 | - |
LIZARD [34] | Spartan-7 | Basic/parallel | 100 | 108/150 | 304/466 | 277/200 | 277/1200 | - |
Mickey 2.0 [34] | Spartan-7 | Basic v1/v2 | 80 | 78/107 | 258/370 | 250/384 | 250/384 | - |
Mickey 2.0 [34] | Spartan-7 | Serial v1/v2 | 80 | 51/70 | 171/205 | 250/384 | 250/384 | - |
SNOW 3G [35] | Virtex-5 | HC-PRNG 1 | 128 | - | 7881 | 28.84 | 922.88 | 1.36 W |
SNOW-ZUC [36] | Virtex-5 | With chaotic generator | - | - | 10602 | 21.201 | 678.432 | 1.467 W |
ZUC-256 [37] | Altera DE2-115 | Pipelined | 256 | - | - | 115 | 3680 | |
ZUC-256 [38] | Spartan-6 | CO-LFSR/SRO algorithms 2 | 256 | 718 | 2494 | 209.346 | 6540 | - |
Trivium [34] | Spartan-7 | Serial v1/v2 | 80 | 15/22 | 42/49 | 256/385 | 256/385 | - |
Trivium [34] | Spartan-7 | Basic/parallel | 80 | 71/133 | 200/446 | 416/344 | 416/22016 | - |
WG(16,32) [39] | Spartan-6 | Algebraic optimizations | - | 631 | 1906 | 256 | - | - |
Hash Functions | Device | Structure | Clock Cycles 1 | Area | LUTs | Freq. MHz | Throughput Mbps | Power |
---|---|---|---|---|---|---|---|---|
Lesamnta-LW [40] | Artix-7 | Serial and shared operations | 768 | - | 434 | 161 | 50 | 99 mW |
LHash-96 [41] | Spartan-3 | Less CPR 2 and higher I/O rates | 414 | 203 slices | 380 | 97 | 60.12 | 28.89 mW 3 |
Spongent-88 [41] | Spartan-3 | Loop with single register | 1980 | 74 slices | 104 | 227 | 29.32 | 28.06 mW 3 |
PHOTON-80/20/16 [42] | Spartan-3/Artix-7 | Round-based | 60/60 | 265/145 slices | 510/ 363 | 157.24/ 376.43 | 262.07/ 627.38 | 27/82 mW |
PHOTON-80 [43] | Spartan-3 | Optimized mix-column | - | 165 slices | - | 93.13 | 9313 | - |
sLiSCP-192/256 [44] | CMOS 65 nm | Parallel | 108/ 144 | 2271/3019 GE | - | 100 (kHz) | 29.62/44.44 (kbps) | 4.62/5.88 μW |
MACs | Device | Message Size | Key Size | Execution Time | Memory KB | Throughput | Power |
---|---|---|---|---|---|---|---|
Chaskey-8/12 rounds [45] | Arduino M0 Pro | 344 bit | 128 bit | 33/42 μs | 16.3/ 16.6 | - | - |
Chaskey [46] | NUCLEO-F401RE | 512 bytes | 128 bit | 99 ms | 22 | 1.308 1 (Kbits/sec) | 3713.32 1 (μJoules/bit) |
LightMAC [46] | NUCLEO-F401RE | 512 bytes | 128 bit | 0.946 ms | 34.5 | 1414.178 1 (Kbits/sec) | 3.434 1 (μJoules/bit) |
Authenticated Encryption Schemes | Device | Structure | Area | LUTs | Freq. MHz | Throughput Mbps | Power |
---|---|---|---|---|---|---|---|
ACORN-1/-32 [47] | Spartan-6 | Threshold implementation | - | 784/4072 | 156.6/111.5 | 78.3/1784 | 8.6/27.4 |
AEGIS-128L [48] | Virtex-7 | Loop Rolling/pipeline | 7726/10610 slices | - | - | 64497/88564 | - |
Ascorn-128 [49] | Spartan-6 | Round-based 1 /serialized 2 | - | 2.72k /1.41k | 147.228 /217.042 | 392.61/12.05 | 20/19 |
Ascorn-128a [49] | Spartan-6 | Round-based 1/serialized 2 | - | 2.93k /1.92k | 146.163 /218.052 | 719.53/21.70 | 22/21 |
NORX [50] | Virtex-7 | Low-area optimization | 326 slices | - | 250 | 3 (Gb/Sec) | 53 3 |
NORX [51] | TSMC 65nm | Various optimizations | 70.13 KGE | - | 757.57 | 83110 | - |
KETJE [52] | NanGate 45nm | JR/SR/MINOR | 18335/35136/73516 GE | - | 892.85/892.85/ 909.1 | - | 2.08/3.63/7.75 |
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |
© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).
Share and Cite
Tsantikidou, K.; Sklavos, N. Hardware Limitations of Lightweight Cryptographic Designs for IoT in Healthcare. Cryptography 2022, 6, 45. https://doi.org/10.3390/cryptography6030045
Tsantikidou K, Sklavos N. Hardware Limitations of Lightweight Cryptographic Designs for IoT in Healthcare. Cryptography. 2022; 6(3):45. https://doi.org/10.3390/cryptography6030045
Chicago/Turabian StyleTsantikidou, Kyriaki, and Nicolas Sklavos. 2022. "Hardware Limitations of Lightweight Cryptographic Designs for IoT in Healthcare" Cryptography 6, no. 3: 45. https://doi.org/10.3390/cryptography6030045
APA StyleTsantikidou, K., & Sklavos, N. (2022). Hardware Limitations of Lightweight Cryptographic Designs for IoT in Healthcare. Cryptography, 6(3), 45. https://doi.org/10.3390/cryptography6030045