Bias Temperature Instabilities in Modern Transistor Technologies

Dear Colleagues,

The high performant and reliable function of microelectronic devices, such as single transistors, is essential for long-term failure safe operation of complex electrical circuits. Although the performance and also the geometry of integrated metal-oxide-semiconductor (MOS) transistors have been continuously improved all MOS transistors suffer from imperfections at the atomic level which can emerge as electrically active sites, so-called defects. On one hand, these defects are unavoidably introduced during device fabrication, and on the other hand new defects can become created during device operation at nominal bias conditions. The impact of the defects on the device performance itself manifests as a drift of the performance of the MOS transistors over time. In this context the so-called bias temperature instability (BTI), which emerges as a drift of the threshold voltage of a transistor, is an essential criterion for determining the reliability of devices. Although lots of efforts have been put in understanding this phenomenon and also in developing suitable models to explain the observed device performance degradation behaviour, the detailed physical mechanisms behind BTI are still controversially debated.

In principle, BTI can be analysed in two fundamentally different manners. The first one is the investigation of large-area devices where continuous drifts of the threshold voltage resulting from the superposition of the contributions of many defects can be studied. This enables to calibrate analytical models and compact models, which are for instance important for efficient circuit simulation. The second approach is to analyse random telegraph noise (RTN) signals and to investigate single-defects by employing nanoscale devices. By doing so the charge trapping kinetics of single defects can be studied, which is vital for the development of physical defect models, which further enable an accurate lifetime estimation under various operating conditions.

However, a continuous improvement of our understanding of BTI is not only essential for further optimization of silicon transistors, but also for the improvement of the performance of emerging technologies such as devices based on wide bandgap materials like SiC or GaN, but also for novel 2D transistors employing graphene, MoS₂ and many other 2D materials. In addition to the challenges evolving for the physical understanding of the observations, the study of novel material systems also poses a major challenge for suitable characterization techniques and measurement instruments, such as the requirement of high-speed measurement techniques (fast IDVG or fast CV methods), but also the need for ultra-low noise systems enabling to investigate trap assisted tunnelling, to mention a few.

Given the wide diversity of approaches to explore the physical mechanism behind BTI for various material systems and applications the aim of this Special Issue is to provide a platform for scientist from different disciplines to publish their latest advancements and reviews in this direction. This especially includes in addition to the development of experimental techniques and models also the latest examination of low temperature BTI effects in Si transistors, BTI in vertical SiC transistors, but also BTI related effects in devices based on 2D materials.

Dr. Michael Waltl
Guest Editor

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• Transistor reliability
• Bias temperature instabilities (BTI)
• Hot carrier degradation (HDC)
• Characterization and modeling of trap assisted tunneling (TAT)
• Random telegraph noise (RTN)
• Noise in semiconductor devices
• Time-dependent defect spectroscopy (TDDS)
• Characterization of transistors
• Measurement instruments and characterization techniques
• Reliability of wide bandgap SiC and GaN devices
• Defects in transistors employing 2D materials