2.1. The Harvesting Module
Incident RF power in the standard 868 MHz band (scavenged or intentionally transmitted) is captured from the environment by a rectifying antenna, or rectenna, which converts it into DC power. Due to the unregulated nature of the output voltage and current, and to the strong dependence of the output voltage on the load current, a power management module is also required to regulate, store, and distribute the harvested power to the sensor node.
2.1.1. Rectenna
This section describes the rectenna unit we devised and reports on its performance.
Figure 2 shows a photo of the discrete-component prototype: it consists of a PIFA (Planar Inverted F Antenna)-like printed antenna which is matched to the RF detector input port by means of a multistage distributed-element matching network.
The first step towards rectenna optimization is antenna design. To satisfy the space constraints of typical sensors for WSN applications [
19,
20], we selected a compact PIFA-like antenna designed to operate in the 868 MHz band (
Figure 2). The topology is similar to that proposed for a completely different type of application [
21] in which the target was sensitivity rather than joint maximization of output power and voltage. It consists of two branches in which the lengths have been optimized to tune the antenna to the required resonant frequency and to meet the specifications on radiation efficiency, radiation pattern and input return loss. The overall substrate size of the final design is 73 × 55 mm
2. The commercial substrate chosen was a Roger 4350B (
εr = 3.55, tan
δ = 0.0031, thickness = 1.5 mm).
Figure 3a shows the simulated and measured input reflection coefficient of the PIFA antenna. In addition,
Figure 3b shows the simulated E- and H-plane at the operating frequency. As expected, the antenna has an omnidirectional radiation pattern in the horizontal plane: the low-directivity behavior is a desirable feature for RF energy harvesting scenarios, where the direction of the incoming power is typically unknown. The corresponding peak gain achieved is 1.4 dBi. All simulations were carried out using a commercial full-wave simulator (
CST Microwave Studio 2016).
The second step consists in designing the rectifying section, which involves choosing a rectifier topology and a nonlinear design for the rectifier-antenna matching network. As regards the former, single-stage full-wave voltage doubler topology represents the best option for ultra-low power applications, as is well documented in the literature [
22,
23]. For this reason, a full-wave Dickson rectifier based on low-threshold Skyworks SMS7630-079 Schottky diodes was selected.
Once the rectifier topology is selected, an optimum matching network between the rectifier and the antenna needs to be designed by nonlinear circuit techniques, in order to ensure, throughout the power range available, that maximum RF power enters the rectifier input. The topology chosen is the distributed matching network shown in
Figure 4a: it consists of two impedance steps and two stubs, the first being short-circuited to ground whereas the second is open. Impedance steps are employed to guarantee broadband matching between the RF detector (i.e., the rectifying circuit) and the antenna. For the operating frequency (868 MHz) chosen here and for the targeted RF input power, ranging from −20 to −10 dBm, a nonlinear regime is optimized accounting for the dispersive behavior of the linear sub-network (antenna and matching network), represented by a frequency-variable complex reflection coefficient computed by full-wave simulation. The nonlinear model of the diodes is completed with their package model, which is essential for accurate optimization of the entire rectenna at these operating frequencies. Optimization is based on the Harmonic Balance (HB) method and aims at maximizing the RF-to-dc conversion process, through optimization of rectenna efficiency, defined as [
24]:
where
VRECT and
IRECT are the dc components of the rectified voltage and current at the output port when a certain load is applied, while
PAV is the power available at the rectenna location, and represents the maximum power the antenna is able to deliver to the rectifying circuit. Commercial simulator ADS was used for the integrated nonlinear/EM design optimization.
Figure 4a shows the circuit layout, with details on the microstrip line dimensions and on the optimum load resistor. Such a rectenna system has been fabricated and the corresponding performance is reported in
Figure 4b, where the simulated and measured behavior of the RF-to-dc conversion efficiency, computed as in (1), and the output dc voltage are plotted as a function of the input power (
PAV): the rectenna exhibits a conversion efficiency better than 25% throughout the entire range of low RF power, starting from −20 dBm. In particular, at −18 dBm the efficiency is greater than 30%, corresponding to a dc power of about 6 μW, which represents a practical limit for current state-of-the-art DC/DC converters [
25]. At the same time, a dc output voltage greater than 200 mV has been experimentally verified for
PAV = −20 dBm. All these values were obtained with respect to an optimum dc load of 22 kΩ.
In order to estimate the maximum achievable distance of a sensor equipped with the proposed rectenna from an RF source, the system was tested in a 15 × 15 m2 laboratory environment. Experiments took place purposely outside an anechoic chamber in order to account for a more realistic scenario including limited multipath effects; nevertheless measured received power was tolerably close to the theoretical value derived from Friis equation.
The measurement procedure was carried out in two steps: (i) first, the receiver-to-transmitter distance was set; (ii) then, measurement of the output dc voltage on the rectenna load was carried out. The distances involved in the measurements ranged from 4 to 13 m. The transmitted power was selected following the current regulations for RFID applications [
26]: 0.5 W in the 863–870 MHz frequency range and 2 W for a narrow band starting from 869.4 MHz to 869.65 MHz. The output DC voltage on the optimum load R
OPT (22 kΩ) was measured by a digital multimeter. This setup lends itself to effective experimental verification of the actual behavior of the entire rectenna, i.e., the antenna acting as the power source of the rectifier. In order to create a reference comparison with the expected simulated results, the link adopted was first modeled by a Friis equation and the actual rectified power (
PRECT) was straight forwardly computed by the following equation:
where
PTX is the power transmitted at the remote location (the power exciting the transmitting antenna),
GTX and
GRX are the gains of the receiving and transmitting antennas, respectively,
D is the link distance, λ is the wavelength at the operating frequency. It is noteworthy that experimental and theoretical analyses may be carried out considering the maximum gain direction, for both the transmitting and receiving antennas. As the transmitting antenna, we adopted a commercial logperiodic antenna (
PCB VA5JVB), with
GTX = 6 dBi. As mentioned before, the receiving antenna gain is
GRX = 1.4 dBi.
Figure 5 reports the rectified dc power versus distance, for two different ERP levels. Considering a minimum required power of 6 μW for the dc-dc converter [
27], it can be concluded that the rectenna is able to operate at 6-m distance for the 0.5-W-ERP experiment, and up to 12-m distance for the 2-W-ERP. It is noteworthy that the models used during rectenna optimization for both the dispersive linear sub-circuit and the nonlinear devices allowed one to obtain predicted performances that were in very good agreement with the experimental one over a wide range of transmitted RF power, as can be observed in the plots of
Figure 5 where the measured and predicted rectenna output dc power are compared over a number of RF source-rectenna distances.
2.1.2. DC/DC Converter
The DC/DC converter used in the system features an ultra-low power buck-boost converter designed in STMicroelectronics 0.32 μm CMOS microelectronic technology [
14]. The overall architecture can be divided into two main blocks: a start-up circuit, which allows for IC bootstrap with RF input sources typically providing low voltages, and the main DC/DC converter which also provides a fractional open-circuit voltage (FOCV) MPPT algorithm in order to adapt to the best power transfer condition. The IC dynamically decides whether to route power to the load or to a small self-supply capacitor C
conv: this achieves very fast activation times even in the presence of large buffer capacitors at the load output port. When C
conv is sufficiently charged, all power is routed to the load. Should C
conv get excessively discharged, all power is routed here to replenish it before the IC fails. A block diagram of the circuit IC is reported in
Figure 6.
The start-up module consists of a 16-stage charge pump implemented with low-threshold MOSFETs and driven by an internal oscillator. A minimum voltage of approximately 250 mV from Vrect is required to keep it operating. During the start-up phase, when the input voltage (i.e., the rectenna output voltage) approaches 250 mV, the charge pump circuit starts working, and the output voltage on the self-supply capacitor Cconv is boosted. However, internal devices are not fully switched on until the output voltage gets to 600 mV, so that the output charging rate is initially limited by the sub-threshold state of the system. As soon as the generated voltage reaches 0.6 V the start-up circuit becomes fully operational and the charge pump improves its charging rate until the output exceeds 1.36 V, which is the minimum operating voltage of the main DC/DC converter. At this point the charge pump is disabled and power conversion occurs through the buck-boost DC/DC converter. Although the overall efficiency of the start-up stage settles between 5% and 15%, its sole purpose is to initially bootstrap the main DC/DC converter, so that its impact on operative efficiency can be considered negligible.
Once the 1.36 V threshold is reached, an in-rush current of about 11 μA is absorbed from the energy source by the module for a short time to complete bootstrapping the converter functionalities. After this, the module can be sustained with an input power of just 935 nW showing a quiescent current of 121 nA. The different functional modes are summarized with the corresponding supply voltages in
Table 1. It is worth recalling that these values refer to the voltage on the self-supply capacitor V
conv. Another aspect worth consideration is the high output resistance of the rectenna, which causes significant voltage drops on its output node as the current increases.
In order to extract the maximum power from the source, the IC adopts an FOCV MPPT technique. The input source is kept at 50% of the open-circuit voltage of the rectenna, which actually represents the maximum power transfer condition for the system. The open-circuit voltage is sampled for 2 μs every 8 conversion cycles of the DC/DC converter. The buck-boost DC/DC converter operates in discontinuous current conduction mode, and is switched when the source voltage crosses the reference MPPT voltage. The overall efficiency is highly affected by source impedance and open-circuit voltage.
Thereafter, a full analysis was performed with the aim of obtaining an exhaustive characterization of the DC/DC converter in the specific running conditions of the system proposed. An equivalent model of the rectenna described in
Section 2.1.1 was extracted from the static voltage-current characteristics and used for characterization. This consists in a DC voltage source (V
OC) with a 22 kΩ series resistance. The output voltage V
harv of the DC/DC is set at 2.3 V, which is the chosen maximum operating voltage of the sensing node as described in
Section 2.3. During operation, the variations on V
harv will be limited to a few hundred mV as the worst case. A 10 MΩ load was connected to V
harv. Results show that when the open-circuit voltage of the rectenna V
OC ranges from 0.32 V to 1.4 V, the related efficiency grows from 35% to 73%, with a plateau reached early on at 0.8 V. The whole characterization is reported in
Figure 7.
With respect to
Figure 4b, VRECT will be kept by the IC at approximately half of VOC, as the DC/DC converter works to maintain a state of maximum power transfer by providing an input impedance equal to the source impedance (22 kΩ in this case). Moreover, the extracted model was considered valid throughout the operative range of the system.
Figure 8 shows the dedicated board containing the DC/DC converter along with its subsidiary components.
2.2. The Active Node
The sensing and communication node, whose internal architecture is shown in
Figure 9, includes a temperature and relative humidity sensor, a low-power microcontroller and a sub-GHz radio device for data communication. STMicroelectronics HTS221 is an ultra-compact sensor based on a planar capacitance technology that integrates humidity and temperature sensing with a mixed signal ASIC to provide data measured through standard digital serial interfaces. The ultra-low power STMicroelectronics STM32L1 microcontroller, based on the ARM Cortex-M3 core, interfaces with the sensor for data acquisition and manages communication with the STMicroelectronics SPIRIT1 module, a low-power sub-GHz RF transceiver.
Wireless communication is based on DASH7 [
28], an open source Wireless Sensor and Actuator Network (WSAN) protocol; the microcontroller implements OpenTag, a DASH7 protocol stack and a minimal Real-Time Operating System (RTOS) designed to be light and compact and targeted to run on resource-constrained microcontrollers.
The DASH7 network architecture has a star structure where all the nodes, which are typically low-power devices able to transmit and receive data, communicate only with a gateway that is never offline and connects the DASH7 network to other networks and to the web.
DASH7 supports two communication models: pull and push [
29]. The pull model consists of a request-response mechanism initiated by the gateway; it uses an advertising protocol for rapid ad-hoc node synchronization before sending an addressed request to a node and waiting for the response [
29]. The data transfer to the gateway initiated by the nodes is based on the push model (e.g., beaconing); this approach is implemented as an automated message or beacon that is sent at specific time intervals.
In this work, the beaconing approach is used to send the temperature and humidity data from the sensor node to the gateway; this method is the least power hungry and the node can send the message as soon as the harvesting module provides enough power to power-up the node or wake up it from a deep sleep state.
The node can be supplied with a voltage ranging from 1.8 V to 3.6 V, and is programmed to perform two different stop policies: off-mode and standby-mode. The policy is selected by the harvesting module, as will be explained in the following section.
As can be seen in
Figure 10 and
Figure 11, the two modes behave in the same way at power on, when, after the start-up phase, the node acquires data from the sensor and transmits them to the gateway. Afterwards, if
off-mode is selected, the node generates a signal for the harvesting module to inform it that the power supply can be switched-off. When the power supply is once more provided, the node will perform a new start-up phase, data acquisition and message transmission. This phase is associated with a significant energy overhead.
Figure 10 shows a schematic of the current consumption of the node and its behavior in
off-mode indicating the average current in each of the three phases (start-up, data acquisition and transmission); in all each activation phase lasts 680 ms and the average current consumption over this time is 4.7 mA at 1.9 V.
On the contrary, if the
standby-mode is selected, after the first start-up phase and message transmission, the node informs the harvesting module that transmission is completed and that it is entering a deep sleep state in which its current consumption is 3 μA. The node then waits for an external interrupt, generated by the harvesting module, to wake up and perform a new data acquisition and message transmission. In
standby-mode, therefore, the power supply is never switched-off, and the overhead consists in constant power consumption. The schematic of the node’s current consumption and its behavior in
standby-mode is shown in
Figure 11. In this configuration, with the exception of the first power-on in which the current consumption is the same as each activation in
off-mode, the start-up phase does not have to be repeated for each activation phase because the power supply is never switched-off. As can be seen in
Figure 11, in
standby-mode each activation phase following the first one lasts 38 ms, and the average current consumption during this time is 3.81 mA at 1.9 V. In
standby-mode, the charge consumption for each data acquisition and message transmission is much less than in
off-mode, but a current of 3 μA has to be guaranteed to keep the node alive in the deep sleep state.
The selection between off-mode and standby-mode has a significant impact on the power budget. The off-mode is associated with a constant energy overhead, consisting in the energy consumed for starting the system. By contrast, the standby-mode is associated with a constant power overhead. Hence, which of the two modes costs less will depend on the frequency of activation. For frequent activation, the stand-by mode consumes less energy. Furthermore, the frequency of activations strictly depends on the harvested power.
2.3. Policies for Power Optimization
In this section, the proposed adaptive feature is described in detail, as well as the architectural choices and dimensioning of control circuits shown in
Figure 13. The interface between the harvesting module and the active node is implemented through four control signals connected to the microcontroller (
Policy,
Reset_VDD,
Start and
Reset_Start), besides the ground and positive supply (
VDD).
The Policy signal selects one of the two stop policies of the active node (off-mode and standby-mode).
The first factor to be analyzed is the buffer capacitance
Cbuff, which plays the role of energy storage needed by the system to offset the total power request of the node during its active phase. Such requests are summarized in
Table 2, which integrates the current absorbed by the node when switching into active mode from each of the other two modes.
In order to have a voltage drop of about 0.4 V, the resulting
Cbuff must be at least
where the voltage drop was chosen as a trade-off between system power consumption and wake-up time. In this instance, a lower bound of 1.9 V was chosen by considering a 100 mV margin to the minimum 1.8 V supply voltage required by the node to operate, while the upper bound was chosen by considering that a lower voltage implies lower power consumption, though at the same time it requires a larger buffer capacitance which causes a longer start-up time when the system has to be booted for the first time. Hence a maximum operating voltage of 2.3 V was chosen and, as a result, an 8 mF
Cbuff must be considered.
Three control circuits are necessary to generate the correct control signals for the micro-controller (
Figure 13).
The first one is the Control circuit for OFF mode. This block has the task of monitoring the voltage across Cbuff capacitance voltage and consequently to provide power supply to the sensing node only when voltage is in the acceptable range (1.9 V–2.3 V). In this way, the sensing module is only switched on when VDD exceeds 2.3 V, i.e., when the buffer capacitance has sufficient energy to sustain at least one complete data transmission. Likewise, power supply is taken off as soon as VDD drops below 1.9 V, as the sensing module cannot work at lower voltages. During off-mode, a reset signal (Reset_VDD) must be issued by the microcontroller at the end of each transmission stage, so that power supply is simultaneously turned off. This behavior ensures that the next transmission will only be held when the buffer capacitance is fully recharged, i.e., when it reaches 2.3 V again. A NCP303 low-power voltage supervisor was used to implement the block, along with two AS11P2 analog switches and two resistors in order to obtain the desired hysteresis, respectively 2.4 MΩ and 500 kΩ. The total quiescent current of the block is 500 nA, mostly due to the NCP303 supervisor.
The second one is the
Control circuit for STANDBY mode. This block has the task of monitoring the capacitance voltage and consequently providing the
start signal only when voltage is above 2.0 V. During
standby-mode, the sensing node is always powered, and subsequent transmissions are regulated by the
start signal, so that it must only be issued when the buffer capacitance is storing enough energy to sustain transmission. Actually, the expected voltage drop due to a single transmission in
standby-node is a mere 18 mV as explained in following equation
so a threshold voltage of 1.9 V +
∆V = 1.918 V could be enough to sustain standby-mode, but a safer margin of 2.0 V − 1.9 V = 100 mV was chosen for this condition. A reset signal (
Reset_Start) from the microcontroller is also requested at the end of each transmission in order to force the
start signal to a low level, even if the related capacitance voltage drop has not been sufficient to trigger the voltage supervisor. This happens because the microcontroller is sensitive to a positive
start signal edge, so that a low-to-high transaction is always required to awaken the sensing node. An NCP303 low-power voltage supervisor was used to implement the block, along with one AS11P2 analog switch and a pull-up resistor of 2.4 MΩ. The total quiescent current of the block is 400 nA, mostly due to the NCP303 supervisor.
The ability to dynamically select whether to operate in
off-mode or
standby-mode is a crucial aspect of the solution presented, as it enables the system to fully exploit the available environmental energy under any circumstance without human intervention. In both cases the minimum transmission period is obtained, as the microcontroller is either supplied (
off-mode) or awoken (
standby-mode) as soon as the buffer capacitance has recovered the energy lost, but depending on the variable amount of extracted energy, one solution can be less advantageous than the other, if not altogether unfeasible. Transmission Period (
TP) is defined as the time interval between two consecutive transmissions and can be calculated as:
where
Qneeded is the charge lost during each transmission,
Iextracted is the current provided by the DC/DC converter,
Iqharv is the quiescent current of the harvesting module that is directly supplied by V
HARV while
Iqnode is the quiescent current of the rest of the system supplied by
VDD. These values differ between the two operative modes, and are summarized in
Table 3.
The most significant difference is that in off-mode the charge needed is significantly higher than in standby-mode, but the total quiescent current is only 500 nA, since all the other modules are switched off during recharge periods. As a consequence, in off-mode nearly all the current from the power converter can be used to recharge the buffer capacitance.
Thus, this last mode proves more suitable when the extracted current is relatively low, whereas the
standby-mode becomes more cost effective at higher extracted currents, when its lower value of activation charge becomes predominant. A detailed graph of transmission data rates versus extracted currents is shown in
Figure 14, analytically obtained through Equation (5).
The available current is defined as the effective current that can be used by the active part of the system or, in other words, the whole extracted current subtracted by Iqharv, which is always drawn from the DC/DC converter (Iavailable = Iextracted − Iqharv). As shown in the graphs, as the available current rises above 4.190 μA, standby-mode becomes the best choice in terms of minimum data rates, and the related threshold value is about 13 min.
With this assumption, the
Control circuit for policy detection has the task of correctly identifying whether the current available is either above or below the threshold value of 4.190 μA, and communicating this to the microcontroller through the
policy signal. Since the correct relationship between the power received by the rectenna and the power extracted by the DC/DC has been fully investigated (see details in Results section), the least power-consuming solution is to simply monitor the average voltage at the rectenna output. This value is solely related to the extracted current through the efficiencies of the interposed stages, and experimental results show that a value ≥585 mV for V
RECT is required to obtain an available current of 4.190 μA. Since the low-power voltage supervisor NCP303 has a threshold value of 2 V, a dedicated low-power voltage amplifier with a
gain was added, composed of an LPV521 op-amp and two resistors of 20 MΩ and 4 MΩ. Moreover, a simple RC filter was inserted with τ = 100 ms, in order to reject the periodic fluctuations caused by the FOCV algorithm of the DC/DC converter, which actually disconnect the rectenna for about 4 μs every 8 extraction cycles. The overall quiescent current of the block is 600 nA, as already reported in
Table 3.