A Multistage DC-DC Step-Up Self-Balanced and Magnetic Component-Free Converter for Photovoltaic Applications: Hardware Implementation

Abstract

This article presents a self-balanced multistage DC-DC step-up converter for photovoltaic applications. The proposed converter topology is designed for unidirectional power transfer and provides a doable solution for photovoltaic applications where voltage is required to be stepped up without magnetic components (transformer-less and inductor-less). The output voltage obtained from renewable sources will be low and must be stepped up by using a DC-DC converter for photovoltaic applications. 2 K diodes and 2 K capacitors along with two semiconductor control switch are used in the K-stage proposed converter to obtain an output voltage which is (K + 1) times the input voltage. The conspicuous features of proposed topology are: (i) magnetic component free (transformer-less and inductor-less); (ii) continuous input current; (iii) low voltage rating semiconductor devices and capacitors; (iv) modularity; (v) easy to add a higher number of levels to increase voltage gain; (vi) only two control switches with alternating operation and simple control. The proposed converter is compared with recently described existing transformer-less and inductor-less power converters in term of voltage gain, number of devices and cost. The application of the proposed circuit is discussed in detail. The proposed converter has been designed with a rated power of 60 W, input voltage is 24 V, output voltage is 100 V and switching frequency is 100 kHz. The performance of the converter is verified through experimental and simulation results.

1. Introduction

Renewable energy resources are becoming popular and trendy with the increase in demand and cost of energy. The proper utilization of energy resources is one of the most important issues of the present century. There are various renewable energy resources, including solar, tidal, wind, bio, nuclear and geothermal, with zero pollution emissions. Solar energy is a free, inexhaustible source of energy and is increasingly competitive with other energy sources. This energy is utilized with the help of arrays, consisting of a number of solar panels, connected in series [1,2,3]. In the past, various PV system methods or structures were adopted to minimize the cost to efficiency ratio. In [4,5,6,7,8], a Photovoltaic Central Inverter Structure (PV-CIS) is employed to feed photovoltaic energy to the electric grid. In PV-CIS PV lines are arranged in parallel and connected to one central inverter as shown in Figure 1. The drawback of CIS are: (i) a large number of panels are required which increases the cost of system; (ii) more number of DC cables with high-voltage rating are needed; (iii) losses in the line; (iv) loss of power due to module mismatch; (v) common Maximum Power Point Tracking (MPPT) is used; (vi) system reliability depends on the single inverter.

In [4,5,6,7,8], a Photovoltaic String Inverter structure (PV-SIS) is employed to feed photovoltaic energy to the electric grid. In PV-SIS, several PV lines are used, which are made up of several series- connected PV panels as shown in Figure 2. All the PV lines are connected to separate inverters via a DC-DC converter and the inverter outputs are connected in parallel and feed into the electric grid. The drawbacks of the PV-SIS system are: (i) it requires a large number of panels to design a several PV line; (ii) a large number of converters are required to feed the grid; (iii) the cost is high due to the separate MPPT and complex control circuitry is required to synchronize all the inverters.

In [4,5,6,7,8], Photovoltaic AC Module Structure (PV-ACMS) is discussed to fed photovoltaic energy to the electric grid and it provides a viable solution to overcome the drawbacks of PV-CIS and PV-SIS. In PV-ACMS a single photovoltaic panel is connected to the electric grid via an inverter as shown in Figure 3a. The drawbacks of PV-ACMS are: (i) it requires several module inverters which increase the cost of the system; (ii) separate MPPT is needed for each panel; (iii) the overall efficiency is low. In [4,5,6,7,8], Photovoltaic Multi-String Inverter Structure (PV-MSIS) is discussed to overcome the drawback of PV-CIS, PV-SIS and PV-SIS structures. In PV-MSIS several PV panels are connected to a single inverter connected via several DC-DC converters as shown in Figure 3b. This structure combines the features of PV-SIS and PV-ACMS. The drawback of the PV-MSIS concept is: (i) it required several DC-DC converters to transfer energy to the inverter; (ii) high cost due to the greater number of converters and separate MPPT.

The output obtained from a photovoltaic cell/array is usually low, so before feeding this voltage to the inverter for practical application purposes, it must be stepped up using a conventional DC-DC boost converter [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]. With the increase in the duty-cycle of switch and leakage resistance of inductors, the performance of the converter degrades. Due to these practical problems, conventional DC-DC converters are unable to provide doable solutions for step-up voltage applications [15]. In theory, when a duty cycle approaches 100%, an infinite voltage conversion ratio is achieved with a conventional boost converter, but in practice, the inductor leakage resistance of the inductor limits the voltage conversion of the converter [16], so the traditional converters cannot be used where the required conversion ratio is four or more [16]. Furthermore, to achieve a high conversion ratio by using large duty cycle compromises the utilization of high frequency for Pulse Width Modulation (PWM) because of semiconductor control devices’ inherent switching delay. Unluckily, a large reactive network follows the limited switching frequency which is employed to protect from the ripple condition of voltage and current [17]. The traditional buck-boost converter is not reliable due to its discontinuous input current, which results in low utilization of the input source [13,15]. By increasing the switching frequency of the converter, the problem of leakage resistance for certain values of ripple can be overcome. The finite switching time in a normal power device limits the switching frequency if the duty ratio is either too high or too small, so in order to abolish the above problems and simultaneously acquire essential high voltage, isolated converters can be engaged. Many isolated and non-isolated converter topologies have proposed over time, which make use of inductors, coupled inductors and transformers [16,17,18,19,20,21,22,23,24,25,26,27]. The high voltage stress occurring due to the transformer leakage inductance leads to switching losses and electromagnetic interference (EMI) problems, resulting in the reduced efficiency of conventional converters. Hard switching converters are inconvenient to use for high voltage applications due to their circuit complexity, higher voltage stress across the switch and the increased cost of the converter. Hence, for isolated topologies the size, weight and losses of power transformers are limiting factors. Recently, various combinations of coupled inductors, voltage multipliers or switched capacitor multipliers [23,24,25,26,27,28,29,30,31,32,33,34,35] along with a switched inductor (SI), switched capacitor (SC), voltage lift switched inductor (VLSI) and modified VLSI principles were used to accomplish the necessity [15,26]. Figure 4a–c shows the recent SI, VLSI and modified VLSI inductive networks. For acquiring a high boost ratio, a cascaded approach is introduced. To design a Cascaded Boost Converter (CBC), a number of inductors are essential, which is the most complex part. In addition, losses and increased current ripple prove to be a barrier to achieve a high conversion ratio and better efficiency [36,37,38]. With an objective of acquiring a high voltage gain just by using a single switch, the Quadratic Boost Converter (QBC) was proposed, though, in a QBC, higher voltage rating switches are required with higher R_DS-ON, as voltage stress raised across the switch is equal to the output voltage [39,40,41]. Multilevel converters provide a suitable solution for power conversion because of the low voltage stress across each device [42]. High voltage is achieved by multilevel DC-DC converters using capacitors and diode circuitry at the output end and the output voltage level can be increased without actually disturbing the actual circuit. By varying the number of output levels and duty cycle, the voltage gain of multilevel converters can be varied [43,44]. For conventional multilevel converters, designing magnetic components like inductors is a complex task, which also induces electromagnetic emission noise. Other than these issues the presence of inductors and transformers in the power circuit degrades the integration capability and increases the cost, weight and size of the converters. Switched Capacitor (SC) power circuits provide good integration ability due to their small volume and weight, since magnetic components like transformers and inductors is not needed to design a SC converter [33].

In this article, a new magnetic component-free (transformer-less and inductor-less) DC-DC converter is proposed to overcome the drawbacks of PV-CIS, PV-SIS, PV-ACMS, PV-MSIS and the above discussed converter topology. The proposed converter provides a viable solution for existing photovoltaic application systems where voltage must be stepped up without magnetic components before transferring energy to a multilevel-inverter. The single proposed converter is sufficient to transfer energy to a multilevel inverter as shown in Figure 5.

The proposed photovoltaic system (PV System) consists of PV modules, the proposed DC-DC converter, battery and the multilevel inverter (MLI) which converts the battery/proposed DC-DC converter voltage to AC voltage to power AC loads/feed in the electric grid. Some amount of power is lost during the conversion of photovoltaic energy to electric energy. The PV device maximum output power (product of voltage and current) is described by the Maximum Power Point (MPP) and it is also depends on the environmental conditions (generally on temperature and light conditions). A Maximum Power Point Tracker is compulsory to ensure the maximum power output (P_max) of a solar PV device. The Maximum Power Point Tracker can be used to adjust its input voltage to utilize the maximum photovoltaic output power and then transform this power to supply the varying voltage requirements. When the PV voltage is increased the current will ultimately decrease, and when the PV current is increased the voltage will ultimately decrease. Depending on parameters like irradiance and temperature the MPP of the I-V curve of a PV module changes dynamically. Therefore, the MPP needs to be located by a tracking algorithm as it is not known beforehand.

To achieve the maximum power transfer from the PV module to the load it is necessary to match the load resistance R_L to the best possible output resistance of the PV module R_PV (R_mpp = V_mpp/I_mpp). Characteristic power-voltage and current-voltage graphs or curves are shown in Figure 6a.

The output power of PV module will be zero when the photovoltaic current (I_PV) is equal to the short circuit current (I_SC) or the photovoltaic voltage (V_PV) is equal to the open circuit voltage (V_OC). Thus, it is possible to track the maximum power point (MPP) of a photovoltaic cell by regulating the operating voltage of V_PV. In [45] Maximum Power Point Tracking is discussed for a reconfigurable switched-capacitor converter and in [46] a perturbation and observation (P&O) algorithm is discussed for DC-DC converters connected to photovoltaic generators. The concept to control power of a multistage magnetic component-free DC-DC converter is explained in Figure 6b–f. Thus, to regulate the operating voltage V_PV, the ON time of the capacitor and number of stages (if the structure is reconfigurable) are two controlled parameters in the proposed system, therefore it forces the MPPT charge controller to extract the maximum power PV module to operate at a voltage close to the maximum power point which causes it to draw the maximum available power from the PV module.

The proposed converter is also suitable for the DC link application in DC-AC systems where capacitor voltage balancing is the main challenge. The proposed converter also provides a viable solution for low power applications, since inductors and transformers are not required to design the proposed converter.

2. Recent Transformer-Less and Inductor-Less DC-DC Converters

In this section recent transformer-less and inductor-less DC-DC converter power circuit topologies and their drawbacks are discussed in detail. Various multilevel DC-DC converters and switched capacitor topologies without inductor were recently addressed in the literature.

2.1. Series-Parallel Switched Capacitor (SC) Converter

In [47,48,49], a series-parallel switched capacitor (SPSC or series-parallel SC) converter using only control switching elements and capacitors was proposed. In Figure 7a three-level series-parallel SC converter is depicted. The operation of this topology is simple and divided into only two modes (two switching states only). All the switches are controlled in such a way that all the capacitors are charged in series and discharged in parallel. The conversion ratio of an N-level series-parallel SC converter is 1/N (in step-down mode) and N times (in step-up mode). More than 90% efficiency is reported in the literature.

However the series-parallel SC converter has following drawbacks:

• Difficult to change the switching state of the converter due to the several switching elements.
• Unequal voltage across switches, thus power switches of various ratings are required.
• Series-parallel SC is bidirectional, but it is not possible to control the power flow. It depends on the voltages at the input and output DC buses.
• If switching is not properly controlled, it may instigate a charge unbalance situation among the converter capacitors.
• Non-modularity, since a large number of switches, gate drivers and diodes are required and the number of devices increases with the number of levels. Due to this a series parallel converter is large in size and has high cost.

2.2. Flying Capacitor Multilevel DC-DC Converter (FCMDC)

In [49,50,51], flying capacitor multilevel DC-DC converter (FCMDC) is proposed. Figure 7b depicts the power circuit of a three–level FCMDC. The conversion ratio of an N-level FCNDC is 1/N (in step-down mode) and N times (in step-up mode). FCMDC is a bidirectional converter with efficiency higher than 95%. The voltage stress of switches is also equal and thus requires same rating of the switching devices. Nevertheless FCMDC has the following drawbacks:

• A large number of transistors and capacitors is required (2N the number of switches and N number of capacitors are required to design an N-level FCMDC), hence this converter is large in size and also has a high cost.
• Difficult to extend the power circuit to increase the number of stages to change the output conversion ratio since the converter does not have a modular structure.
• A complicated switching scheme is required to operate the converter.
• FCMDC is inefficient at high switching frequency when the ON time is comparable to the rise and fall time of the switches since; to transfer energy from the input source to the capacitors a very small time frame is allowed.
• Utilization of components is less. It is not possible to control the power circuit if any of the switches fails.

2.3. Magnetic-Less Multilevel DC-DC Converter (MMDC)

In [52], a magnetic-less multilevel DC-DC converter (MMDC) is proposed by connecting two transistor and one capacitor switching cells (modular block) in a mesh pattern. Figure 8 depicts the power circuitry of the three-level MMDC. The conversion ratio of an N-Level MMDCC is 1/N (in step-down mode) and N times (in step-up mode). The voltage stress of each transistor of the switching cells is the same and equal to V_in and also it is independent of the duty cycle and conversion ratio of the converter. However, the following are the drawbacks of the MMDC:

• A very large number of switching devices and capacitors are required to design an MMDC N (N + 1) switches, N (N + 1) diodes and 0.5N (N + 1) capacitors are required to design the N-Level MMDCC.
• It is difficult to manage direction of power flow of the converter due to the greater number of transistors present in the conducting path.
• The power flow of the converter is also depends on the voltages at the input and output DC buses, thus it is not a good option for the applications where the source voltage may vary.

2.4. Fibonacci DC-DC Converter

In [53], a Fibonacci DC-DC converter is proposed using capacitors and switching device circuitry. The voltage conversion ratio of the converter follows the well-known Fibonacci series. Figure 9 depicts the power circuitry of the three stage-Fibonacci converter. High voltage is achieved but it still requires a large number of switching devices and capacitors. The following are the drawbacks of the Fibonacci DC-DC converter:

• A large number of control switches are required to design the converter (3N + 1 number of control switches are required to design an N-stage converter)
• The Fibonacci DC-DC converter follows the Fibonacci series and thus it is not possible to achieve voltage conversion ratios like 2, 4… (which are not present in the Fibonacci converter)
• It is not capable of transferring power in both directions.

2.5. Modified Step-Up DC-DC Converter (Switch Mode DC-DC Converter)

In [54], a modified step-up DC-DC converter (switch mode DC-DC converter) is proposed which has continuous input current capability. Figure 10 depicts the switch mode DC-DC converter. Its power circuitry is divided into two parallel parts. A detailed study about the mode of operation and capacitor state is given in

Table 1. Mode of operation and state of capacitors of Modified Step-up DC-DC Converter.

Operation Mode	Switches State								Capacitors of Left Part (Section-I)	Capacitors of Right Part (Section-II)
	S1	S2	S3	S4	S5	S6	S7	S8
Mode-I	OFF	ON	OFF	ON	ON	OFF	ON	OFF	Charging	Discharging
Mode-II	OFF	OFF	OFF	OFF	ON	OFF	ON	OFF	No action	Discharging
Mode-III	ON	OFF	ON	OFF	OFF	ON	OFF	ON	Discharging	Charging
Mode-III	ON	OFF	ON	OFF	OFF	OFF	OFF	OFF	Discharging	No Action

. The operation of the proposed converter is simple and the conversion ratio of the converter is adjusted by varying the duty cycle. In addition, the continuous input current from low voltage input sources reduces the EMI problem.

However this converter has the following drawbacks:

• A large number of switching devices is required.
• It introduces high switching losses and thus the efficiency of the converter is less.
• Moreover, there is no extension of the circuit to increase the voltage conversion ratio.
• This converter is not suitable for high power high voltage applications due to the lower voltage conversion ratio.

2.6. Switched Capacitor DC-DC Converter

In [55], a new switched capacitor DC-DC converter with low ripple input current is proposed. Figure 11 depicts the power circuit of the converter. The low ripple and continuous input current help to reduce EMI of the circuit. However this circuit has no provision to increase the voltage conversion ratio.

2.7. Multilevel Modular Capacitor Clamped DC-DC Converter (MMCCC)

In [56], a multilevel modular capacitor clamped DC-DC converter (MMCCC) is proposed. Figure 12 depicts the power circuit of the MMCCC for five levels. The following are the drawbacks of the MMCCC:

• Using this topology a high voltage conversion ratio is achieved, but it requires a large number of switching devices and capacitors.
• The voltage stress across switches of the converter is high. For an N level MMCCC the voltage stress of N-2 switching devices is equal to 2V_in and the remaining switches have V_in voltage stress.

3. Proposed Self-Balanced and Magnetic Component-Free Multistage DC-DC Converter

3.1. Mode of Operation

The power circuit of the proposed self balanced and magnetic component-free (transformer-less and inductor-less) multistage DC-DC converter for K stages is depicted in Figure 13. The conspicuous features of the proposed topology are: (i) it is magnetic components free; (ii) continuous input current; (iii) low voltage rating semiconductor devices and capacitors; (iv) modularity; (v) easy to add a higher number of levels to increase the voltage; (vi) only two control switches are used with alternating operation; and (vii) simple control. The proposed DC-DC converter topology is free from magnetic components like inductors and it is designed for unidirectional power transfer applications. The proposed topology provides an output voltage higher than the input voltage without any magnetic components. The operation at high frequency permits a reduction in the size of capacitors thus enabling a reduced size of the circuit without external components. In this topology the number of control switches does not depend on the number of levels. The required number of diodes and capacitors depends on the number of output levels. Two diodes and two capacitors are required to increase the level of the proposed converter by one. Thus, to design a 4-stage proposed step-up DC-DC converter topology, two control switches, eight uncontrolled (power diodes) and eight capacitors are required.

To explain the operation modes of the proposed magnetic component-free K-stages converter circuit the following is considered. The mode of operation of the converter is divided into two modes: Mode 1 when switch S_b and S_a act as a short circuit (turned ON) and open circuit (turned OFF) respectively, and Mode 2 when switch S_a and S_b act as a short circuit (turned ON) and open circuit (turned OFF), respectively. Hence, switch S_a and switch S_b are complementary in operation. The proposed topology has simple control and is operated at a fixed duty cycle of 0.5 to provide voltage to photovoltaic devices. A complex gate driver is also not required to drive the switch; instead an oscillator is sufficient to provide a gated signal.

In Mode 1 (Figure 14), switch S_b is turned ON and switch S_a is turned OFF, capacitor C₁₂ is charged by input voltage through diode D₁₁ and switch S_b when the voltage across capacitor C₁₂ is smaller than the input voltage. When the voltage across capacitors C₁₂ + C₂₂ is smaller than the voltage V_C11 + V_in, then the energy stored in the capacitor C₁₁ is transferred to capacitor C₂₂ through D₂₁ and switch S_b. Similarly capacitor C_(k-1)1 transfers its energy to C_K2 when the voltage across capacitors C₁₂ + C₂₂ +… + C_K2 is smaller than voltage V_in + V_C11 + C_C21 +… + V_C(K-1)1 through diode D_K1. In this mode the output voltage is equal to the input voltage (V_in) + V_C11+V_C21 +…+ V_CK1.

In Mode 2 (Figure 15), control switch S_a is turned ON and switch S_b is turned OFF, when the voltage across capacitor C₁₁ is smaller than capacitor C₁₂, then capacitor C₁₁ is charged by capacitor C₁₂ through diode D₁₂ and switch S_a. When the voltage across capacitor C₁₁ + C₂₁ is smaller than the voltage across capacitor C₁₂ + C₂₂, then capacitor C₂₂ transfers its energy to capacitor C₂₁ through diode D₂₂ and switch S_a. Similarly capacitor C_K2 transfers its energy to capacitor C_K1 through D_K2 when the voltage across capacitor C₁₁ + C₂₁+…+ C_k1 is smaller than the voltage C₁₂ + C₂₂ + C_K2. In this mode the output voltage is equal to the input voltage (V_in) + V_C12 + V_C22 + …+ V_CK2.

3.2. Voltage Gain Analysis of a Multistage Converter without Diode and Switches Loss

When the voltage drop across diodes and switches are not considered, all capacitors are subjected to the same voltage V_in. The voltage conversion ratio or voltage gain is equal to the (K + 1) i.e., number of stages +1 and also depends on number of capacitors. Figure 16a,b depict the graphs of the required number of devices/components versus the number of stages in 2-dimensional and in 3-dimensional view, respectively. From Figure 16a,b it is observed that the number of devices/components linearly increases as the number of stages is increased. Thus, with each stage increase two more diodes and capacitors are needed. It is also observed that the number of diodes is equal to the number of capacitors.

$${\mathrm{V}}_{\mathrm{C}11}={\mathrm{V}}_{\mathrm{C}12}={\mathrm{V}}_{\mathrm{C}21}={\mathrm{V}}_{\mathrm{C}22}={\mathrm{V}}_{\mathrm{C}\mathrm{K}2}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}$$

(1)

$${\mathrm{V}}_{\mathrm{o}}=(\mathrm{K}+1)\times {\mathrm{V}}_{\mathrm{i}\mathrm{n}}$$

(2)

$${\mathrm{V}}_{\mathrm{o}}=\frac{{\mathrm{K}}_{\mathrm{C}}+2}{2}\times {\mathrm{V}}_{\mathrm{i}\mathrm{n}}$$

(3)

$${\mathrm{V}}_{\mathrm{o}}=\frac{{\mathrm{K}}_{\mathrm{D}}+2}{2}\times {\mathrm{V}}_{\mathrm{i}\mathrm{n}}$$

(4)

$${\mathrm{K}}_{\mathrm{C}}={\mathrm{K}}_{\mathrm{D}}=0.5\mathrm{K}$$

(5)

where, K_C and K_D number of capacitor and diode used to design the proposed circuit. The graph of voltage gain versus number of stages is shown in Figure 17a. It is observed that the proposed converter with K stages provides a K + 1 voltage conversion ratio. The graph of the number of stage devices/components versus voltage gain is shown in Figure 17b. It is observed that the number of devices/components linearly increases as the voltage gain requirement is increased. Thus, two diodes and two capacitors need to be connected to increase voltage gain by a factor of 1. It is also observed that 2 K diodes and 2 K capacitors are required to attain a voltage gain K + 1.

The graph of voltage gain (V_o/V_in), number of stages (K) and duty cycle (D) is shown in Figure 17c. It is observed that two capacitors and two diodes are required to design one stage of the proposed converter. The graph of output voltage for stages 1 to 9 by considering an input voltage of 25 V is shown in Figure 17d. It is observed that the output voltage is increased as the number of stages increases, and each stage contributes a voltage equal to the input voltage (25 V) to an output voltage of the proposed converter.

3.3. Voltage Gain Analysis of the Multistage Converter with Diode and Switches Loss

The voltage drop across power diodes and switches is ignored in medium and high power applications, but in low power applications it is considered. The analysis of the circuit is done with consideration of the voltage drop across diodes and switches. For simplicity, the voltage drop across diodes and switches is assumed to be equal to V_d.

$${\mathrm{V}}_{\mathrm{C}11}={\mathrm{V}}_{\mathrm{C}12}-{\mathrm{V}}_{\mathrm{D}12}-{\mathrm{V}}_{\mathrm{S}\mathrm{a}}$$

(6)

$${\mathrm{V}}_{\mathrm{C}11}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4{\mathrm{V}}_{\mathrm{d}}$$

(7)

$${\mathrm{V}}_{\mathrm{C}12}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-2{\mathrm{V}}_{\mathrm{d}}$$

(8)

$${\mathrm{V}}_{\mathrm{C}21}={\mathrm{V}}_{\mathrm{C}}{}_{12}+{\mathrm{V}}_{\mathrm{C}}{}_{22}-{\mathrm{V}}_{\mathrm{C}}{}_{11}-{\mathrm{V}}_{\mathrm{D}}{}_{22}-{\mathrm{V}}_{\mathrm{S}\mathrm{a}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4{\mathrm{V}}_{\mathrm{d}}$$

(9)

$${\mathrm{V}}_{\mathrm{C}22}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}+{\mathrm{V}}_{\mathrm{C}}{}_{11}-{\mathrm{V}}_{\mathrm{C}}{}_{12}-{\mathrm{V}}_{\mathrm{D}}{}_{21}-{\mathrm{V}}_{\mathrm{S}\mathrm{b}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4{\mathrm{V}}_{\mathrm{d}}$$

(10)

$${\mathrm{V}}_{\mathrm{C}\mathrm{K}1}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4{\mathrm{V}}_{\mathrm{d}}$$

(11)

$${\mathrm{V}}_{\mathrm{C}\mathrm{K}2}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4{\mathrm{V}}_{\mathrm{d}}$$

(12)

It is investigated that the voltage across each capacitor is equal to V_in − 4V_d except for the voltage across capacitor C₁₂. The voltage across capacitor C₁₂ is equal to V_in − 2V_d. Thus, the proposed topology is self-balanced and magnetic component-free. The output voltage of the converter is limited by the devices’ forward voltage and number of devices.

The graph of the proposed converter output voltage versus number of stages with a practical diode (V_d = 1) and ideal diode is shown in Figure 18a. The graph of the proposed converter output voltage versus number of diodes or capacitors with a practical diode (V_d = 1) and an ideal diode is shown in Figure 18b. From Figure 18a,b it is observed that the difference between the ideal and practical output voltage increases as the number of stages, diodes and capacitor requirement is increased. The difference between the ideal and practical output voltage depends on the number of stages of the proposed converter and it is equal to 4KV_d as given in Equation (15).

$${\mathrm{V}}_{\mathrm{C}11}={\mathrm{V}}_{\mathrm{C}21}={\mathrm{V}}_{\mathrm{C}22}={\mathrm{V}}_{\mathrm{C}\mathrm{K}1}={\mathrm{V}}_{\mathrm{C}\mathrm{K}1}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4{\mathrm{V}}_{\mathrm{d}}$$

(13)

$${\mathrm{V}}_{\mathrm{C}12}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}-2{\mathrm{V}}_{\mathrm{d}}$$

(14)

$${\mathrm{V}}_0=(\mathrm{K}+1){\mathrm{V}}_{\mathrm{i}\mathrm{n}}-4\mathrm{K}{\mathrm{V}}_{\mathrm{d}}$$

(15)

4. Design Calculation of the Capacitors of the Proposed Converter

To explain the designed calculation of the proposed converter a 1-stage proposed converter is considered. The power circuit of the 1-stage proposed converter is shown in Figure 19a. The ON state and OFF state equivalent circuit of the 1-stage proposed converter is depicted in Figure 19b,c respectively, where R_D is the forward resistance of the diode, R_S is the forward resistance of the switch, I_Sb is the current through the switch S_b and I_Sa is the current through switch S_a.

Initially the voltage across capacitor C₁₂ and C₁₁ is zero. Capacitor C₁₂ is charged through a resistance R_D and R_S from a supply voltage V_in when switch S_b is closed. The voltage across C₁₂ does not increase to V_in instantaneously, but builds up exponentially and not linearly.

$$\begin{array}{l}{\mathrm{V}}_{\mathrm{i}\mathrm{n}}=\frac{{\mathrm{C}}_{12}\mathrm{d}({\mathrm{v}}_{\mathrm{C}12})}{\mathrm{d}\mathrm{t}}\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)+{\mathrm{v}}_{{\mathrm{C}}_{12}}\\ \frac{\mathrm{d}({\mathrm{v}}_{\mathrm{C}12})}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{v}}_{{\mathrm{C}}_{12}}}=\frac{\mathrm{d}\mathrm{t}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{12}}\end{array}\}$$

(16)

$$\begin{array}{l}{\displaystyle \int \frac{\mathrm{d}({\mathrm{v}}_{\mathrm{C}12})}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{v}}_{{\mathrm{C}}_{12}}}}={\displaystyle \int \frac{\mathrm{d}\mathrm{t}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{12}}}\\ \log ({\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{{\mathrm{C}}_{12}})=-\frac{\mathrm{t}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{12}}+\mathrm{K},\mathrm{K}=\log {\mathrm{V}}_{\mathrm{i}\mathrm{n}}\\ {\mathrm{V}}_{{\mathrm{C}}_{12}}={\mathrm{V}}_{\mathrm{i}\mathrm{n}}(1-{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}}),\mathrm{T}=\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{12}\end{array}\}$$

(17)

$${\mathrm{i}}_{{\mathrm{C}}_{12}}=\frac{\mathrm{d}({\mathrm{C}}_{12}{\mathrm{v}}_{\mathrm{C}12})}{\mathrm{d}\mathrm{t}}=\frac{{\mathrm{C}}_{12}\mathrm{d}({\mathrm{v}}_{\mathrm{C}12})}{\mathrm{d}\mathrm{t}}$$

(18)

$${\mathrm{V}}_{\mathrm{i}\mathrm{n}}={\mathrm{i}}_{{\mathrm{C}}_{12}}\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)+{\mathrm{v}}_{{\mathrm{C}}_{12}}$$

(19)

Similarly:

$${\mathrm{i}}_{\mathrm{S}\mathrm{b}}=\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)}{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}}$$

(20)

Capacitor C₁₁ is charged through a resistance R_D and R_S from a capacitor C₁₂ voltage when switch S_a is closed. Thus, when switch S_a is closed capacitors C₁₁ and C₁₂ is charging and discharging, respectively.

$$\begin{array}{l}{\mathrm{V}}_{{\mathrm{C}}_{12}}={\mathrm{i}}_{{\mathrm{C}}_{11}}\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)+{\mathrm{v}}_{\mathrm{C}1}\\ {\mathrm{V}}_{{\mathrm{C}}_{12}}={\mathrm{i}}_{{\mathrm{C}}_{12}}\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)+{\mathrm{v}}_{{\mathrm{C}}_{11}}\end{array}\}$$

(21)

$$\begin{array}{l}{\mathrm{V}}_{{\mathrm{C}}_{12}}=\frac{{\mathrm{C}}_{11}\mathrm{d}({\mathrm{v}}_{\mathrm{C}11})}{\mathrm{d}\mathrm{t}}\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)+{\mathrm{v}}_{{\mathrm{C}}_{11}}\\ \frac{\mathrm{d}({\mathrm{v}}_{\mathrm{C}11})}{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{v}}_{{\mathrm{C}}_{11}}}=\frac{\mathrm{d}\mathrm{t}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{11}}\end{array}\}$$

(22)

$$\begin{array}{l}{\displaystyle \int \frac{\mathrm{d}({\mathrm{v}}_{\mathrm{C}11})}{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{v}}_{{\mathrm{C}}_{11}}}}={\displaystyle \int \frac{\mathrm{d}\mathrm{t}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{11}}}\\ \log ({\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{{\mathrm{C}}_{11}})=-\frac{\mathrm{t}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{11}}+\mathrm{K},\mathrm{K}=\log {\mathrm{V}}_{{\mathrm{C}}_{12}}\\ {\mathrm{V}}_{{\mathrm{C}}_{11}}={\mathrm{V}}_{{\mathrm{C}}_{12}}(1-{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}}),\mathrm{T}=\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right){\mathrm{C}}_{11}\end{array}\}$$

(23)

Similarly:

$${\mathrm{i}}_{\mathrm{S}\mathrm{a}}=\frac{{\mathrm{V}}_{\mathrm{C}}{}_{12}}{\left({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}\right)}{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}}$$

(24)

In steady state and at high switching frequency, the voltage across capacitor C₁₁ and C₁₂ at any instant during charging is cycled as given in Equations (25) and (26) where, ${\mathrm{V}}_{\mathrm{C}{\prime }_{11}}$ and ${\mathrm{V}}_{\mathrm{C}{\prime }_{12}}$ is the initial voltage of capacitor C₁₁ and C₁₂. If the initial storage voltage of C₁₁ and C₁₂ is positive:

$$\begin{array}{l}{\mathrm{V}}_{{\mathrm{C}}_{12}}=({\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{\mathrm{C}{\prime }_{12}})(1-{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}})+{\mathrm{V}}_{\mathrm{C}{\prime }_{12}}\\ {\mathrm{V}}_{{\mathrm{C}}_{11}}=({\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{\mathrm{C}{\prime }_{11}})(1-{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}})+{\mathrm{V}}_{\mathrm{C}{\prime }_{11}}\end{array}\}$$

(25)

If the initial storage voltage of C₁₁ and C₁₂ is negative:

$$\begin{array}{l}{\mathrm{V}}_{{\mathrm{C}}_{12}}=({\mathrm{V}}_{\mathrm{i}\mathrm{n}}+{\mathrm{V}}_{\mathrm{C}{\prime }_{12}})(1-{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}})-{\mathrm{V}}_{\mathrm{C}{\prime }_{12}}\\ {\mathrm{V}}_{{\mathrm{C}}_{11}}=({\mathrm{V}}_{{\mathrm{C}}_{12}}+{\mathrm{V}}_{\mathrm{C}{\prime }_{11}})(1-{\mathrm{e}}^{\frac{-\mathrm{t}}{\mathrm{T}}})-{\mathrm{V}}_{\mathrm{C}{\prime }_{11}}\end{array}\}$$

(26)

The time required for the capacitor C₁₂ to attain any value of V_C12 during the charging cycle is given in Equations (27) and (28).

When the initial voltage across the capacitor is positive:

$$\mathrm{t}=\mathrm{T}\log (\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{\mathrm{C}{\prime }_{12}}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{{\mathrm{C}}_{12}}})=({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}){\mathrm{C}}_{12}\log (\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{\mathrm{C}{\prime }_{12}}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{{\mathrm{C}}_{12}}})$$

(27)

When the initial voltage across the capacitor is negative:

$$\mathrm{t}=\mathrm{T}\log (\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}+{\mathrm{V}}_{\mathrm{C}{\prime }_{12}}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{{\mathrm{C}}_{12}}})=({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}){\mathrm{C}}_{12}\log (\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}+{\mathrm{V}}_{\mathrm{C}{\prime }_{12}}}{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\mathrm{V}}_{{\mathrm{C}}_{12}}})$$

(28)

The time required for the capacitor C₁₁ to attain any value of V_C11 during the charging cycle is given in Equations (29) and (30).

When the initial voltage across the capacitor is positive:

$$\mathrm{t}=\mathrm{T}\log (\frac{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{\mathrm{C}{\prime }_{11}}}{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{{\mathrm{C}}_{11}}})=({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}){\mathrm{C}}_{11}\log (\frac{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{\mathrm{C}{\prime }_{11}}}{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{{\mathrm{C}}_{11}}})$$

(29)

When the initial voltage across the capacitor is negative:

$$\mathrm{t}=\mathrm{T}\log (\frac{{\mathrm{V}}_{{\mathrm{C}}_{12}}+{\mathrm{V}}_{\mathrm{C}{\prime }_{11}}}{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{{\mathrm{C}}_{11}}})=({\mathrm{R}}_{\mathrm{D}}+{\mathrm{R}}_{\mathrm{S}}){\mathrm{C}}_{11}\log (\frac{{\mathrm{V}}_{{\mathrm{C}}_{12}}+{\mathrm{V}}_{\mathrm{C}{\prime }_{11}}}{{\mathrm{V}}_{{\mathrm{C}}_{12}}-{\mathrm{V}}_{{\mathrm{C}}_{11}}})$$

(30)

$$\begin{array}{l}{\mathrm{C}}_{12}=\frac{1}{2\mathsf{\pi }\mathrm{f}\mathrm{s}{\mathrm{X}}_{\mathrm{C}12}}=\frac{1}{2\mathsf{\pi }\mathrm{f}\mathrm{s}\frac{{\mathrm{V}}_{\mathrm{C}12}}{{\mathrm{I}}_{\mathrm{C}12}}}=\frac{{\mathrm{I}}_{\mathrm{C}12}}{2\mathsf{\pi }\mathrm{f}\mathrm{s}{\mathrm{V}}_{\mathrm{C}12}}\\ {\mathrm{C}}_{11}==\frac{1}{2\mathsf{\pi }\mathrm{f}\mathrm{s}{\mathrm{X}}_{\mathrm{C}11}}=\frac{1}{2\mathsf{\pi }\mathrm{f}\mathrm{s}\frac{{\mathrm{V}}_{\mathrm{C}11}}{{\mathrm{I}}_{\mathrm{C}11}}}=\frac{{\mathrm{I}}_{\mathrm{C}11}}{2\mathsf{\pi }\mathrm{f}\mathrm{s}{\mathrm{V}}_{\mathrm{C}11}}\end{array}\}$$

(31)

Voltage and current of all the capacitors are the same during the complete switching cycle. Thus the equal rating of all capacitors is suitable to design the proposed converter whose voltage rating is greater than the input voltage.

5. Comparison of Proposed Converter with Recent DC-DC Inductor-less Converters

In this section the proposed circuit is compared with recent transformer-less and inductor-less DC-DC converters (discussed in Section 2 of this article) in terms of number of controlled switches, diodes, capacitors, and voltage gain. The requirement of the number of switches to design DC-DC converters is tabulated in

Table 2. Number of switches required to design different DC-DC converters.

Converter Type	Number of Levels/Stages
	1	2	3	4	5	6	7	8	N
SPSC	1	4	7	10	13	16	19	22	3N − 2
FCMDC	2	4	6	8	10	12	14	16	2N
MMDC	2	6	12	20	30	42	56	72	N(N + 1)
Fibonacci	4	7	10	13	16	19	22	25	3N + 1
Switch Mode	4	8	12	16	20	24	28	32	4N
MMCCC	1	4	7	10	13	16	19	22	3N − 2
Proposed	2	2	2	2	2	2	2	2	2

.

It is observed that proposed converter requires less switches compared to other recent transformer-less and inductor-less converters. It is also observed that the requirement of switches is independent of the number of levels of the converter (only two switches are required to design the proposed converter). It is also observed that the requirement of the number of switches to design and MMCCC is the same. The requirement of the number of diodes and number of capacitors to design DC-DC converters is tabulated in

Table 3. Number of diodes required to design the DC-DC converters.

Converter Type	Number of Levels
	1	2	3	4	5	6	7	8	N
SPSC	1	4	7	10	13	16	19	22	3N − 2
FCMDC	2	4	6	8	10	12	14	16	2N
MMDC	2	6	12	20	30	42	56	72	N(N + 1)
Fibonacci	4	7	10	13	16	19	22	25	3N + 1
Switch Mode	4	6	8	10	12	14	16	18	2N + 2
MMCCC	1	4	7	10	13	16	19	22	3N − 2
Proposed	2	4	6	8	10	12	14	16	2N

and

Table 4. Number of capacitors required to design the DC-DC converters.

Converter Type	Number of Levels
	1	2	3	4	5	6	7	8	N
SPSC	1	2	3	4	5	6	7	8	N
FCMDC	1	2	3	4	5	6	7	8	N
MMDC	1	3	6	10	15	21	28	36	N(N + 1)/2
Fibonacci	1	2	3	4	5	6	7	8	N
Switch Mode	3	5	7	9	11	13	15	17	2N + 1
MMCCC	1	2	3	4	5	6	7	8	N
Proposed	2	4	6	8	10	12	14	16	2N

, respectively. It is observed that the proposed converter requires less diodes compared to recently proposed transformer-less and inductor-less DC-DC converters. The maximum number of diodes is required to design the Fibonacci converter. To design SPSC and MMCCC the number of diodes requirement is the same. It is observed that the proposed converter requires less capacitors compared to MMDCC and the switch mode converter. The proposed converter also requires fewer components in total compared to the other converters. In

Table 5. Voltage conversion ratio of the DC-DC converters.

Converter Type	Number of Levels
	1	2	3	4	5	6	7	8	N
SPSC	1	2	3	4	5	6	7	8	N
FCMDC	1	2	3	4	5	6	7	8	N
MMDC	1	2	3	4	5	6	7	8	N
Fibonacci	1	3	5	8	Not feasible to design for higher levels
Switch Mode	2	3	4	5	6	7	8	9	N + 1
MMCCC	1	2	3	4	5	6	7	8	N
Proposed	2	3	4	5	6	7	8	9	N + 1

voltage conversion ratio of recent inductor-less DC-DC converter is tabulated.

In Figure 20a–d the proposed converter is compared with DC-DC converters (discussed in Section 2) in terms of number of switches, diodes, capacitors and voltage gain. Graphically it is also observed that the proposed converter provides a viable solution in terms of number of components. In

Table 6. Cost of the proposed and recent DC-DC converters (discussed in Section 2).

Converter	Cost of the Converter
SPSC	(3N − 2) (Cost of each switch + cost of each diode) + N (cost of each capacitor)
FCMDC	2N (Cost of each switch + cost of each diode) + N (cost of each capacitor)
MMDCC	N(N + 1){(Cost of each switch + cost of each diode) + 0.5 (cost of each capacitor)}
Fibonacci	(3N + 1) (Cost of each switch + cost of each diode) +N (cost of each capacitor)
Switch Mode	4N (Cost of each switch) + 2(N + 1)(cost of each diode) + (2N + 1) (cost of each capacitor)
MMCCC	(3N − 2) (Cost of each switch + cost of each diode) + N (cost of each capacitor)
Proposed	2 (Cost of each switch) +2N (cost of each diode + cost of each capacitor)

the proposed converter is compared in terms of cost. It is calculated that the proposed converter required less cost compared to other DC-DC converters. Only two switches are required to design an N-stage proposed converter hence it requires a simple control circuit.

6. Experimental and Simulation Results of the Proposed Self-Balanced and Magnetic Component-Free Multistage DC-DC Converter

The proposed self-balanced and magnetic component-free multistage DC-DC converter simulation and experimental results are discussed in this section. The proposed multistage converter has been designed for four stages with rated power 60 W, switching frequency 100 kHz, output voltage is 100 V and the supply voltage is 24 V. Switches S_a (here S₁) and S_b (here S₂) are operated complementarily with a 50% duty cycle. High switching frequency is used to reduce the rating of the capacitor.

The output voltage and current waveform with ideal components (voltage drop across the switch and the diode is zero) is shown in Figure 21a. It is observed that the settling time for the output voltage of the proposed converter with ideal components (forward resistance of the diode is 0) is less than 2 ms. The effect of voltage drop across the diode is analyzed in the previous section. The output voltage and current waveform (assuming 1 V voltage drop across the switch and diode) are shown in Figure 21b.

It is observed that the settling time for the output voltage of the proposed converter with practical components is approximately 4 ms due to the forward resistance of the diode and switch. Thus, the practical waveform differs from the ideal waveform because of the time constant (R_D + R_S) C as explained in Section 4. The output power waveform and switch voltage are shown in Figure 22a,b, respectively. The output voltage and input voltage waveform with ideal components (voltage drop across the switch and the diode is zero) are shown in Figure 22c. The output voltage and input voltage waveform (assuming a 1 V voltage drop across the switch and diode) are shown in Figure 22d.

It is observed that 120 V output voltage is achieved from a 24 V input supply. Thus, ideally the voltage gain of the proposed converter is 5, which is equal to the number of stages +1. When the voltage drop across the diode is considered, an output voltage of 100 V is achieved from a 24 V supply. The voltage across the switch is equal to the input supply voltage (24 V). The voltage across all capacitors is same, which is equal to the input supply voltage (24 V) if the voltage drop across the diode is not considered. The voltage across all diodes is same (24 V) when the diode is reverse- biased. The voltage across diodes is shown in Figure 22e–f. The voltage across the capacitors is shown in Figure 23. The proposed 4-stage self-balanced and magnetic DC-DC converter is investigated experimentally and the result shows a good match with the simulation results. The hardware components are listed in

Table 7. Hardware component details of the proposed converter.

Sr/No	Components	Value	No. of Components
1	Switch (S1 and S2)	IRF250 (0.085 ON sate resistance)	2
2	Diodes	BYQ28E	8
3	Capacitors	220 μF, 50 V	8
4	Load	168 Ω, 60 W	1
5	Gate Driver IC	TLP250	2

.

PIC18F45K20 is used to generate pulses and TLP250 is used as driver IC. The hardware prototype of the proposed converter is shown in Figure 24.

Pulses are generated from a PIC controller and the gate driver output is shown in Figure 25a,b, respectively. Output voltage and input voltage waveform are shown in Figure 25c. It is observed that 100 V output is achieved from a 24 V input supply.

The output current waveform is shown in Figure 25d and it is observed that the output current is 0.619 A. The voltage across each capacitor is shown in Figure 26a–h. It is observed that the voltage across each capacitor is nearly the same and slightly less than the input voltage 24 V (an effect of the diode). Voltage stress across each diode is shown in Figure 27a–h. It is observed that the voltage stress across the diode is approximately the same and the peak voltage across the diode is slightly less than the input voltage (24 V) (an effect of the voltage drop). The voltages of all capacitors and all diodes differ slightly due to the forward resistance of the diode and switch. The lower stages (source side) capacitors are charged through the path which contain less diodes whereas as the number of stages increases the path followed for the charging of higher stage (moving towards load) capacitors contain more diodes. Thus, practically a slight difference is observed in the voltage of the capacitors.

7. Conclusions

The self-biased and magnetic-free multistage step-up converter is articulated and designed for unidirectional renewable photovoltaic applications. The proposed converter is well suited for renewable photovoltaic applications where the voltage needs to be stepped up without using magnetic components. The proposed converter also provides a viable solution to improve the photovoltaic systems in term of modularity, cost and control. The proposed converter is suitable for the DC link applications in DC-AC systems where capacitor voltage balancing is the main challenge. The proposed converter also provides a viable solution for low power applications, since the inductor and transformer are not required to design the proposed converter. Also Maximum Power Point Tracking (MPPT) can be easily implemented to improve the efficiency of the converter. The voltage across the switch is less; hence low voltage switches are used for designing high voltage converters. The conspicuous features of the proposed topology are:

(i)

Magnetic component-free (transformer-less and inductor-less)

(ii)

Continuous input current

(iii)

Low voltage rating semiconductor devices and capacitors

(iv)

Modularity

(v)

Easy to add a higher number of levels to increase the voltage

(vi)

Only two control switches with alternating operation and simple control are needed.

The proposed converter has been designed with a rated power of 60 W, the input voltage is 24 V, the output voltage is 100 V and the switching frequency is 100 kHz. High switching frequency has been used to decrease the component size. The performance of the proposed converter is verified through simulation and experimental results.