A Modular AC-DC Power Converter with Zero Voltage Transition for Electric Vehicles

Abstract

A study of the fundamental of operation of a three-phase AC-DC power converter that uses Zero-Voltage Transition (ZVT) together with Space Vector Pulse Width Modulation (SVPWM) is presented. The converter is basically an active rectifier divided into two converters: a matrix converter and an H bridge, which transfer energy through a high-frequency transformer, resulting in a modular AC-DC wireless converter appropriate for Plug-in Electric Vehicles (PEVs). The principle of operation of this converter considers high power quality, output regulation and low semiconductor power loss. The circuit operation, idealized waveforms and modulation strategy are explained together with simulation results of a 5 kW design.

1. Introduction

AC-DC power converters are typically used in Plug-in Electric Vehicles (PEVs) that require high reliability, reduced total harmonic distortion (THD) of the drawn currents and output regulation to charge batteries or supercapacitors with high performance and satisfy stringent power quality and density standards [1,2,3]. Electric Vehicle (EV) systems need to consider power quality regulations that typically include the harmonic emission during the charging and transient states, which have been analyzed with different standards and methods as the works described in [4,5]. Moreover, high-frequency switching techniques can increase the power quality, density and energy transfer reliability of AC-DC power converters without altering the basic topology configuration, keeping output controllability and reliability [6]; however, high AC line currents, drawn by the converter to rapidly charge the storage devices distributed along the traction DC link of the EV, may endanger the EV charger operator or impair the charger connector and, therefore, the supply drawn currents are limited to gain reliability causing slow energy transfer [7].

An available method of ensuring operator reliability with high currents, obtaining a simple way of connecting the charge uses wireless power transfer [8,9,10]. This is a twofold method, since the technique commonly uses a transformer to effectively isolate the power transfer from the user, and provides possible circuit splitting since the transformer is operated as an intermediary between two modules. For example, the converter presented in [11] uses a Medium-Frequency-Transformer for wind power conversion applications; however, the system uses an indirect matrix converter with three output phases that increases the circuit complexity and the magnetic components. EVs typically us two modules, where the first module is located on a charging station and the other on board the vehicle, improving the power density of the converter and increasing the EV distance range since the on-board section may be free of heavy devices [12]. The use of a single-phase high-frequency transformer was proposed in [13] as a wireless device to convert power from the utility to a DC-link capacitor bank; however, the circuit incurs in the use of several power stages required to generate high-frequency power signals from the utility supply to the transformer, limiting the efficiency of the converter and causing high complexity.

This paper presents the principle of operation of a modular AC-DC converter with Zero-Voltage Transition (ZVT), whose aim is to produce high-quality current waveforms, output regulation and soft switching of the semiconductor devices through the use of an off-board current-feed matrix converter and an on-board high-frequency H bridge, in such a way that the size of the converter located inside the vehicle becomes reduced in contrast with other topologies, [14,15,16]. The method potentially exhibits the following advantages: first, the current-feed matrix converter is used for straightforward generation of low-ripple, AC line currents without the need of several power stages; second a high-frequency transformer is used to isolate the matrix converter from the H bridge and regulate the output voltage; and third, the circuit uses a ZVT technique together with Space Vector Pulse Width Modulation (SVPWM) to achieve soft commutation of the power semiconductors and generate high-quality sinusoidal currents. Simulation results obtained in Saber with a 5 kW model are provided in the article, demonstrating the correspondence with the developed theoretical background and idealized waveforms to verify its feasibility.

2. ZVT AC-DC Converter

2.1. Circuit Description

The topology arises from the idea of splitting a conventional active rectifier in two modules as is shown in Figure 1. The off-board module of the converter is a three-phase current fed matrix converter that generates a single phase high-frequency current. This converter is intended to be located outside the electric vehicle in the charging station. The matrix converter has six bi-directional switches (Q₁–Q₆) and is fed by the line current of inductors L. The primary side of a high-frequency transformer is connected at the output of the matrix converter to allow wireless power transfer between the matrix converter and the second module.

The on-board module uses the secondary side of the high-frequency transformer and a series inductor, L_s, partially formed by the transformer leakage inductance and an additional inductor, together with an H bridge to regulate the output voltage, V_o. The H bridge inverts the output voltage with a phase-shifted Pulse Width Modulation (PWM) technique, such that a quasi-square with a ±nV_o amplitude is generated on the primary side of the transformer, v_prim. In this way, the conventional SVPWM technique is modified to obtain three-level PWM voltage waveforms which are used to control the line currents together with the supply voltage.

2.2. Principle of Operation

The control strategy used in the AC-DC converter is based in a SVPWM technique allowing DC output voltage regulation using an index modulation, being easy to implement with a fast response compared to other methods of PWM [17,18,19]. The conventional SVPWM technique is modified with a ZVT strategy, in such a way that the semiconductor devices are soft switched. The fundamental of operation of the SVPWM technique with ZVT is described below assuming negligible output voltage ripple and lossless components. Figure 2a–c show the active rectifier switching states, S_a, S_b and S_c, of a conventional SVPWM scheme for one switching period in the first sector, which ranges from 0° to 60°, where 1 and 0 indicate on and off states respectively. These switching states are splitted to define the switching states of the H bridge and those of the matrix converter.

The H-bridge switching states S_x and S_y are presented in Figure 2d,e, with a duty cycle of 50% and a short-circuit period, T_SV0H, that generates the voltages v_xG (Figure 2f), and v_yG (Figure 2g) referred to the G node of the DC rail. The H-bridge voltage (Figure 2h), v_xy = v_xG − v_yG, clamps the secondary side of the transformer to zero Volts when the H bridge is in the short-circuit state. During the first semi cycle, ∆T/2, the voltage in the secondary side of the transformer, v_sec, is clamped to V_o and the switching states of the matrix converter legs, S_am, S_bm and S_cm (Figure 2i–k) are equal to S_a, S_b and S_c respectively. When S_a, S_b and S_c are equalized in the three inverters legs, a short-circuit occurs; which is caused in the modular version through the H bridge during T_SV0H, such that the matrix converter retains the last switching state combination. During the second semi cycle, a mirrored state sequence occurs, since the output voltage in the H bridge becomes v_sec = −V_o and the switching states in the matrix converter are the complement of S_a, S_b and S_c. The H-bridge short-circuit is caused again and the matrix converter retains the last switching states when S_a, S_b and S_c are equal. In this way, the neutral combination is again caused by the H bridge instead of the matrix converter.

The matrix converter voltages referred to the DC rail node G, v_acG, v_bcG and v_ccG are shown in Figure 2l–n, which are the product of the primary voltage v_prim (v_prim = nv_sec) and the individual switching state of each leg. When the short-circuit is caused by the H bridge, the matrix converter voltages are clamped to zero Volts.

2.3. SVPWM Technique

Six active voltage space vectors, sv₁ to sv₆, are obtained at the central nodes of the matrix converter shown in Figure 1b by using six switching states combinations, SQ₁ to SQ₆, which are listed in

Table 1. Switching states vectors of matrix converter.

Switching State Combination	Sam, Sbm and Scm States
SQ1	(1, 0, 0)
SQ2	(1, 1, 0)
SQ3	(0, 1, 0)
SQ4	(0, 1, 1)
SQ5	(0, 0, 1)
SQ6	(1, 0, 1)

, with respect to the states of S_am, S_bm and S_cm. These space vectors are plotted in the bi-dimensional α-β plane of Figure 3 using the Clarke transform [20]. sv₁ to sv₆ are generated using the switching states of the matrix converter together with its output voltage ±nV_o. A neutral space vector, sv₀, is produced by using any state combination of the matrix converter together with the H-bridge short-circuit. sv₀ is located at the origin of the α-β plane.

An arbitrary averaged voltage vector, v_cav = V_cpk∟θ_c, can be generated at the converter input using a Volts-seconds balance to control the input line currents together with the supply voltages. Since the matrix converter output voltage reverses its biasing during half of the switching cycle, the Volts-seconds balance utilises the operating sector and its opposite sector of the α-β plane. For example, during the first semi cycle of a switching period in sector S₁, v_cav is determined by:

$$v_{cav}=a_{1}s{v}_1+a_{2}s{v}_2+a_{0}s{v}_0$$

(1)

where ${\alpha }_1=\frac{T_{sv1}}{\raisebox{1ex}{$\Delta T$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}$, ${\alpha }_2=\frac{T_{sv2}}{\raisebox{1ex}{$\Delta T$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}$ and ${\alpha }_0=\frac{T_{sv0H}}{\raisebox{1ex}{$\Delta T$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}$.

Whereas, during the second semi cycle, v_cav is defined by:

$$v_{cav}=a_{4}s{v}_4+a_{5}s{v}_5+a_{0}s{v}_0$$

(2)

where ${\alpha }_4=\frac{T_{sv4}}{\raisebox{1ex}{$\Delta T$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}$, ${\alpha }_5=\frac{T_{sv5}}{\raisebox{1ex}{$\Delta T$}\!\left/ \!\raisebox{-1ex}{$2$}\right.}$, since v_prim = −nV_o.

The same procedure applies for the rest of the sectors.

Table 2. Switching states vectors.

Angle θc	Sector	vprim (+)	vprim (−)
		Switching State	Switching State
1–60°	S1	SQ1, SQ2	SQ4, SQ5
61–120°	S2	SQ2, SQ3	SQ5, SQ6
121–180°	S3	SQ3, SQ4	SQ6, SQ1
181–240°	S4	SQ4,SQ5	SQ1, SQ2
241–300°	S5	SQ5, SQ6	SQ2, SQ3
301–360°	S6	SQ6, SQ1	SQ3, SQ4

summarizes the switching states according to the sector location of θ_c together with the biasing of v_prim.

v_xy and v_sec are shown in Figure 4a,b respectively for straight comparison to describe the generation of the secondary transformer current, i_LS, shown in Figure 4c. During the first semicycle, i_LS is assumed positive together with v_sec clamped to V_o. The slope of i_Ls is negative since the converter voltage is greater than the AC supply voltage even when the matrix converter switches from SQ₁ to SQ₂; whilst during the H-bridge short circuit the matrix switching state SQ₂ is retained, such that the slope of i_LS is inverted. A current reversal occurs in i_Ls since v_xy is clamped to −V_o and v_sec to zero during an overlap period T_ovl that is calculated with Equation (3):

$$T_{ovL}=\frac{n{I}_{primpk}{L}_s}{V_o}$$

(3)

where I_primpk is the peak magnitude of the current in the primary side of the transformer, i_prim.

In this way, the ZVT is performed in the semiconductor devices during the current reversal to obtain soft commutation. The overlap period finishes when i_LS reaches the same magnitude with an opposite sign, such that the first semi cycle becomes to an end. The second semi cycle is a mirror of the first since the complementary switching states of SQ₁ and SQ₂, SQ₄ and SQ₅ respectively, are used to operate the matrix converter and because the H bridge has clamped v_xy to −V_o.

i_Ls is equal to ni_prim, where i_prim depends on the switching of the line currents.

Table 3. i_LS magnitude for each switching state.

Switching State	iprim
SQ1	iprim = ia − ib − ic
SQ2	iprim = ia + ib − ic
SQ3	iprim = ib – ia − ic
SQ4	iprim = ib + ic – ia
SQ5	iprim = ic − ib – ia
SQ6	iprim = ia − ib + ic

lists the equivalence of i_prim respective to the line currents and the matrix switching states.

3. ZVT AC-DC Converter

A block diagram for the AC-DC operation of the circuit of Figure 1b is shown in Figure 5. In this figure θ_c and the index modulation, M_a, are the inputs required for the SVPWM scheme. Since the converter of Figure 1b is divided into two parts, a sequenced operation is used and described below:

(a)

The conventional active rectifier switching states are generated using M_a and θ_c. These are equivalent to the control signals of Figure 2a–c.

(b)

S_am, S_bm and S_cm, shown in Figure 2i–k, are generated and multiplexed to assign the control signals for each bi-direccional switch.

(c)

S_x and S_y, shown in Figure 2d,e, are generated from the active periods of the conventional active rectifier.

(d)

An overlap is required to turn on and off the bidirectional switches during the reversal of current i_LS.

3.1. H-Bridge and Matrix Converter Switching States

The derivation of the H-bridge and matrix converter control switching states is described using the block diagram of Figure 6, which are obtained from the switching states of the conventional active rectifier, as described in Section 2.2. Firstly, S_a, S_b and S_c are generated using θ_c and M_a. The conventional SVPWM active periods, T_a, T_b and T_c, are compared with a high-frequency carrier triangular waveform to produce three digital signals, PWM_a, PWM_b and PWM_c, which are shown in Figure 7. These signals are multiplexed with respect to the sector location to derive the switching states S_a, S_b and S_c, (Figure 7e–g). The H-bridge switching states, Q_a, Q_c, Q_b an Q_d, are obtained with a sequential circuit using S_a, S_b and S_c as inputs.

Other set of multiplexers are utilized to derive three digital signals, S_a’, S_b’ and S_c’, that produce the active switching states by using off and on states instead of the short and long pulse trains of PWM_a and PWM_c respectively, as is shown in Figure 7h–j. S_a’, S_b’ and S_c’ are also multiplexed with respect to the sector location and are processed to derive the switching state of each matrix converter leg. The digital circuit to generate the matrix converter control signals for the first leg, Q_1a, Q_1b, Q_4a and Q_4b, is shown at the right-hand of Figure 6. This circuit commutates the switching states to the opposite side of the α-β plane, sending the complement states when v_sec is clamped to negative voltage. The same circuit is used to generate the control signals for the second and third matrix converter legs.

3.2. Neutral-to-Active Switching Transition in the Matrix Converter

Since each bi-directional switch in the matrix converter is built with two semiconductor devices with a common collector configuration that allows the current flow in both directions, an overlap in all the matrix converter legs is required to commutate the flowing of current in one direction to the opposite direction during the negative biasing of v_sec. Figure 8 shows the switching sequence of Q_1a, Q_1b and Q_4a, Q_4b to turn off Q₁ and turn on Q₄.

In Figure 8a, Q_1a and Q_1b are conducting the current in the blue or red arrow direction, i_Q1. When Q₁ and Q₄ are commutated to the on and off states respectively, Q_1b is turned off and Q_4b is turned on when the current is flowing in the blue arrow direction; and Q_1a is turned off and Q_4a is turned on when the current is flowing in the red arrow direction (Figure 8b). Finally, when the current flow stops due to the biasing inversion of v_sec through the corresponding arrow, the transistors of Q₄ are turned on, (Figure 8c), and, therefore, the current in Q₄, i_Q4, flows in the opposite direction through the matrix converter leg.

The logic circuit that generates the overlap in the first matrix converter leg is included in the right-hand of Figure 6. This diagram shows the zero crossing detector signals C_z1 and C_z2 that are used to indicate the end of the overlap.

3.3. Active-to-Active Switching Transition in the Matrix Converter

The transition between two active vectors takes place twice in a switching period. In Figure 2a the transition occurs from SQ₁ to SQ₂ during the first semi cycle; whereas in the second semi cycle, the transition occurs from SQ₅ to SQ₄. The transition between adjacent active vectors implies a switching state change in one matrix converter leg. By instance, the state of the second matrix leg, S_bm in Figure 2, switches from the off to the on state producing an active-to-active transition. The turn on-to-off sequence of Q₃ and Q₆ is shown in Figure 9.

In Figure 9a, Q_6a and Q_6b are firstly turned on and the current flows in the red or blue arrow direction, i_Q6; then, in Figure 9b Q_6a and Q_3a are turned off and on respectively to allow the current reversal in the matrix converter leg when the current is flowing in the blue arrow direction; or Q_6b and Q_3b are turned off and on respectively to allow the current reversal when the current is flowing in the red arrow direction. In this figure, the transistors of Q₆ are turned on for a period of time t_D longer than the turning off time of the semiconductor device, t_r, to guarantee that the current stops flowing through it. This bidirectional switch configuration comes to an end when the transistor of Q₆ is turned off as shown in Figure 9c. Lastly, the sequence finishes by turning on transistors of Q₃, as shown in Figure 9d, with i_Q3 flowing in the opposite direction.

4. Steady-State Analysis and Parameters Selection

A steady-state analysis of the AC-DC modular converter is derived using the generalized diagram of Figure 10, where v_s is the three-phase source voltage vector, L is the line inductor, v_L is the line inductor voltage vector, v_cav is the converter voltage vector, n:1 is the transformer turns ratio that links the off-board AC-AC module with the AC-DC module; V_o is the DC output voltage and R is the output load.

Assuming a vectorial current control to drive the phase and magnitude of the line current i_L and produce high power factor, a phasorial diagram is shown in Figure 11 which describes the behavior of the AC-DC converter of Figure 1. In this diagram, v_s, v_L and v_cav are defined by:

v_s = V_spk∟0°,

(4)

v_L = V_Lpk∟90°,

(5)

v_cav = V_cpk∟ϕ°

(6)

In Figure 11 the amplitudes of v_cav and v_L are defined by:

$$V_{cpk}=\frac{V_{spk}}{\cos \phi }$$

(7)

$$V_{Lpk}=V_{cpk}\sin \phi$$

(8)

Whereas the current i_L is obtained with Equation (9):

$$i_L=\frac{v_L}{\omega L}$$

(9)

Considering the phasorial diagram of Figure 11, v_L is calculated using Equation (10):

$$v_L=v_s-v_c$$

(10)

Equations (9) and (10) are used to derive the amplitude of i_L, I_Lpk, which is defined by:

$$I_{Lpk}=\frac{V_{spk}tg\phi }{\omega L}$$

(11)

where ω = 2πf. Assuming ideal conditions, a power balance is derived:

$$P_{in}=P_{out}$$

(12)

where P_in and P_out are the input and output power converter respectively and are equivalent to Equation (13):

$$\frac{3V_{spk}{I}_{Lpk}}{2}=\frac{V_o^2}{R}$$

(13)

Substituting Equation (11) in (13), the power balance becomes:

$$\frac{3{V_{spk}}^{2}tg\phi }{2\omega L}=P_o$$

(14)

According to Figure 11, the AC-DC converter can operate under two extreme conditions; a minimum supply voltage, V_spkmin, obtaining a maximum phase, ϕ_max, with a maximum power demand at the output, P_omax; and a maximum supply voltage, V_spkmax obtaining a minimum phase, ϕ_min, with a minimum power demand at the output, P_omin. Therefore, ϕ_max and ϕ_min are obtained using Equations (15) and (16) respectively:

$${\phi }_{max}=t{g}^{-1}\frac{2P_{omax}\omega L}{3V_{spkmin}^2}$$

(15)

$${\phi }_{min}=t{g}^{-1}\frac{2P_{omin}\omega L}{3V_{spkmax}^2}$$

(16)

Considering P_omax = 5 kW, P_omin = 500 W, V_spkmin = 144 V and V_spkmax = 216 V, ϕ_max and ϕ_min are obtained for different values of L. Figure 12 is used to select the optimal L that allows an appropriate range of phase control. L was judged to be 3 mH, in such a way that ϕ can be ranged from 0.46° to 10.3°.

The voltage V_cpk is expressed in function of the modulation index, M_a, when the converter operates with a SVPWM scheme [14], as follows:

$$V_{cpk}=M_{a}n{V}_o\frac{\sqrt{3}}{4}$$

(17)

The minimum and maximum converter voltages, V_cpkmin and V_cpkmax, are utilized to obtain the minimum and maximum modulation indexes, M_amin and M_amax respectively, which are shown in (18) and (19):

$$M_{amin}=\frac{4V_{cpkmin}}{\sqrt{3}n{V}_o}$$

(18)

$$M_{amax}=\frac{4V_{cpkmax}}{\sqrt{3}n{V}_o}$$

(19)

where V_cpkmin = 144.004 Volts and V_cpkmax = 219.53 Volts were calculated using Equation (7) for V_spkmin and V_spkmax respectively. An optimal value for n was determined by using Equations (18) and (19) and ranging n from 2 to 10, such that the results are plotted in Figure 13. n was selected to be 5 since M_a can be set between 0.66 and 1 to control the amplitude of the converter input voltage. It was judged in this work that n should be 5 to allow the converter an appropriate SVPWM operation and leave a small upper range of M_a for the ZVT effects since the maximum value of M_a is 1.16 for SVPWM [20].

Equations (14) and (17) show that there is a compromise between the selection of the parameters n, ϕ and L to reach a wide range of M_a within the conventional active rectifier operation range.

5. Numerical Verification

To verify the principle of operation of the modular AC-DC converter and the SVPWM with ZVT control strategy, a simulation in Saber was performed using ideal components and the parameters listed in

Table 4. Simulation Parameters.

Parameter	Value
Source voltage va, vb and vc	180 V peak
Source frequency	60 Hz
Switching fequency	7.2 kHz
Input inductor L	3 mH
Index modulation Ma	0.628
Input resistor R	0.1 Ω
Leakage Inductance Ls	50 µH
Turns ratio n	5:1
Output voltage Vo	100 V
Output Power Po	5 kW

.

5.1. Verification of the Modified SVPWM

A Saber simulation was performed synchronizing the operation of the divided rectifier control signals with the fundamental frequency of the supply, using the scheme of Figure 14. I_Lpk is the current reference used to define θ_c and M_a for the SVPWM operation of the rectifier and cause high power factor as shown in Figure 11. The converter voltage was phase shifted to align the line currents with the supply using the vectorial control system of Figure 14. A reference current of I_Lpk = 19.54 A was used to obtain a 100 V, 5 kW output with high power factor supply. The component of V_cav in the q axis, V_cavq, was determined using Equation (7) and the phasorial diagram of Figure 11, V_cavq = 22.1 V, such that V_cavd = V_spk = 180 V, therefore, the phase between v_s and v_cav was φ = 7°.

To confirm the correct operation of the scheme shown in Figure 14, Figure 15 shows a Saber result plot of the supply and converter phases, θ_S and θ_C, for current references of 9.4 A and 19.54 A and cause 2.5 kW and 5 kW respectively. In Figure 15a a phase shift of 3° is obtained, whereas in Figure 15b the phase shift becomes of 7° since the current reference was increased. The effectiveness of the SVPWM rectifier operation of the circuit of Figure 1b was verified analyzing the Saber simulation results of the line currents and input voltages of the converter. Figure 16a shows Saber results of the source voltage v_aN and the line current i_a. The resultant line current i_a is sinusoidal with a 3.3% ripple. Figure 16b shows the five-level converter voltage, v_acN, to verify the correct operation of the space vector strategy. The current and voltage in the primary side of the transformer, i_prim and v_prim are shown in Figure 16c, where i_prim is the rectified version of the line currents, but, inverted in one quadrant of the switching cycle producing a high-frequency AC square current.

The operation of the H bridge was verified contrasting the conventional SVPWM states with the phase-shifted control signals of the H bridge. Figure 17 plots the Saber results of S_a, S_b and S_c (Figure 17a–c, respectively) in contrast to S_x and S_y (Figure 17d,e). The H-bridge input voltages v_xG and v_yG are shown in Figure 17f,g, respectively, and its difference v_xy is shown in Figure 17h. In the latter figure, v_xy is a ±V_o quasi-square waveform, whose zero level is effectively produced by the H-bridge overlap, which can be used to produce the neutral vectors required by the conventional rectifier states in a switching cycle.

The SVPWM strategy for the divided AC-DC converter of Figure 1b was verified by contrasting a switching cycle of the states S_am, S_bm and S_cm with S_a, S_b and S_c. The upper plot of Figure 18 shows S_a, S_b and S_c together with S_am, S_bm and S_cm; whilst the three-phase input converter voltages with respect to the G node of the DC link, v_acG, v_bcG and v_ccG, are shown in the lower plots of Figure 18 (Figure 18g–i) for straightforward comparison with those plotted in Figure 2. In these plots v_acG and v_ccG are positive and negative rectified waveforms of v_xy; furthermore, v_bcG becomes a fully AC waveform due to the state reversals of the matrix converter leg since this switching cell utilizes the active-to-active switching transition.

5.2. ZVT Verification

The effects of the ZVT in the transistors of the matrix converter were initially verified analyzing the quasi-square voltages v_xy and v_sec together with the transformer secondary current, i_sec = i_Ls, as shown in Figure 19 for direct comparison with Figure 4. In Figure 19a,b, during the first semi cycle, v_xy and v_sec are clamped to V_o such that i_Ls (Figure 19c) has a smooth negative slope; however, this slope becomes positive when the H bridge is in its overlap state to produce a neutral voltage vector at the converter AC input. A expanded portion of the first semi cycle of i_Ls is shown in Figure 19d.

At the beginning of the second semicycle, i_Ls is reversed in an overlap period of T_ovL = 3 µs, as shown in the expanded portion of Figure 19e, which was confirmed using Equation (3), since v_xy and v_sec are now clamped to −V_o and zero respectively; whereas the rest of the second semicycle i_Ls becomes a mirrored wave of the first, which is shown in the expanded portion of Figure 19f. i_Ls is an AC trapezoidal waveform that is shaped by the switched operation of the H bridge and the matrix converter, which needs to be controlled to ensure stability and prevent saturation by the aid of a DC blocking capacitor, or a peak current control [21], since a high-frequency transformer is used in the proposed converter.

A zero-voltage switching transition is achieved in the matrix converter legs due to the zero-voltage biasing of its bidirectional switches whilst i_Ls is being reversed. This was verified analyzing the voltage and current waveforms in the first matrix leg switches Q₁ and Q₄ when an i_LS reversal occurs. Figure 20 depicts the simulated switching transition result described in Figure 8 to turn on Q₄ and turn off Q₁.Initially in Figure 20, the switches of Q₁, Q_1a and Q_1b, and those of Q₄, Q_4a and Q_4b, are in the on and off states respectively. Later in Figure 20a, Q_1a and Q_4a have an overlap period that cause to the voltage of Q₄, v_Q4, decrease to zero, and then i_Q4 increases as shown in Figure 20b, achieving a ZVT turn on in Q₄ during the current reversal. Whereas i_Q4 increases, i_Q1 falls to set Q₁ to the off state, as shown in Figure 20c, which depicts a hard switch off transition. During the overlap, v_sec is clamped to zero and then biased to −V_o at the end of the overlap, whilst the current reversal in i_Ls occurs (Figure 20d).

Figure 21a shows the simulated results of the opposite switching transition to turn on Q₁ and turn off Q₄. Mirrored waveforms are obtained for i_Q1, i_Q4, v_Q1 and v_Q4 in contrast to Figure 20. The ZVT is shown in Figure 21b when i_Q1 becomes positive during the zero voltage in Q₁. v_sec is clamped to +V_o whilst i_Ls is reversed.

5.3. Steady-State Power Balance Verification

To verify the input-to-output active power balance, the DC output power was calculated by the aid of the H-bridge output current i_rect. The current i_Ls and i_rect are shown in Figure 22a,b, respectively. In these figures i_Ls is seen to be rectified by the H bridge since i_rect may become either ±i_Ls, during the ±V_o clamping of v_xy respectively or zero when the H bridge is in its short-circuit state. The average or i_rect, I_rect, was calculated using the simulation results shown in Figure 22, and it was found that I_rect = 50 A and, therefore, the output power is 5 kW, since the Saber simulation was performed assuming a constant DC output voltage of V_o = 100 Volts. In this fashion, the output power equalizes the active supply power, demonstrating the principle of operation of the AC-DC divided converter of Figure 1b.

To verify the high-quality supply currents the harmonic content in the line current i_a was calculated, as shown in Figure 23; the measured current THD was 4.43%, being the power rated at 5 kW. Two main current harmonic clusters were found at the harmonic order of n = 242 and n = 488, corresponding to the frequencies of 14.5 kHz and 29.28 kHz, which were increased in amplitude since four switching transitions take place between space vector combinations during a switching period.

The low order harmonic content of the input current was compared with the Standard EN61000-3-2 [22], for the limits of Class A converters. Figure 24 shows that the components are within the standard limits; for example, for n = 3, the amplitude is 0.39 A, 2% of the fundamental, that is less than limit, 2.3 A.

6. Comparison of the Proposed Converter with Other AC-DC Topologies

Table 5. Comparison with three other AC-DC converters.

	Topology	Proposed AC-DC Modular Converter	Three-Phase PFC Rectifier with DC-DC Converter, [14]	AC-DC Matrix Converter, [14]	Isolated On-Board Vehicle Battery Charger Utilizing SiC Power Devices, [15]	Inductively Coupled Multi-Phase Resonant Wireless Converter, [16]
Factor
Level		3	2	2–3	1–2	1
Supply voltage phases		3	3	3	1	1
Switching Devices		16 (4 on board)	12	12	6	6
THD		4.40%	<5%	<1%	4.20%	<5%
Switching losses		Virtual 0 W (ZVT)	241.1 W	165.2 W	0 W (using ZVT)	0 W (using ZVT)
Switching Frequency		7.2 kHz	10 kHz	10 kHz	250 kHz	83–88 kHz
Capability to reverse power flow		Yes	No	Yes	No	No
Possibility to split the converter		Yes	No	No	No	Yes
Output Power		5–20 kW	22.6 kW	20.4 kW	6.1 kW	1 kW
Efficiency		95.8% (estimated)	97.72%	96.80%	94%	93.34%
Total Volume On-Board Converter		1700 cm3 (Estimated)	8430 cm3	6668.5 cm3	1742 cm3	5250 cm3 (Estimated)
Power Density		10 kW/dm3 (Estimated)	3.8 kW/dm3	4.3 kW/dm3	5 kW/dm3	192 W/dm3 (Estimated)
Advantages over others		Reduces the size of the converter located on-boar the vehicle. The SVPWM together with ZVT generate high-quality sinusoidal currents with null switching losses	Eliminates harmonics, improves the power factor, great simplicity, stable and reliable operation	The volume of the reactive components is reduced. Passive components are not needed in intermediate steps	The switching frequency is increased, the size and weight is reduced	Full-range regulation from zero to full power without switching losses
Major Drawbacks		The efficiency can be reduced by using the transformer	Need to be followed by a step-down DC-DC converter. Passive components are required in intermediate steps	The converter is on-board the vehicle. When the switching devices reach the temperature of 145°, the maximum output power decreases	The conversion is made by three steps with intermediate passive components. Not suitable for high power applications	Not suitable for high power applications. More than transformers are used, increasing the losses

presents a detailed comparison of the proposed topology with four other AC-DC converters of different levels. The first row of this table is referred to the charging power levels for EVs, which are currently three according to the International Electrotechnical Commission standard IEC61851 [23]. Level 1 is for small on-board battery chargers with typical use in home or office; Level 2 is for medium power battery chargers that can be used in private or public outlets, and Level 3 is generally designed for a recharging station for commercial and public transportation. The proposed topology is intended for Level 3 applications, which justifies the use of a three-phase voltage supply.

Table 5 shows that the number of switching devices used in the proposed converter is slightly higher in contrast to the topologies described in [14,15,16]; however, only four of them are located on-board the vehicle. The use of the bidirectional switches in the matrix converter allows the possibility power flow reversal through the converter, being more suitable to future smart grids. The implementation of the proposed AC-DC modular converter is considering the use of high-frequency, nanocrystal magnetic materials for the transformer core. In this fashion, higher power capability may be obtained with distributed gapped cores, such as the used in [15], increasing the efficiency limit by the actual wireless coupling techniques used in actual AC-DC chargers for wireless electric vehicles [22].

7. Conclusions

The splitting of a conventional active rectifier into a matrix converter and an H bridge linked through a high-frequency transformer resulted in an AC-DC modular converter topology ideal for high power density applications. The converter portion on board makes the topology particularly attractive for PEV’s; nevertheless, the technique is suitable for other applications. A SVPWM technique with ZVT was proposed for the described converter which allows symmetric generation of virtually square current waves that are attractive for high-frequency wireless transmission of high power.

The topology was verified using a numerical prediction performed in Saber which resulted in high-quality supply currents with a current THD of 4.43%. An input-to-output power balance was verified ensuring reliable power transmission. The high-frequency switching of 7.2 kHz allowed ZVT of the semiconductor devices, since a short overlap period was caused by a simple sequential logic circuitry which aids to the reduction of the switching power losses of typical SVPWM schemes; nevertheless, semiconductor current monitoring is required to obtain correct switching behavior of the matrix converter.

Future aims of research of this topology consider its practical development at higher switching frequencies, allowing further reduction of size and weight, possibility of wireless power transmission, which would be particularly attractive for reliable and risk free charging of electric vehicles. Furthermore, the application of the proposed topology could be examined for other power electronic topologies.