2.1. Dual-Sequence Current Control
For a three-phase, three-wire VSC system, the zero-sequence components are not present. Therefore, the instantaneous active and reactive powers measured at the point of common coupling (PCC) can be expressed by [
29]:
where
and
are the voltage and current vectors at the PCC; the subscript “⊥” represents a 90°-lagging version of the original vector; the superscripts “+” and “−” refer to the positive- and negative-sequence components; the operator “·” refers to the dot product of vectors;
and
are positive-sequence powers originating from positive-sequence components, while
and
are negative-sequence powers resulting from negative-sequence components;
and
are the oscillating power terms, whose average value is zero.
The dual-sequence current control strategy of a VSC mainly depends on how its current references are generated [
5]. Even though the current references can be formulated in various ways, a common feature of these strategies is that they can feed positive- and negative-sequence short circuit currents simultaneously. Therefore, the current references can be decomposed into positive- and negative-sequence components, and can be expressed by Equations (
3) and (
4) in a more general form [
30]:
where
a,
b,
c and
d are the four factors that determine the control strategy;
and
are the active and reactive power references, respectively. By substituting Equations (
3) and (
4) into Equations (
1) and (
2), the instantaneous powers can be simplified as
Since the average value of the oscillating power terms is zero,
and
have to be satisfied so that the output powers from the VSC satisfy its power references [
30]. This indicates that the control strategies can be characterized by two factors,
a and
c, which represent the share of the positive-sequence active and reactive powers, respectively. Therefore, different control strategies can principally be considered to be different combinations of the sequence output powers. In the following text, current references with Equations (
3) and (
4) will be used to represent the short circuit response of VSC-based sources in the proposed fault analysis method.
2.2. Algorithm
For balanced fault analysis using the conventional method, changes in the network voltages caused by a fault are equivalent to those caused by a voltage source at the fault terminal when all other voltage sources are short-circuited. For unbalanced faults, the analysis is conducted by algebraically manipulating the Thevenin equivalent circuits of sequence networks, as seen from the fault location, according to the fault types. However, the conventional method cannot be directly applied if a VSC exists in the system. When Equations (
3) and (
4) are used, both positive- and negative-sequence networks are shown to be active, while the conventional method assumes the negative-sequence network is passive. In addition, the formation of Equations (
3) and (
4) indicates that VSCs should be treated as voltage-dependent current sources whose magnitudes and phases rely on the voltages at the PCC. However, current injections from VSCs can also alter the PCC voltages to some extent depending on the strength of the grid. This means an iterative method is necessary to solve the problem.
The proposed fault analysis method firstly converts all synchronous generators (SGs) under fault conditions into their equivalent Norton’s circuits. For the
i-th SG with an internal voltage,
, and direct transient reactance,
, its current injection,
, and parallel admittance,
, in positive-sequence are expressed by
It is worth mentioning that SGs do not inject negative-sequence current, as only a positive-sequence electromotive force is developed. However, SGs provide negative-sequence current paths through their negative-sequence admittance which can be modeled by [
31]:
where
and
are the direct and quadrature sub-transient reactances for the
i-th SG, respectively. Then, ignoring all converters but not their interface transformers, the bus admittance matrix
,
and
for the positive-, negative- and zero-sequence networks as well as the corresponding bus impedance matrix
,
and
can be derived in a conventional way.
Secondly, the current references of a VSC using Equations (
3) and (
4) can be rewritten as
where the subscript
represents the quantities related to the
j-th converter;
m denotes quantities after the
m-th iteration;
and
are the control strategy factors for the
j-th converter, which should be given prior to the fault analysis. Then, the current injection vectors in the positive- and negative-sequence networks can be expressed by Equations (
11) and (
12), where a zero means there is no current injection at the corresponding bus.
The system under fault conditions can be considered to be a superposition of the normal network and the faulted network. The normal network consists of the three independent bus impedance matrices,
,
and
, and the current injection vectors
and
. Then, the bus voltages in all three sequences raised by the current injections,
and
, can be calculated as
On the other hand, the faulted network is defined by the boundary conditions which are based on the fault type. The boundary conditions are the same as for the conventional method, where a two-phase fault means parallel-connecting positive- and negative-sequence networks, a single-phase-to-ground fault means that all three sequence networks are series-connected, while a two-phase-to-ground fault means all three-sequence networks are parallel-connected. From the calculations in Equations (13) and (14), the sequence voltages as seen from the faulted bus
f in the normal network can be identified as
and
. Given the bus impedance matrices
,
and
, the self-impedances of the bus
f in each sequence network can be identified as
,
and
. Therefore, the boundary conditions for different types of faults can be illustrated by the circuits in
Figure 1, where
represents the fault impedance.
For a single-phase-to-ground fault, the fault current after the
m-th iteration can be obtained based on
Figure 1a:
For a two-phase fault, the fault current after the
m-th iteration can be obtained based on
Figure 1b:
For a two-phase-to-ground fault, the fault current after the
m-th iteration can be obtained based on
Figure 1c:
Then, the voltage drops on all buses caused by the fault in each sequence network can be calculated by
Finally, the sequence voltages after the
m-th iteration on all buses are updated using the superposition:
For the next iteration, the sequence voltages of all converter terminals obtained by Equations (24)–(26) are substituted into Equations (
9) and (
10) to update the current references. The whole procedure from Equation (
9) to Equation (
26) is repeated until the current references of all converters reach convergence.
Figure 2 presents the flow chart of the proposed fault analysis method.
2.3. Verification
The proposed fault analysis method was firstly tested on a modified IEEE 9-bus system, as shown in
Figure 3. The modifications to the original system [
32] were (1) the system voltage level was increased to 400 kV; (2) the synchronous generators connected to bus 6 and bus 10 were replaced by VSC1 and VSC2, respectively. The current references of both converters under grid unbalanced faults were in the form of Equations (
3) and (
4); (3) one more bus (bus 2) was added compared to the original system; (4) the parameters of all transmission lines, transformers and machines were replaced by real data.
Figure 4 illustrates the sequence networks when there is a fault at bus
f. In the positive-sequence network, there were three current injections,
(from SG),
and
(from VSC1 and VSC2), while in the negative-sequence network there were two current injections
and
(from VSC1 and VSC2). Therefore, Equations (
11) and (
12) became
Prior to the fault, VSC1 and VSC2 were delivering 165 MW and 75 MW active power, respectively, at the unity power factor. The voltage on bus 1 was maintained at 1 p.u. It was assumed that under fault conditions there were
MW,
Mvar for VSC1 and
MW,
Mvar for VSC2. For VSC2, the control strategy was characterized by
(providing only positive-sequence short circuit powers
and
). For VSC1, the control strategy (characterized by
and
) was varied under different scenarios which are summarized in
Table 1. For the purpose of verifying the calculated results, the system shown in
Figure 3 was also modeled in a RTDS. The dual-sequence current control block diagram of the VSCs under fault conditions is illustrated by
Figure 5, where two current control loops implemented in the synchronous refernece frame were used to track the positive- and negative-sequence current references. The angle
used by the Park transformation was obtained by the Dual Second Order Generalized Integrator Phase Locked Loop (DSOGI-PLL) presented in [
33]. The results calculated from the proposed fault analysis method were compared with the RTDS simulations for verification. For example, with a solid A–B fault or A–g fault on bus 4,
Figure 6 presents the RTDS simulations of the sequence voltages of the faulted bus (bus 4) and the PCC points (bus 6 and 10) in two scenarios: A–g fault with S3 and A–B fault with S4. For these two scenarios,
Figure 7 presents the simulated short circuit currents from the VSCs. As a summary for the different scenarios,
Table 2,
Table 3,
Table 4 and
Table 5 compare the RMS values of the sequence voltages as well as the RMS values of the sequence currents contributed by the VSCs during the fault. It can be observed that the results obtained from the proposed method agree with the simulations. This verifies that the proposed method is able to perform static fault analysis considering the dual-sequence current control of VSCs. Errors could arise from the fact that the short-circuit impedance of a synchronous generator is a time-varying quantity, and RTDS performs the simualtions in real time. The power system in RTDS was modeled with details for all the components. During the fault, the system’s dynamics cannot be completely reflected by the static fault analysis.
By comparing the results from S1 with S4, it can be seen that changes in sequence active powers (, ) do not alter the retained grid voltages notably. However, when comparing S1, S2 and S3, it can be observed that changes in sequence reactive powers (, ) have more effects on the retained voltages. This is reasonable since the voltages of an inductive grid are mainly regulated by reactive power. Different control strategies could yield different values for factor c, hence changing the combination of and .