Large-Signal Stabilization of Three-Phase VSR with Constant Power Load

Abstract

As an important interface converter, the three-phase voltage-source rectifier (VSR) connects the grid to DC-input converters. The constant power load (CPL) characteristic of the converter-load often causes large-signal stability problems. In order to solve this problem, the stability boundary of the VSR with CPL is analyzed based on the mixed potential theory, and the stability condition under large-signal disturbance is obtained; thus, the jump range of the load power can be estimated. To improve the stability of the system, a voltage loop control scheme based on ADRC is proposed. A theoretical analysis based on the mixed potential theory shows the proposed scheme expands the power jump range of the VSR with CPL effectively, and improves its disturbance rejection performance. Finally, experimental results prove the effectiveness of the proposed control scheme.

1. Introduction

In order to achieve the goal of multi-functionality, low-cost and high reliability, modularization has become an important trend in power electronics [1,2,3]. In the process of modularizing power electronic devices, the situation of converters as loads becomes more and more common, and has attracted wide attention [4,5]. As important interface converters, three-phase voltage-source rectifiers (VSRs) connect the grid to DC-input converters, and are widely used in the fields of electric vehicle charging [6], DC micro-grid [7], more electric aircrafts (MEAs) [8], and photovoltaic generation [9].

Many academic papers have focused on stability issues related to three-phase VSRs (or voltage-source inverters, VSIs). In [10], bifurcation and large-signal stability of VSR are analyzed under grid voltage dips, and the stable operating region is identified. Mehrasa M. and Pouresmaeil E. use direct Lyapunov method to discuss a series of stability issues of VSRs applied in different power sectors such as modular multilevel converters (MMCs) [3,11], shunt active power filters [12], and distributed generation [13,14]. A dynamic model in d-q frame with six independent dynamical state variables is obtained, and global asymptotical stability is achieved by the use of direct Lyapunov method [11]. Furthermore, a multi-loop control strategy is proposed to provide stable operation under both MMC’s arm inductance and resistance parameters variations, and also loads changes [3].

However, the above studies do not focus on the effect of load characteristics on the stability of VSR. Figure 1 shows the schematic of a three-phase VSR cascaded with a DC-input converter. In this situation, for VSR, the load is no longer a resistance, but a converter with a constant power load (CPL) characteristic because of its closed-loop control. The CPL causes stability problems easily [15,16,17]; moreover, the problems are more significant when the DC-bus capacitance is a small-capacity film capacitor to improve the system life and reliability. Some scholars have discussed this problem and put forward some solutions based on small signal stability theory, such as the passive damping method [18,19], sliding mode control method [17], virtual impedance (active damping) method [20,21,22], and so on. However, when the cascaded system suffers from a large-signal disturbance such as load power jump or grid voltage drop, the small signal stability theory is no longer applicable, because the theory only studies the stability problems near the operating point.

The problems of large-signal stability in converters with CPLs were analyzed in some literature in recent years [16,23,24]. In [23], the large-signal stability region of a DC/DC converter is estimated by a small signal loop. The norm inequalities are used to get the sufficient conditions for converter stability in order to estimate the stable region of the system. Furthermore, the effect of the small signal loop gain on the large-signal stability region is revealed. In [24], the Hamiltonian function method is used to discuss the influence of pulse load on the stability of the system, and some details of the transient response are shown. It indicates that pulse load has special effect on the stability of cascaded systems. For example, the system is in an unstable state when the load is connected, however it may attenuate to a stable state during the load disconnection. In general, it was called a metastable state. In [16], the influence of the negative impedance characteristic of CPLs on the stability of the converter is studied based on the mixed potential theory. In addition, a method to improve the large-signal stability in the cascade system is proposed with multistage LC filters. However, this method requires additional passive components, which increases the volume of the device.

On the premise of no additional circuits, some meaningful work on control methods has been undertaken to improve the large-signal stability of converters with CPLs [25,26,27,28]. The sliding mode control method to improve the stability of VSR is proposed in [25]. In this method, the voltage loop is controlled by sliding mode, and the state observer of the real-time power of the system is designed to observe the power. Furthermore, the parameters of the state observer are derived from the Lyapunov stability theorem. However, for different systems, there is no uniform method to establish the Lyapunov function, so the realization process of the control algorithm is relatively complicated. Moreover, due to the boundary of the current and grid voltage, the range of attraction area for large-signal disturbance is limited, which limits its practicality. In [26], a “stabilizing agent” is implemented on each CPL to reduce the negative impedance characteristic to solve the DC micro-grid stability problem. Thanks to the improved fault tolerance of the solution, the method permits us to consider several fault scenarios, such as the electrical reconfiguration, or the failure of an agent. In [27], multiple linear controllers are designed at different operating points of a three-phase VSR and switched according to certain rules. When the load changes, the drop and overshoot of DC bus voltage are both significantly reduced. The stability of the control method is proved by the general Lyapunov functions. To improve the dynamic performance of three-phase VSR with large-signal disturbance, a direct voltage control method based on feedback linearization is proposed in [28]. The scheme breaks through the conventional double closed-loops control mode, and directly controls input variables by voltage error, so as to stabilize the bus voltage rapidly. However, this scheme relies on an accurate mathematical model of the circuits. Some abnormal operating conditions, such as the imbalance of the grid voltage, would lead to poor control performance.

Active disturbance rejection control (ADRC) has been widely studied because of its excellent immunity against disturbance sources [29,30,31], and has been applied to motion control [30], power electronics, and so on [31]. However, the stability of converters with ADRC has not been adequately analyzed, especially for large-signal stability problems.

In this paper, the authors are discussing the large-signal stability of three-phase VSRs with CPL. The main contributions are triple:

(1)

Obtaining a large-signal model of three-phase VSR with CPL based on mixed potential theory, whose stable boundary is derived when load power jumps.

(2)

Proposing a voltage control scheme to improve the large-signal stability based on ADRC, and whose control stability is proven.

(3)

Deriving the stable boundary of VSR with CPL based on ADRC, which proves that the proposed control scheme expands the load power jump range effectively.

The rest of this paper is organized into four sections. Following the introduction, a large-signal stability analysis based on mixed potential theory under PI control is provided in Section 2. The proposed control scheme based on ADRC and the stability analysis of it is presented in Section 3. Moreover, the effectiveness of the control scheme is verified by experiments in Section 4. Finally, some conclusions are drawn in Section 5, and an Appendix A is given after that.

2. Large-Signal Stability Analysis Based on Mixed Potential Theory under PI Control

2.1. Introduction to the Mixed Potential Theory

The mixed potential theory is a method to study the stability of nonlinear circuits by constructing Lyapunov functions, especially for circuits with CPLs [32,33]. The mixed potential functions are functions related to energy, which are composed of current potential functions and voltage potential functions. The core content of the theory is to establish mixed potential functions to satisfy certain stability theorems, and finally, to obtain the ranges of the system parameters to ensure stability.

The mixed potential function P consists of resistance, capacitance, and inductance in a nonlinear network. Assume i₁, …, i_r represents inductor currents, and v_r+1, …, v_r+s are capacitor voltages. P is defined as:

$$P={\displaystyle \int {\displaystyle \sum _{\mu >r+s}{v}_{\mu }d{i}_{\mu }}}+{\displaystyle \sum _{\sigma =r+1}^{r+s}{i}_{\sigma }{v}_{\sigma }}$$

(1)

In Equation (1), the first item on the right is the current potential of all the non-storage elements; the second is the sum of energy in capacitors. If v_μ can not be represented by i_μ, the current potential can be written by voltage potential and Equation (2):

$${\displaystyle \int v_{\mu }d{i}_{\mu }}=v_{\mu }{i}_{\mu }-{\displaystyle \int i_{\mu }}d{v}_{\mu }$$

(2)

The relationship between P and the system state equation can be described as:

$$\{\begin{array}{l}L\frac{d{i}_{\rho }}{dt}=\frac{\partial P}{\partial i_{\rho }}\\ -C\frac{d{v}_{\sigma }}{dt}=\frac{\partial P}{\partial v_{\sigma }}\end{array}$$

(3)

where L and C are inductance and capacitance respectively in the circuit.

Equation (3) gives the criterion to verify the validity of the mixed potential functions. Generally speaking, the unified form of P is:

$$P(i,v)=-A(i)+B(v)+(i,\gamma v-\alpha )$$

(4)

where A(i) and B(v) represents the current potential and voltage potential of the non-storage elements in the circuit respectively, (i, γv − α) represents the energy of capacitors and parts of non-storage elements in the circuits, where γ is a constant matrix not necessarily associated with circuit topology with elements ±1, 0, and α is constant vector.

2.2. Stability Problems of the Three-Phase VSR with CPL

Because VSRs are often used as grid interface converters, their loads are usually not resistors, but power electronic converters. Power electronic converters are usually controlled by closed loops; therefore, they are regarded as CPLs. Taking the DC/DC converter as an example of the load, when the input current suddenly rises, the input voltage will decrease in order to maintain the output constant. The characteristic of maintaining constant power is called the CPL characteristic. This characteristic is bad for the stability, which will be explained below.

Take the voltage source in series with CPL as an example, as shown in Figure 2. When the CPL is disturbed to cause the input current i_CPL to rise, in order to maintain its output constant, the input voltage v_CPL of the CPL will decrease. However, this will lead to an increase in the voltage on the resistance Rs to make the current i_CPL rise again. This response, similar to positive feedback, takes the circuit away from the operating point, and causes it to lose stability. The larger the disturbance, the more significant stability problems caused by CPL will be.

2.3. Analysis of Power Jump Range of Three-Phase VSR with CPL

The average model equivalent circuit of three-phase VSR with CPL in dq coordinates system is shown in Figure 3. Neglecting the power loss, Equation (5) can be obtained based on the power balance.

$$i_o=\frac{v_d{i}_d+v_q{i}_q}{v_{dc}}$$

(5)

where v_d,q are the control voltage in the dq coordinates respectively, i_d,q are the grid current in the dq coordinates respectively, i_o is the output current of the equivalent current source on the DC side, and v_dc is the output voltage of the VSR.

According to the mixed potential theory, the current potential function of non-storage elements in the circuit is:

$$\begin{array}{ll}{\displaystyle \int {\displaystyle \sum _{\mu >r+s}{v}_{\mu }d{i}_{\mu }}}& ={\displaystyle {\int }_0^{i_d}{e}_{d}d{i}_d-{\displaystyle {\int }_0^{i_d}R{i}_{d}d{i}_d-{\displaystyle {\int }_0^{i_d}{v}_{d}d{i}_d}}}+{\displaystyle {\int }_0^{i_d}3\omega L{i}_{q}d{i}_d}+{\displaystyle {\int }_0^{i_q}{e}_{q}d{i}_q}\\ & -{\displaystyle {\int }_0^{i_q}R{i}_{q}d{i}_q-{\displaystyle {\int }_0^{i_q}{v}_{q}d{i}_q}}-{\displaystyle {\int }_0^{i_q}3\omega L{i}_{d}d{i}_q}+{\displaystyle {\int }_0^{i_o}{v}_{dc}d{i}_o}-{\displaystyle {\int }_0^{i_L}{v}_{dc}d{i}_L}\end{array}$$

(6)

where v_d,q are the control voltage in the dq coordinates respectively, R is the equivalent series resistance of the grid side, i_L is the load current of the VSR.

The potential energy stored in the capacitor in the circuit is:

$${\displaystyle \sum _{\delta =r=1}^{r+s}{i}_{\delta }{v}_{\delta }=-i_o{v}_{dc}+P_{CPL}}$$

(7)

where P_CPL is the power of the CPL.

From Equations (6) and (7), the mixed potential function of the system can be obtained as:

$$\begin{array}{ll}P\left(v,i\right)={\displaystyle \int {\displaystyle \sum _{\mu >r+s}{v}_{\mu }d{i}_{\mu }}}+{\displaystyle \sum _{\delta =r=1}^{r+s}{i}_{\delta }{v}_{\delta }}=& e_d{i}_d+e_q{i}_q-\frac{1}{2}R{i}_d^2-\frac{1}{2}R{i}_q^2-{\displaystyle {\int }_0^{i_d}{v}_{d}d{i}_d}-{\displaystyle {\int }_0^{i_q}{v}_{q}d{i}_q}\\ & +{\displaystyle {\int }_0^{i_d}3\omega L{i}_{q}d{i}_d}-{\displaystyle {\int }_0^{i_q}3\omega L{i}_{d}d{i}_q}-{\displaystyle {\int }_0^{v_{dc}}{i}_{o}d{v}_{dc}}+{\displaystyle {\int }_0^{v_{dc}}\frac{P_{CPL}}{v_{dc}}}d{v}_{dc}\end{array}$$

(8)

According to Equation (3), the relationship between P and the state equations of the circuit can be used to verify the correctness of the function:

$$\{\begin{array}{l}\frac{\partial P}{\partial i_d}=e_d-R{i}_d-v_d+3\omega L{i}_q=L\frac{d{i}_d}{dt}\\ \frac{\partial P}{\partial i_q}=e_q-R{i}_q-v_q-3\omega L{i}_d=L\frac{d{i}_q}{dt}\\ \frac{\partial P}{\partial v_{dc}}=-i_o+\frac{P_{cpl}}{v_{dc}}=-C\frac{d{v}_{dc}}{dt}\end{array}$$

(9)

This indicates that Equation (9) satisfies the form Equation (3), which proves that the mixed potential function P is correct.

The proportional integral (PI) regulators are commonly used to control voltage and current of the three-phase VSR, as shown in Figure 4. The control loop equations are:

$$\{\begin{array}{}\left(10\mathrm{a}\right)& v_d=-\left(K_{ip}\left(i_{dref}-i_d\right)+K_{ii}{\displaystyle \int \left(i_{dref}-i_d\right)dt}\right)+3\omega L{i}_q\left(10\mathrm{b}\right)& v_q=-\left(K_{ip}\left(I_{qref}-i_q\right)+K_{ii}{\displaystyle \int \left(I_{qref}-i_q\right)dt}\right)-3\omega L{i}_d\left(10\mathrm{c}\right)& i_{dref}=K_{vp}\left(V_{dcref}-v_{dc}\right)+K_{vi}{\displaystyle \int \left(V_{dcref}-v_{dc}\right)dt}\end{array}$$

where V_dcref is the output voltage reference of the VSR, I_qref is the current reference of the q axis, ω is the frequency of the grid, K_ip and K_ii are the proportion and integral coefficients of PI regulator of d axis current and q axis current respectively, K_vp, K_vi are the proportion and integral coefficients of PI regulator in voltage loop, respectively.

According to Appendix A, the current potential function of the circuit is a second order matrix:

$$\mathit{A}\left(i\right)=\left[\begin{array}{cc}-e_d{i}_d+\frac{1}{2}R{i}_d^2+{\displaystyle {\int }_0^{i_d}{v}_{d}d{i}_d+{\displaystyle {\int }_0^{i_d}3\omega L{i}_{q}d{i}_d}}& 0\\ 0& -e_q{i}_q+\frac{1}{2}R{i}_q^2+{\displaystyle {\int }_0^{i_q}{v}_{q}d{i}_q-{\displaystyle {\int }_0^{i_q}3\omega L{i}_{d}d{i}_q}}\end{array}\right]$$

(11)

and the voltage potential function is a first order matrix:

$$\mathit{B}\left(v\right)=-{\displaystyle {\int }_0^{v_{dc}}{i}_{o}d{v}_{dc}+{\displaystyle {\int }_0^{v_{dc}}\frac{P_{CPL}}{v_{dc}}d{v}_{dc}}}$$

(12)

In order to analyze the stability, the second order partial derivatives of A(i) and B(v) are solved as:

$${\mathit{A}}_{\mathit{i}\mathit{i}\mathbf{\_}\mathit{P}\mathit{I}}\left(i\right)=\frac{{\partial }^2\mathit{A}\left(i\right)}{\partial i^2}=\left[\begin{array}{cc}R+K_{ip}& 0\\ 0& R+K_{ip}\end{array}\right]$$

(13)

$${\mathit{B}}_{\mathit{v}\mathit{v}\mathbf{\_}\mathit{P}\mathit{I}}\left(v\right)=\frac{{\partial }^2\mathit{B}\left(v\right)}{\partial v^2}=\frac{K_{vi}{K}_{ip}{i}_{d}C\left(V_{dcref}-v_{dc}\right)}{e_d{i}_d-P_{CPL}}-\frac{K_{vp}{K}_{ip}{i}_d}{v_{dc}}+\frac{v_d{i}_d-P_{CPL}}{v_{dc}^2}$$

(14)

According to the mixed potential stability theorem in the Appendix A, the sufficient condition for the stability of the three-phase VSR with CPL under large-signal perturbation is:

$$P_{CPL\_PI}<\frac{C(R+K_{ip})}{3L}{v}_{dc}^2-K_{vp}{K}_{ip}{v}_{dc}{i}_d+v_d{i}_d+\underset{M}{\underbrace{\frac{K_{vi}{K}_{ip}C{v}_{dc}}{e_d{i}_d-P_{CPL\_PI}}\left(V_{dcref}-v_{dc}\right)}}$$

(15)

By Equation (15), the maximum power jump range of the three-phase VSR with CPL can be estimated. This result is used on the one hand to measure the performance of the VSR, and on the other hand, as a technical requirement to improve the parameter design. It is worth noting that because this result is a sufficient condition for large-signal stability, it is somewhat conservative.

3. Control Scheme and Stability Analysis Based on ADRC

In the case of disturbance, the principle of PI regulators is to compensate for errors which occur in the integrator. However, when the disturbance is large, the delay effect of the integrator makes the regulator unable to quickly and accurately obtain the disturbance information and compensate, which easily leads to instability. Therefore, a control scheme based on ADRC with excellent immunity is proposed to enhance the stability of VSR with CPL under large-signal disturbance.

The general structure of ADRC is shown in Figure 5. It includes the expanded state observer (ESO), the state error feedback (SEF), the transient profile generation (TPG) and the rejection. ADRC is not dependent on the mathematical model of the controlled plant. All the uncertain disturbances acting on the controlled plant are considered as “uncertain disturbances”, and the input and output signals are used to estimate and compensate for them. Thanks to the ESO and rejection, ADRC has omitted the integral part compared with the conventional PI regulator. This characteristic coincided with the need to improve the stability under large-signal disturbance. In this paper, a linear ADRC is proposed and the parameters can be simplified by ESO bandwidth and system bandwidth, which makes it easy to set.

3.1. Voltage Loop Control Scheme Based on the First Order ADRC

The control block of the voltage loop of three-phase VSR based on ADRC is shown in Figure 6. For the three-phase VSR with CPL, the DC side voltage equation is:

$$C\frac{d{v}_{dc}}{dt}=\frac{e_d{i}_d-R{i}_d^2}{v_{dc}}-\frac{P_{CPL}}{v_{dc}}$$

(16)

Ignoring the equivalent series resistance R and matching the form of ADRC plant, Equation (16) is rewritten as a first order differential equation:

$$\dot{y}=w+bu$$

(17)

where $w=-2P_{CPL}/C$ is the external disturbance, $u=i_{dref}$ is the reference of d-axis current, $b=2e_d/C$ is the control gain, and $y=v_{dc}^2$ is the input of ADRC.

Assume $b_0\approx b$ is the estimation of control gain. Let $x_1=y$, uncertain disturbance (including external disturbance and internal disturbance) $f\left(y,\dot{y},u\right)=w+\left(b-b_0\right)u$. Then, extending the uncertain disturbance to the state variable $x_2=f\left(y,\dot{y},u\right)$, the state equations of voltage loop are:

$$\{\begin{array}{l}{\dot{x}}_1=x_2+b_{0}u\\ {\dot{x}}_2=h\\ y=x_1\end{array}$$

(18)

where x₁, x₂ is the state variables, and $h=\dot{f}\left(y,\dot{y},u\right)$.

A liner ESO can be established from Equation (18) as:

$$\{\begin{array}{l}{\dot{z}}_1=z_2+{\beta }_1\left(x_1-z_1\right)+b_{0}u\\ {\dot{z}}_2={\beta }_2\left(x_1-z_1\right)\end{array}$$

(19)

Suitable gains β₁ and β₂ make z₁ and z₂ in ESO achieve good tracking effect on x₁ and x₂. Ignore the estimation error of ESO, that is, $z_1\to x_1$ and $z_2\to x_2$. Meanwhile, if we let

$$u=\frac{-z_2+u_0}{b_0}$$

(20)

Equation (17) can be simplified as:

$$\dot{y}=\left(f\left(y,\dot{y},u\right)-z_2\right)+b_{0}u=u_0$$

(21)

The SEF of ADRC is designed as a proportional term:

$$u_0=K_p\left(v-z_1\right)$$

(22)

where $v=V_{dcref}^2$.

3.2. Parameters Simplification and Stability Proof

First, the key parameters of ESO and SEF in ADRC are designed. For the ESO as Equation (19), the characteristic polynomial is given by:

$$\lambda \left(s\right)=s^2+{\beta }_{1}s+{\beta }_2$$

(23)

Setting the pole of the characteristic equation as ESO bandwidth ${\omega }_0$, which results in:

$${\beta }_1=2{\omega }_0,{\beta }_2={\omega }_0^2$$

(24)

Let the proportional gain

$$K_p={\omega }_c$$

(25)

where ${\omega }_c$ is the system bandwidth.

Therefore, the parameters design of the ADRC is simplified as the design of system bandwidth and ESO bandwidth. In this paper, taking ω_c = 100. According to engineering experience, ω₀ is generally five to ten times ω_c, and is set as ω₀ = 800 here.

In order to prove the VSR based on ADRC stable, the convergence of ESO should be proven first. From Equations (19) and (24), the transfer functions of the variables z₁ and z₂ of ESO in the frequency domain are given by:

$$z_1=\frac{{\beta }_{1}s+{\beta }_2}{s^2+{\beta }_{1}s+{\beta }_2}y+\frac{b_{0}s}{s^2+{\beta }_{1}s+{\beta }_2}u=\frac{2{\omega }_{0}s+{\omega }_0^2}{s^2+2{\omega }_{0}s+{\omega }_0^2}y+\frac{b_{0}s}{s^2+2{\omega }_{0}s+{\omega }_0^2}u$$

(26)

$$z_2=\frac{{\beta }_{2}s}{s^2+{\beta }_{1}s+{\beta }_2}y-\frac{b_0{\beta }_2}{s^2+{\beta }_{1}s+{\beta }_2}u=\frac{{\omega }_0^{2}s}{s^2+2{\omega }_{0}s+{\omega }_0^2}y-\frac{b_0{\omega }_0^2}{s^2+2{\omega }_{0}s+{\omega }_0^2}u$$

(27)

Let the tracking error $e_1=z_1-y$ and $e_2=z_2-f\left(y,\dot{y},u\right)$, then

$$e_1=-\frac{s^2}{s^2+2{\omega }_{0}s+{\omega }_0^{2}s}y+\frac{b_{0}s}{s^2+2{\omega }_{0}s+{\omega }_0^{2}s}u$$

(28)

$$e_2=-\left(1-\frac{{\omega }_0^2}{s^2+2{\omega }_{0}s+{\omega }_0^2}\right)ys+\left(1-\frac{{\omega }_0^2}{s^2+2{\omega }_{0}s+{\omega }_0^2}\right)b_{0}u$$

(29)

Without loss of generality, y and u are all set as step signals of magnitude K, that is, y = K/s and u = K/s. Then the steady-state errors are:

$$\{\begin{array}{l}{e}_{1s}=\underset{s\to 0}{\lim }s{e}_1=0\\ e_{2s}=\underset{s\to 0}{\lim }s{e}_2=0\end{array}$$

(30)

This indicates that the ESO has good convergence and estimation. On this basis and from Equations (17)–(22), the voltage closed loop transfer function of VSR based on ADRC is given by:

$$G\left(s\right)=\frac{K_p}{s+K_p}$$

(31)

Obviously, if only K_p > 0, the three-phase VSR based on ADRC is stable.

3.3. Large Sigal Stability Analysis of Three-Phase VSR with CPL Based on ADRC

The power jump range is still analyzed by mixed potential theory in this section to discuss the stability of three-phase VSR with CPL based on ADRC. Assume $z_1=v_{dc}^2$ and b₀ = b, then

$$z_2=f\left(y,\dot{y},u\right)=-2P_{CPL}/C$$

(32)

The control function of voltage loop is given by:

$$i_{dref}=\frac{u_0-z_2}{b_0}=\frac{C{K}_p(V_{dcref}^2-v_{dc}^2)+2P_{CPL}}{2e_d}$$

(33)

The control loop equations of a three-phase VSR based on ADRC are constructed by Equations (10a), (10b) and (33). The current potential function and the voltage potential function are still Equations (11) and (12) respectively. In the same way as in Section 2.3, the stability is analyzed by the theorem in the Appendix A. According to the control loop Equations (10a), (10b) and (33), the second order partial derivatives of A(i) and B(v) are solved as:

$${\mathit{A}}_{\mathit{i}\mathit{i}\mathbf{\_}\mathit{A}\mathit{D}\mathit{R}\mathit{C}}\left(i\right)=\left[\begin{array}{cc}R+K_{ip}& 0\\ 0& R+K_{ip}\end{array}\right]$$

(34)

$${\mathit{B}}_{\mathit{v}\mathit{v}\mathbf{\_}\mathit{A}\mathit{D}\mathit{R}\mathit{C}}\left(v\right)=-\frac{K_p{K}_{ip}C{i}_d}{e_d}+\frac{v_d{i}_d-P_{CPL}}{v_{dc}^2}$$

(35)

According to the mixed potential stability theorem in the Appendix A, the sufficient condition for the stability of the three-phase VSR with CPL based on ADRC under large-signal perturbation is:

$$P_{CPL\_ADRC}<\frac{C(R+K_{ip})}{3L}{v}_{dc}^2-\frac{K_p{K}_{ip}C{v}_{dc}^2{i}_d}{e_d}+v_d{i}_d$$

(36)

Compared with the Equation (15), it can be seen that the power jump range under large-signal disturbance is different from that of PI control. Specifically, on the premise that the two methods have the same gain (i.e., K_p = K_vp), the difference between Equations (15) and (36) is determined by item M in Equation (15). The instability leads by large-signal disturbance mainly refers to the shock and divergence of the bus voltage when the CPL power increases. Therefore, under the premise of restoring stability, the minimum bus voltage must appear at the first oscillatory trough after the disturbance, as shown in Figure 7. In the process, the bus voltage reduces from V_dcref to the minimum value V_dcmin, energy in the capacitor is continuously extracted to meet the power requirement of the CPL, so e_di_d − P_{CPL_PI} < 0, or M < 0. It can be concluded that when there is a large-signal disturbance, the power jump range of VSR based on ADRC is larger than PI control. In other words, the stability is better.

4. Experiments

To verify the proposed control methods, a prototype of the three-phase VSR with CPL as shown in Figure 8 is built and tested. The system configuration is shown in Figure 1. Detailed parameters of the three-phase VSR are listed in

Table 1. Circuit Parameters of the Three-phase VSR.

Symbol	Quantity	Value
Eabc	Grid phase voltage	220 V
fg	Grid frequency	50 Hz
fs	PWM frequency	16 kHz
L	Input inductance	3.2 mH
Vdcref	Bus voltage	650 V
R	Equivalent resistance	0.2 Ω
C	Bus capacitance	100 μF
Kip	Proportional gain of the current PI regulator	5
Kii	Integral gain of the current PI regulator	100
Kvp	Proportional gain of the voltage PI regulator	0.2
Kvi	Integral gain of the voltage PI regulator	80

, and the control circuit is based on the digital signal processor (TMS320F28335). The CPL is a full bridge DC/DC converter, of which the input voltage is 650 V, the output voltage v_{CPL_o} is 300 V, and switching frequency is 20 kHz.

Figure 9a shows the main operating waveforms of the VSR with conventional PI control. At the beginning, the load power of VSR was 2 kW, and the system operated under light load. When the load power suddenly increased to 10 kW, the bus voltage v_dc and grid current i_a, i_b, and i_c begin to oscillate until the protection was triggered and the system shut down. This indicates that this large-signal disturbance (load power suddenly increases by five times) caused the system to lose stability, and that the conventional PI control failed.

Figure 9b shows the main operating waveforms of the VSR with proposed ADRC. The other experimental conditions are the same as PI control. When the load power suddenly increased from 2 kW to 10 kW, the bus voltage v_dc was quickly regulated back to the reference 650 V. In this case, the cascade system composed of VSR and CPL ran well, and the steady performance was good. The THD of grid currents was 3.5%, 3.9%, and 4% respectively. Compared with Figure 9a, the power jump range of the VSR with CPL had been effectively expanded and stability had been improved.

Figure 10 shows the main operating waveforms of the CPL when load power is changed from 2 kW to 10 kW. It can be seen that after the load power jumped, the closed-loop control of CPL makes the output voltage v_{CPL_o} quickly back to 300 V, and the oscillation is very small. The CPL output current i_{CPL_o} and output power P_CPL also quickly reached the target value, which satisfies the CPL characteristic. This shows that the results of Figure 9 is meaningful and sufficient.

5. Conclusions

In this paper, the problem that three-phase VSRs with CPL are unstable under large-signal disturbance is discussed first. Then, based on the mixed potential theory, the stability boundary of VSR with CPL when load power jumps (a typical large-signal disturbance) is analyzed. In order to improve the large-signal stability of the system, a voltage loop control scheme based on ADRC is proposed. It was shown that the scheme expands the power jump range of the VSR effectively, and improves the disturbance rejection performance, so that it is more suitable for applications with heavy load frequently switching. Finally, the validity of the control scheme is demonstrated by experiments.