Analysis of Fault-Tolerant Operation Capabilities of an Isolated Bidirectional Current-Source DC–DC Converter

Abstract

Reliable and predictable operation of power electronics is of increasing importance due to continuously growing penetration of such systems in industrial applications. This article focuses on the fault-tolerant operation of the bidirectional secondary-modulated current-source DC–DC converter. The study analyzes possible topology reconfigurations in case an open- or short-circuit condition occurs in one of the semiconductor devices. In addition, multi-mode operation based on topology-morphing is evaluated to extend the operating range of the case study topology. The influence of post-failure modes on the functionality and performance is analyzed with a 300 W converter prototype. It is demonstrated that failure of one transistor in the current-source side can be mitigated without dramatic loss in the efficiency at maximum power, while preserving bidirectional operation capability.

1. Introduction

Increased dependability on power electronic systems in various application areas has made their reliable operation over their designed lifetime an essential factor. Depending on the operation conditions, various stresses like temperature, humidity, and vibration affect the reliability of the power electronic system [1]. Normal operation depends on a high number of fragile components, while failure in one of those can lead to loss of functionality, increased downtime, and maintenance costs. This has enforced significant efforts in the research on the reliability-related issues from various perspectives, including development of robust and reliable components, measures to increase system redundancy, condition monitoring, intelligent control etc. [2,3]. Among the components with the strongest influence on the system reliability, the semiconductors and capacitors can be distinguished as most prone to failure. Significant efforts have been made to increase their reliability [4,5], along with other measures, such as planned replacement based on lifetime estimation during maintenance [6]. Additionally, the fault-tolerant operation of power electronic systems was addressed by increasing the redundancy using additional switches, switching states, parallel- or series-connected converters, etc. [7]. The use of redundant switches assumes appropriate converter topology reconfiguration in the case of certain types of failure and relies on precise fault diagnosis after one occurs. Despite the increased price of such systems, in certain application areas, like power supply, energy transmission, or aircraft, these extra costs can be accepted [1].

In some cases, the reconfiguration by “topology-morphing” can be used during the non-fault operation to extend the capabilities of the converter in terms of voltage regulation range and efficiency increase at certain operating points [8,9,10]. These studies were generally focused on voltage source and resonant converters with associated fault detection and diagnostic techniques.

Present work is devoted to the assessment of the fault-tolerant capability of the bidirectional full-bridge current-source DC–DC converter on the basis of the topology presented in [11]. The number of semiconductor devices allows us to take advantage of different reconfiguration possibilities and address various post-failure operation modes. Current-source converters are inherently fault tolerant to internal and external short circuits [12,13], making it easier to handle this condition. Generally, after a failure, the topology can be reconfigured into another one with a simplified structure. The possibilities of such reconfigurations are addressed in Section 2, along with possible fault detection methods and procedures. The multi-mode operation strategy is addressed in Section 3. Finally, our assumptions are verified with experiments in Section 4.

2. Analysis of Case Study Current Source Converter

2.1. Description of Topology

The isolated phase-shifted secondary modulated converter (PS-SMC) topology analyzed is presented in Figure 1 [10]. It features full-bridge at the current source (CS) side that utilizes bidirectional switches. At the secondary voltage source (VS) side, the hybrid structure is used. It can be reconfigured to either full- or half-bridge, using auxiliary switch S9 to compensate for the gain change in certain failure operating modes or to increase the converter regulation capabilities [10]. The bidirectional switch S9 can be realized by the semiconductor transistors or an electro-mechanical relay.

2.2. Analyzed Failure Modes

Despite significant improvements, semiconductor devices are still the power electronic converter components most susceptible to failure [1]. The reasons of failures and the failure type can vary, with strong dependence on the application area and operating conditions. In general, there are two types of failures of power semiconductor devices—open-circuit (OC) and short-circuit (SC). The OC condition can occur due to the gate drive failure, solder fatigue, or bond wire lift-off. On the other hand, SC failure can be the result of static or dynamic latch up, overvoltage, avalanche breakdown, etc. [12]. In some cases, the SC failure can lead to secondary effects that eventually result in an OC mode [14]. This work considers both OC and SC failure modes of one or several transistors in the topology and identifies possible reconfiguration possibilities.

A fault detection and diagnosis algorithm should be capable of locating the failed semiconductor and take action within a limited timeframe to avoid failure propagation to other components of the circuit. Thanks to inherent tolerance to SC conditions of the current-source topologies, the time available for the reconfiguration can be higher than that for voltage-source converters. On the other hand, the OC condition has to be addressed fast enough, as in this situation, the inductor creates overvoltage across the other healthy devices, which can fail due to the avalanche effect. Typical metal–oxide–semiconductor field-effect transistors (MOSFETs) are avalanche-rugged devices and can handle repetitive avalanche until their failure due to overheating, assuming the pulse energy is much lower than critical [14]. For the insulated-gate bipolar transistors (IGBTs), the avalanche ruggedness is smaller than the SC one due to high currents forming around the edge of the device and can vary significantly, depending on the device type and configuration [15,16,17].

2.3. Failure Detection Methods

Various OC and SC detection methods have been reported, which can be grouped into the following categories based on the operating principle:

• Desaturation detection;
• Shunt resistor;
• Current scaling (“mirror”);
• Gate charge (voltage);
• Inductive current rate of change (di/dt) sensing;
• Rogowski coil;
• Other/combined.

The desaturation method is a popular solution for IGBT [18]. This method is implemented in many driver integrated circuits and detects faults by monitoring collector-emitter voltage during the on-time of the transistor. After blanking time, this value is compared with a predetermined threshold to indicate SC or OC. This method can be effectively used for Si and SiC MOSFETs as well [19,20,21].

In the shunt resistor method, sort circuit protection is provided by monitoring the voltage across the metal film resistor connected in series with the transistor [22,23]. The voltage is then processed by a low-noise operational amplifier and compared to the reference value. A similar principle is applied in the current scaling method [24]. In this case, the current is monitored only through a part of the total die area, which allows for the reducing of the power losses in the shunt resistor. However, this method is mostly suitable at the integration into high-power transistor modules with several parallel transistor dies.

The gate charge method detects the difference in the gate-source voltage characteristics during the SC event [25]. It is associated with a lack of Miller plateau and the fast rise of gate-source voltage. The method is mostly applied to IGBTs, while its implementation with MOSFETs is associated with several challenges related to faster speed, ringing, smaller gate charge, and parameter variation between the devices [26].

The inductive sensing method is based on monitoring di/dt across stray inductance of the transistor module and can be used easily if gate-source and power source terminals are separated, providing a very fast response [27,28]. On the other hand, it cannot detect overcurrent at low di/dt, and its accuracy is highly influenced by the manufacturing tolerances.

The use of a Rogowski coil to detect fault conditions is addressed in [29]. The solution cannot detect the DC current and still remains quite complex for implementation due to parasitic oscillations and requirement of high-bandwidth amplifiers.

A combination of the methods can be used for better detection and protection characteristics. For example, the desaturation method together with di/dt sensing is analyzed in [30] to reduce blanking time. Likewise, the combination of gate voltage monitoring with di/dt achieves more robust SC and OC detection [31]. All of the mentioned methods or their combinations can be potentially applied for the detection of failure conditions in the case study current-source converter.

The reconfiguration approach assumes off-line detection of the faulty device during each start-up of the converter and selection of the appropriate control strategy to overcome the fault. The failure is detected according to the procedure in Figure 2.

2.4. Reconfiguration Possibilities and Post-Failure Modes

The converter in Figure 1 has high flexibility and offers several reconfiguration possibilities to other existing topologies from the group of snubberless current-source topologies:

• Asymmetric secondary-modulated converter (A-SMC) [32,33], as shown in Figure 3a;
• Flyback secondary-modulated converter (FBK-SMC) [34], as shown in Figure 3b;
• Symmetric secondary-modulated converter (S-SMC) [35], as shown in Figure 3c.

Theoretically, reconfiguration to other topologies, like parallel-resonant converters [32,36,37,38], is also possible. However, that requires significant changes in the control and strongly affects the regulation capabilities. Moreover, the failure conditions that would require such reconfiguration are very specific and unlikely to happen. Therefore, these options are omitted from the current study.

The failure mode assumes malfunction of at least one of the transistors or the gate driver. After timely failure detection, localization, and definition, the appropriate topology reconfiguration should be made. As mentioned previously, the failed device is represented as an open- or short-circuit. In certain cases, several reconfiguration possibilities are possible; therefore, the most suitable option has to be identified based on the performance or functionality preserved.

The possible failure scenarios and reconfiguration possibilities are summarized in

Table 1. Acceptable failures and reconfiguration possibilities ^A.

Transistor	PS-SMC	A-SMC	FBK-SMC				S-SMC
S1.1	+	+	1	+	0/-	+	+
S1.2	+	1	1	+	0/-	+	1
S2.1	+	+	+	1	+	0/-	+
S2.2	+	+	+	1	+	0/-	1
S3.1	+	+	0/-	+	1	+	+
S3.2	+	1	0/-	+	1	+	1
S4.1	+	+	+	0/-	+	1	+
S4.2	+	+	+	0/-	+	1	1
S5	+	+	+	+	+	+	+
S6	+	+	+	+	+	+	+
S7	-	-	+	+	+	+	-
S8	-	-	+	+	+	+	-
S9	-	-	+/1	+/1	+/1	+/1	-

^A “+”—fully operational, “1”—short-circuit (SC) failure or turned on, “0”—OC failure, “-”—not active or gate drive failure.

. The converter topology is assumed to be changed to one of those previously mentioned—A-SMC, FBK-SMC, or S-SMC in case a transistor fault is detected. It should be noticed that more than one failure can be tolerated for a particular reconfiguration option until the required fully operational devices are present. As it follows from Table 1, the CS side of the topology can tolerate a failure of any single transistor in either an open- or short-circuit state. Moreover, additional failure of certain gate drivers (“not active” condition) can be accepted as well.

Generally, the post-failure operation will impose certain restrictions on the converter operation due to increased power losses. At the SC failure of transistors S1.2 and/or S3.2, the converter should switch to the A-SMC mode, as shown in Figure 3a. In this mode, both S1.2 and S3.2 should be always turned on. Moreover, this mode can be used intentionally without any failures to increase the soft-switching range at low power levels; such a possibility will be discussed in the following section. Open- or short-circuit failure of any bidirectional switch can be overcome with reconfiguration to FBK-SMC. In this mode, either both top or bottom bidirectional switches operate at the switching frequency. One of the remaining bidirectional devices should be in the OC mode (or turned-off), while another in the SC mode (or turned-on) by the control system. The mode of the particular device is chosen according to its failure condition. An example of a converter with S1.1 and S1.2 in the SC condition and S3.1 and S3.2 in the OC condition is shown in Figure 3b. During the normal operation, the half-bridge is used at the VS side. In the case of reconfiguration to FBK-SMC, the voltage gain at the CS side is doubled. To compensate that, the switch S9 should be turned off and transistors S7 and S8 activated for the VS side to operate in the full-bridge mode. S-SMC mode, as shown in Figure 3c, should be used at the S2.2 and S4.2 SC failure. In this mode, the transistors S1.2, S2.2, S3.2, and S4.2 should be in the SC mode (or always turned on). Generally, this mode will have higher energy circulation and if possible, other reconfiguration options should be prioritized.

As observed from Table 1, the topology is sensitive to failures at the VS side. Neither open- nor short-circuit failures of bridge transistors can be tolerated. If the converter is intended to switch to the FBK-SMC mode, proper voltage rated devices have to be used at the CS side due to increased steady-state voltage stress in this mode. It should be noticed that the voltage rating of CS devices is dictated by the transient overvoltage peak present in the actively commutated inductive circuits [39] and depends on the converter parasitic parameters.

3. Multi-Mode Operation Strategy

As compared to most other current-source topologies without dedicated snubber circuits, the benefit of the studied PS-SMC converter lies in reduced energy circulation. The reason is that the converter current amplitude in the nominal operating mode never exceeds the CS-side current value and the transformer current is at zero during the shoot-through state. At the same time, this results in a limited capability of the converter to operate at low load conditions—the current in the circuit is not sufficient to recharge C_eq (representing equivalent parasitic capacitance of the circuit and external snubber capacitors, if applied). Moreover, this complicates the optimal selection of the duty cycle for VS-side transistors, as the time required for voltage polarity change can vary significantly, depending on the operating point. As a result, the zero-voltage switching (ZVS) capability of the converter is limited.

Although modulation with adaptive duty cycle can be implemented to reduce the body diode conduction time, it may not provide desired operation during fast changes in load or voltage. The A-SMC features the possibility to provide a soft-switching condition and wide range regulation even at no-load conditions. At the same time, its energy circulation is higher than in the PS-SMC. This section addresses the implementation possibility of multi-mode operation to enhance the regulation capability of the converter at light loads, while preserving the benefits of low energy circulation at high currents.

3.1. Converter Design Specifications

In the isolated boost-type topologies, the transformer primary voltage is always higher than the input one, which provides additional voltage step-up. At the same time, it is advantageous to limit the minimum voltage gain at the design stage for:

• Wider regulation capability;
• Reduced energy circulation;
• Increased transformer utilization;
• Reduced voltage stress on CS semiconductors.

All of these properties allow better utilization of converter components that will result in higher efficiency and increase of the overall practical feasibility. For the current case study, the application specification is defined according to the parameters listed in

Table 2. Main converter parameters and components. CS: current source; VS: voltage source.

Parameter/Component	Symbol	Value
CS voltage	UCS	16–32 VDC
VS voltage	UVS	380–420 VDC
Power	Prated	300 W
Operating frequency	fsw	50 kHz
Transformer turns ratio	n	5.5
CS side Inductor	L1	100 μH
Equivalent switch capacitance	Cs	500 pF
Equivalent inductance	Leq	400 nH
CS MOSFETs	S1.x–S4.x	BSC035N10NS5
VS MOSFETs	S5–S6	IXFP22N65X2

.

The operation of CS converters generally implies voltage overshoot associated with the diode reverse recovery process. In order to be able to safely use low voltage Si MOSFETs without snubbers at the CS side, its voltage has to be stabilized at the relatively low level. Therefore, the minimal normalized gain of <10% at the CS stage was chosen for the current study. To satisfy such criteria, the transformer with low leakage inductance is required, while the C_eq value should be selected carefully to obtain remarkable turn-off loss reduction of the VS devices with relatively low duty cycle loss.

3.2. Determination of Mode Boundary

As was mentioned above, the resulting gain of the PS-SMC converter is determined by the active state loss due to equivalent inductance and capacitance present in the circuit. It is assumed that L_eq is mainly represented by the transformer leakage inductance and C_eq is the equivalent capacitance referred to the CS side. In the calculations, the components are assumed lossless, the transformer magnetizing inductance is assumed to be infinitely large, and the CS-side current ripple is neglected. The equivalent capacitance is estimated as

$$C_{eq}^{}=2\cdot n^2\cdot C_s.$$

(1)

The converter normalized gain in a general form is defined as

$$G_{CS}^{}=\frac{U_{VS}}{2\cdot n\cdot U_{CS}}.$$

(2)

The converter gain at the CS side is calculated as follows [10]:

$$G_{CS}^{PS-SMC}=\frac{I_{CS}\cdot U_{VS}\cdot n}{I_{CS}\cdot U_{VS}\cdot n-8\cdot I_{CS}\cdot I_{CS}^{\max }\cdot L_{eq}\cdot f_{sw}\cdot n^2-4\cdot C_{eq}\cdot f_{sw}\cdot U_{VS}{}^2},$$

(3)

where I_CS is the CS side current and $I_{CS}^{\max }$ is the maximum CS side current (estimated for minimum input voltage and full load).

On the other hand, the A-SMC converter [17] features improved regulation capability, since C_eq is always discharged with maximal current $I_{CS}^{\max }$. The converter gain is calculated as

$$G_{CS}^{A-SMC}=\frac{1}{1-2\cdot f_{sw}\cdot \left(\frac{4\cdot n\cdot I_{CS}^{\max }}{U_{VS}}+t_{res}^{}\right)},$$

(4)

where t_res is the duration of the resonant interval [17].

Given the parameters from Table 2, the minimum G_CS value is calculated as

$$G_{CS}^{\min }=\frac{U_{VS}^{\min }}{2\cdot n\cdot U_{CS}^{\max }}=1.08.$$

(5)

Using Equations (3) and (4), the minimal values were derived for PS-SMC and A-SMC. The intersection of these values with the normalized gain according to Equation (2) provides the borderline between the PS-SMC and A-SMC modes, as shown in Figure 4. In the latter mode, the transistors S1.2 and S3.2 are turned on to allow more current to accumulate in the circuit for the discharge of C_eq, enabling an extended output voltage regulation range. It should be noticed that the borderlines show theoretical values that can be achieved with ideal converter parameter values for particular operating points. In the practical systems, a trade-off is necessary in order to simplify control and optimize the performance, along with a certain design safety margin. This will affect the borderline and will be discussed in more detail in the following section.

4. Results

4.1. Post-Failure Operation and Performance

To validate the analysis from the previous section, a converter prototype according to the topology from Figure 1 and specifications listed in Table 2 was tested. The OC or SC conditions for semiconductors were emulated by the microcontroller by keeping the corresponding gating signal of the transistor “off” and “on”, respectively. The system operated in the open-loop and fault diagnostics was not applied. The focus was on the converter performance and capabilities when operating under various post-failure conditions.

The normal operation of PS-SMC in boost and buck modes is presented in Figure 5a,b, respectively. At the post-failure reconfiguration to the A-SMC topology, as shown in Table 1, the transistors S1 and S3 and the transformer are operating with increased peak current, as shown in Figure 6 are preserved. As was mentioned, this topology allows even a wider regulation range than the reference PS-SMC; the experimental results and analysis addressing this feature are presented in the following section.

The operating waveforms after the reconfiguration of the S-SMC topology are shown in Figure 7. Similar to the previously described failure mode (A-SMC), the peak current in the circuit is increased, while the gain on the reference topology is preserved. As was observed, there is no zero-current interval at the transformer, and thus the amount of circulating current is generally higher than in other configurations. Therefore, other post-failure reconfigurations should be prioritized whenever possible.

As it follows from T, the reconfiguration to FBK-SMC can be used in the case of many various failure modes, particularly if there is an OC switch condition at the CS side. As compared to the reference case, the gain of the topology is double, and the VS-side is reconfigured to the full-bridge to compensate that. The experimental waveforms are presented in Figure 8.

4.2. Multi-Mode Control

To estimate the performance in the post-failure modes, the total efficiency of different configurations above was measured using a Yokogawa WT3000 power analyzer at the room temperature of 25 °C, as shown in Figure 9. It follows that the converter can tolerate most fault conditions without significant reduction of the efficiency. In certain cases, when the S-SMC mode is used at low CS-side voltages, certain power derating may be necessary to keep the operating temperature within required limits. Alternatively, in the FBK-SMC mode, the reduction in the efficiency at light loads is expected due to the loss of ZVS.

In order to implement the multi-mode control strategy, the operating limits of the PS-SMC converter prototype have to be determined taking into account the parameters defined. It was assumed that the converter is controlled with phase-shift control, while the other operating parameters are set to be constant, as listed in Table 2. The estimated and experimentally obtained operating limits of the prototype are depicted in Figure 10. The experimentally obtained values are close to the theoretical ones, while the observed deviation can be explained by a slight mismatch in the component values and power losses in the circuit. It follows that the regulation capability of the converter may be limited due to two different factors—at high CS voltage, the converter cannot deliver the required output voltage due to limited minimal gain (active state loss), while at low loads, it loses the ZVS of VS-side devices due to the increased recharge time of capacitors. For the current study, the parameters were chosen to demonstrate the flexibility of the converter design in general, while the optimal values can be selected according to a particular application and its operating profile.

The waveforms demonstrating the loss of ZVS at 80 W are presented in Figure 11a. The multi-mode operation allows the topology to change to A-SMC and overcome the regulation limitations. An example is illustrated in Figure 11b, where it is shown that the capacitor discharge time (t_d) was significantly reduced in the A-SMC topology due to increased peak current. On the other hand, this results in the increased energy circulation in the topology, therefore baseline PS-SMC mode should be prioritized if the current in the circuit is sufficient for ZVS.

5. Conclusions

This work addresses fault-tolerant operating capabilities of the bidirectional full-bridge current-source converter with secondary-modulation. According to the presented analysis, the converter can tolerate both open- and short-circuit conditions at the low-voltage CS side, assuming a hybrid full/half-bridge circuit used at the high-voltage side. This is achieved by the reconfiguration of the baseline PS-SMC into other known topology types (S-SMC, A-SMC, S-SMC), depending on the failed device location and failure mode. The expected reduction of the efficiency in the post-fault cases is within 2% at maximum power. Although higher reduction in efficiency is expected at lower power levels due to increased energy circulation or loss of ZVS, the bidirectional capability is preserved, and the general functionality provided. At the same time, it was revealed that failures at the high voltage VS-side cannot be tolerated using the reconfiguration principles of the analyzed topology.

Moreover, it was predicted and experimentally confirmed that the A-SMC mode can be applied as a multi-mode strategy to extend the ZVS range of the baseline converter. This allows the converter to easily handle no-load conditions even with relatively large external snubber capacitors.