DC-DC High-Voltage-Gain Converters with Low Count of Switches and Common Ground

Abstract

This paper presents a new concept and research results of DC-DC high-voltage-gain, high-frequency step-up resonant converters. The proposed topologies are optimized towards minimizing the number of switches and improvements in efficiency. Another relevant advantage of such type of converters is that they have a common input and output negative point. The proposed converters are based on the resonant switched-capacitor voltage multiplier circuit, and that is why they are compared with a classic converter from this family. The included results show the operating principle, possible switching methods with the consideration of their impact on the voltage gain level, as well as the voltage and current ripples. The operating concepts and analytical calculations are confirmed by simulation and experimental results.

1. Introduction

Switched capacitor (SC) circuits can be effectively used in power electronic converters [1]. The significant advantages of SC-based DC-DC power converters are high-voltage-gain, low volume, and quasi inductiveless design. To achieve oscillating currents, low-volume inductors can be used in those converters. They can be designed as air-chokes, or even be based on parasitic inductances of the circuits, resulting in a decrease in the weight of the converter. The design without ferrite chokes allows for the use of the converter in high ambient temperature and/or with a low-volume heat sink.

SC DC-DC converters represent one of the classes of non-isolated step-up converters [2,3,4]. Nowadays, there are a significant number of applications where isolated DC-DC step-up converters are required [3], due to technical reasons and safety requirements. However, various kinds of non-isolated converters are extensively developed as well. One of the prospective applications for non-isolated DC-DC step-up converters proposed in the literature [5,6,7,8,9,10] are photovoltaic (PV) systems. High step-up DC-DC converters are often required in grid-connected PV systems to transfer the energy from a low-voltage PV source to the grid [5,6]. In transformerless PV systems [7,8], as well as in microinverters [9], dual-stage DC-AC converters are one of the investigated solutions.

The SC step-up DC-DC converter could be a competitive solution to the switch-mode boost converter. An example of such an idea is presented in Reference [10]. The non-isolated step-up converter can be used not only for a single stage supply, but as a part of a system composed of series-connected converters as well. In such systems, isolation can be implemented in another stage of conversion, e.g., by using a series resonant converter [6,11].

High-voltage-gain in SC-based DC-DC converters can be achieved by applying a suitable topology concept. In References [12,13,14], an SC voltage multiplier (SCVM) has been presented. It is a series-parallel converter in that a high-voltage-gain can be obtained, as it is proportional to the number of switching cells. The advantage of an SCVM is its modular topology; however, the number of required transistors is relatively high. Series-parallel SC converters have also been presented in recent publications [15,16]. In Reference [15], a converter with regulated voltage gain has been discussed. This device utilizes three switches, which means that the voltage gain can reach three. Reference [16] has presented a very effective method that allows the switch count in high-gain series-parallel converters to be decreased. However, the converter presented in Reference [16] does not have a common input and output negative point, and the output voltage is asymmetrically divided. In Reference [17], a converter that combines Dickson-based and ladder SC converter concepts has been presented. In the proposed topology, high-voltage-gain is achieved with limited voltage and current stresses on the switches. The Dickson-based SC concept has also been used in the converter presented in Reference [18] that is composed of an SC part and an interleaved boost converter. The converter achieves a very high-voltage-gain with the output voltage regulation and soft switching operation, using four switches and seven diodes. In Reference [19], high-voltage-gain is achieved in a converter with switched-capacitor and switched-inductor networks. A concept of a family of converters composed of a boost stage and switched-capacitor-inductor cells has been presented in Reference [20]. This increases the voltage gain of the converter significantly with favorable voltage stress levels, efficiency, and component count. References [21,22,23,24] have demonstrated high-voltage-gain multilevel converters based on typical multilevel converter concepts. When we take into consideration the number of the utilized components and the reached voltage gain, the multilevel SC converters can be more beneficial in comparison to the SCVMs. The converter described in Reference [21] is based on a modified classic multilevel SC topology; however, it is composed of a significant number of switches. In Reference [22], an improvement in the operation of the multilevel resonant SC converter (MRSCC) has been proposed. The MRSCC makes it possible to operate with high-voltage-gain and limited voltage stress on the switches with the ability of bi-directional energy transfer. In Reference [23], a multilevel structure has been achieved in the converter with two switches and circuits composed of diodes and capacitors. The converter can operate with zero voltage switching (ZVS) and voltage regulation. In Reference [24], a DC-DC bidirectional SC converter has been presented that improves the total device power ratings in comparison to the multilevel modular capacitor clamped converter (MMCCC) and well-established flying-capacitor converters.

One of the major issues of the SC converters is a large number of switches used in the topology. This problem can be solved by the concepts of cascaded or series systems composed of SC units [25,26] or by new concepts of topologies [16,27,28]. In the concept for the switch count reduction presented in Reference [26], a high-power converter has been analyzed in a multi-section topology. The converter is composed of the typical SCVM sections separated by LC filters. According to this concept, a significant reduction in the number of switches has been achieved. However, an increased number of passive components are utilized as LC filters between the sections in the multi-section converters [26]. The problem of the switch count reduction in an SCVM converter has been analyzed in Reference [29], where the charging of the switched capacitors is controlled by a single switch. For high-voltage-gain, the system is significantly simplified. The design of such a cost-effective converter should assume a much higher current stress of the switch that controls the charging of the switched capacitors.

The converters proposed in this paper are optimized towards a low count of transistors (and they are called Low Count of Transistors Switched Capacitor Voltage Multipliers—LCSCVMs). The basic concept of the topology and operation assumes that every second cell has no transistors whatsoever, but the utilization of all the switched capacitors remains possible, and the effect of voltage gain is comparable to that of the multipliers (SCVMs) presented in Reference [13,14]. Furthermore, the optimized concept is introduced into the cost-effective topology presented in Reference [29], which gives a new relevant converter. Taking into consideration the count of switches, SC converters, such as the SCVM [20], may not be in competition with the LLC converters or other established topologies. However, the concepts proposed in this paper demonstrate a development of the SC topologies towards a significant decrease in the number of switches. One of the converters presented in this paper requires only three switches, which is below the number of transistors used in a full-bridge LLC converter. Other advantages of the SC converters, such as: high gain, high power density and low weight (no transformer or bulky choke), fast dynamic response [3], ability for operation in high temperature (no ferrites), and simple control, can make them an alternative solution for existing topologies intended for high-voltage-gain non-isolated DC-DC conversion. SC-based topologies can be suitable for the miniaturization of converters that can be applied in emerging power electronics applications, such as wearable technology.

For the operational parameters of an SC converter, the switching strategy applied for a given topology can be essential, which has been demonstrated in Reference [14]. For the optimization purposes analyzed in this paper, various switching strategies are proposed for the new topologies. This makes it possible to determine the advantages of the presented topologies, also taking into consideration a variety of qualities, other than the count of switches.

The proposed converters are nearly pure switched-capacitor circuits, where a vast majority of energy is transferred via capacitors rather than inductors. The resonant inductors are used to achieve oscillatory currents. The inductors can be designed as air chokes, which reduces the weight of the converters and allows them to work in higher temperatures. However, another trend in the development of very high-voltage-gain converters can be observed in the literature. The concept presented in Reference [30] is based on coupled inductor (CI) converters that achieve good parameters such as voltage ratio, efficiency, low number of switches, or low voltage stress on switches. Notwithstanding, such converters use chokes and, therefore, differ from the presented SC-based concept regarding admissible ambient temperature of operation, weight, and volume. The design comparison can be analyzed in particular case studies.

In this paper, the qualities introduced by the new topologies will be compared with those of a classic SCVM and of other converters discussed in recently published papers.

The paper is organized as follows. Section 2 demonstrates two proposed topologies of the SC converters and presents the principles of their operation. For both converters, switching strategies are analyzed. The discussion is supported by the results of computer simulations of their operation in five cases of switching strategies. Moreover, with the use of the simulation results, a number of parameters of the converters operating under various switching strategies are compared as well. Section 3 contains efficiency models of the proposed converters that demonstrate their efficiency as a function of their parameters. Section 4 presents the laboratory setup and the experimental verification of its operation, including the efficiency of the converter. All the research results are concluded in Section 5.

2. Operating Principle of the Converters

The operating principle of the converters in Figure 1 is similar to that of other SC multipliers, and is based on the charging and discharging of the switched capacitors in consecutive stages (time intervals). However, various switching strategies can be proposed for the new converters, which creates differences in their parameters. In the SCVM, as well as in the case of the converters proposed in this paper, the switched capacitors are recharging in resonant circuits composed of a switched capacitor and a low-volume resonant inductor. This creates ZCS (zero current switching) operating conditions, and limits the current flow between the capacitors and the voltage source connected in parallel.

The main difference between the topology of the proposed converters and the classic SCVMs is that in the former case, an LC circuit that is not a part of a traditional cell is used, usually consisting of a diode and two transistors [13]. This circuit is charged using the energy of the input source and the electric charge of the switched capacitor that is the nearest to the input source. Then, the middle capacitor is discharged to the output capacitor or to the switched capacitor nearer to the output. Its function is to increase the output voltage and the amount of converted power, simultaneously maintaining the same value of the input voltage and the same cell number as in the case of a typical SCVM.

The LCSCVMa (Figure 1a) offers a larger number of strategies than the LCSCVMb (Figure 1b), due to the possibility of independent control of switches S₁ and S₃. The basic switching strategies can be composed of 2, 3, or 5 stages.

2.1. Switching Strategy Concepts for the LCSCVMa

Table 1. Switching strategy concepts of the LCSCVMa. States of switches S₁–S₄.

The Concept for Switching Strategy of LCSCVMa		Description—Stages of Charge Transfer in the Converter
Strategy C1		1.Simultaneous charging of all the switched capacitors 2. Discharging of the capacitor that is the nearest to the source (C1) to the internal branch (C2) 3. Charging C1, and discharging C2 and the next SC capacitor (C3) to the output 4. Discharging C1 to the internal branch (as in 2) 5. Discharging C2 and C3 to the output
Strategy C2		1. Simultaneous charging of all the switched capacitors 2. Discharging C1 to the internal branch (C2) 3. Discharging C2 and C3 to the output
Strategy C3		1. Simultaneous charging of all the switched capacitors (C1 and C3) 2. Simultaneous discharging of all the switched capacitors and charging the internal branch capacitor (C2)

presents three switching strategies for the LCSCVMa, and Figure 2, Figure 3, Figure 4 and Figure 5 depict the corresponding simulation waveforms.

To characterize the switching strategies, Table 1 contains the idealized control logic waveforms of the transistors (signals S₁ to S₄), as well as the description of the particular operation stages. Dead times have been neglected in Table 1, but they have been taken into account in the simulations and experiments. Capacitor C₂ (Figure 1) is not referred to as a switched capacitor. The maximum switching frequency (strategy C3) is defined as:

$$f_{{\mathrm{S}}_{\max }}=\frac{1}{2T_{pulse}}$$

(1)

where T_pulse is the sum of the duration time T₀/2 of a single current pulse of any transistor and the dead time t_d (any period of time denoted as 1–5 in Table 1),

$$T_0=\frac{1}{f_0}=2\pi \sqrt{LC}$$

(2)

and L = L₁ = L₂ = L₃, C = C₁ = C₂ = C₃ (Figure 1).

All the simulation results were obtained for the following parameters: U_in = 50 V, L_n = 620 nH, C_n = 1.47 μF, f₀ = 166.7 kHz, T_pulse = 4.2 μs (f_Smax = 119 kHz), C_out = 100 μF, P_out = 200 W (n = 1, 2, 3). A resistance of 100 mΩ has been inserted into each branch as an equivalent to parasitic resistances. The time period T_pulse, as well as the duty cycle of the switching signals of the transistors, remain constant in each switching strategy. The selection of the switching frequency depends on the power of the converter, achievable resonant inductance, and switching losses [13]. This parameter, as well as the others, can be fixed in the following steps. In the ZCS mode, the SC converters’ transistors do not operate in the ZVS mode, and during their turn-ons, the output charge is shorted (C_oss losses). The limit of C_oss losses determines the switching frequency of the transistors taking into consideration their type and voltage stresses. The oscillation frequency should be nearly equal to the switching frequency to minimize conduction losses [13]. This frequency depends on the product of L_nC_n, and allows to select C_n for a known value of L_n. The maximum power of the converter depends on capacitance C_n and the switching frequency [13], and it should be higher than or equal to the rated power for the selected parameters. The simulation results presented in this section have been obtained with the use of ICAP/4 simulation package based on the IsSpice4 simulator.

2.1.1. Simulation Results of the Switching Strategy C1

Figure 2 presents steady-state simulation waveforms of the LCSCVMa controlled according to strategy C1. From all the results, it can be seen that the switched capacitors are recharged by oscillatory currents and each stage of the switching is longer than the half-period of the oscillations.

The entire switching cycle is composed of five stages (Table 1). According to the principle of operation, turning on switches S₁ and S₃ involves the charging of the switched capacitors C₁ and C₃. Capacitor C₃ is being charged from capacitor C₂ of the internal branch whose voltage is going down in this stage. The diode D₂ remains turned off, as u_C2 > u_C1 and u_C2 > u_in (Figure 2). In the next stage, switch S₂ is turned on, and capacitor C₂ is being charged from the source u_in and capacitor C₁ connected in series with it. The charging of the output capacitor, from capacitors C₂ and C₃ connected in series, occurs in the next stage when the switch S₄ is turned on. At the same time, capacitor C₁ is being charged from the source. In the next two stages, capacitor C₂ and capacitor C_out are being charged, consecutively.

The advantage of this switching strategy is reducing the number of the performed switching operations, which leads to switching losses limitation. In three of five stages of the switching period, only one switch is affected.

The input current has various values in each switching state, which is a drawback of this strategy. Therefore, a low-frequency component f_S = f_ac-in = f_Smax/2.5 appears in current i_in, as well as in all other currents and voltages in the circuit. Using this kind of switching requires using a large input filter and a large output capacitor. From the standpoint of the components’ volume and input current filtering, this strategy is not favorable.

The output voltage used for the voltage gain calculation in relation (3) has been measured as the average value of the waveform presented in Figure 3 together with the output current. Further results, given in Equations (4)–(7), were obtained in the same manner.

In this strategy, the measured average value of the output voltage of the converter equals U_out = 178 V. For the input voltage of the converter U_in = 50 V (maintained by the voltage source in simulations), the voltage gain of the converter under switching strategy C1 equals:

$$G_{UC1}=\frac{U_{\mathrm{out}}}{U_{\mathrm{in}}}=\frac{178.0}{50.0}=3.56$$

(3)

2.1.2. Simulation Results of the Switching Strategy C2

Figure 4 presents simulation waveforms in the LCSCVMa controlled according to strategy C2. In this strategy, each switching period consists of three stages. The first two switching stages correspond to those in strategy C1. In the third stage, only transistor S₃ is on. The last two stages of strategy C1 do not occur here, and capacitor C₂ is charged and discharged only once in a switching period. The number of the switching operations is lower in comparison to that in strategy C1. The spectrum of currents and voltages shows more favorable qualities in strategy C2 versus C1, as the 50 kHz components are not present (the lowest frequency is 75 kHz).

In this strategy, the measured average value of the output voltage of the converter equals U_out = 177 V. For U_in = 50 V, the voltage ratio is

$$G_{UC2}=\frac{U_{\mathrm{out}}}{U_{\mathrm{in}}}=\frac{177.0}{50.0}=3.54$$

(4)

2.1.3. Simulation Results of the Switching Strategy C3

Figure 5 presents simulation waveforms in the LCSCVMa controlled according to strategy C3. In this strategy, there are only two stages. In the first stage, the charging of the switched capacitors takes place (switches S₁ and S₃ are turned on). During the second stage, the output capacitor and C₂ are being charged (with switches S₂ and S₄ turned on).

In this strategy, each switch operates with a much higher frequency than in the case of strategies C1 and C2. This brings an improvement in the spectrum of the currents and voltages, as the lowest frequency is 120 kHz. It is favorable from the passive components volume optimization standpoint.

In strategy C3, the measured average value of the output voltage of the converter equals U_out = 185 V, and for U_in = 50 V, the voltage ratio is

$$G_{UC3}=\frac{U_{\mathrm{out}}}{U_{\mathrm{in}}}=\frac{185.0}{50.0}=3.7$$

(5)

2.2. Switching Strategy Concepts for the LCSCVMb

The LCSCVMb converter is simpler than the LCSCVMa, and contains three switches only. There is only one stage of charging the switched capacitors, realized by the switch S₁, and two possible stages of discharging them, controlled by switches S₂ and S₃. This creates two switching strategies for this converter, which are presented in

Table 2. Switching strategy concepts of the LCSCVMb. States of switches S₁, S₂, and S₄.

The Concept for Switching Strategy of LCSCVMb		Description—Stages of Charge Transfer in the Converter
Strategy C4		Similarly to strategy C2 for the LCSCVMa, strategy C4 gives the following characteristic in the LCSCVMb: 1. Simultaneous charging of all the switched capacitors 2. Discharging C1 to the internal branch (C2) 3. Discharging C2 and C3 to the output
Strategy C5		Similarly to strategy C3 for the LCSCVMa, strategy C5 gives the following characteristic in the LCSCVMb: 1. Simultaneous charging of all the switched capacitors 2. Simultaneous discharging of all the switched capacitors and charging the internal branch (C2)

. Figure 6 and Figure 7 depict simulation waveforms of the LCSCVMb controlled according to these strategies.

2.2.1. Simulation Results of the Switching Strategy C4

Figure 6 presents simulation waveforms of the LCSCVMb controlled according to strategy C4. The current and voltage waveforms in strategy C4 are nearly identical with those in strategy C2.

In this strategy, the measured average value of the output voltage of the converter equals U_out = 172.1 V, which yields (for U_in = 50 V):

$$G_{UC4}=\frac{U_{\mathrm{out}}}{U_{\mathrm{in}}}=\frac{172.1}{50.0}=3.44$$

(6)

2.2.2. Simulation Results of the Switching Strategy C5

Figure 7 presents simulation waveforms for the LCSCVMb controlled according to strategy C5. The current and voltage waveforms of the strategy C5 are nearly identical with those in strategy C3.

In this strategy, the measured average value of the output voltage of the converter equals U_out = 181.4 V. For U_in = 50 V, the voltage ratio is:

$$G_{UC5}=\frac{U_{\mathrm{out}}}{U_{\mathrm{in}}}=\frac{181.4}{50.0}=3.63$$

(7)

2.3. Comparison among the Topologies and Switching Strategies

In Section 2.1 and Section 2.2, a significant number of waveforms are presented for the particular strategies. The differences in the waveforms of the currents and voltages are clear, but to compare the concepts of the converters and the switching strategies, the following parameters will be taken into consideration and presented in charts:

• Number of components,
• Voltage gain,
• The lowest frequency in the input current (f_{ac_in}),
• The lowest frequency in the output current (f_{ac_out}),
• Voltage pulsation on capacitors (U_C1p-p, U_C2p-p, U_C3p-p),
• rms values of inductor currents (I_{L1_rms}, I_{L2_rms}, I_{L3_rms}),
• Maximum values of inductor currents (I_{L1_max}, I_{L2_ max}, I_{L3_ max}),
• Symmetry of inductor currents (Sym_i_L).

The data are presented in

Table 3. Major parameters comparison among the parameters of LCSCVMa and LCSCVMb converters in the tests of 200 W operation.

Parameter	LCSCVMa Strategy			LCSCVMb Strategy		SCVM
	C1	C2	C3	C4	C5
No. of switches	4	4	4	3	3	6
No. of diodes	4	4	4	5	5	4
Uout, V	178.0	177.0	185.0	172.1	181.4	191.2
TS, μs	21.0	12.6	8.4	12.6	8.4	8.4
fac_in, kHz	47.6	79.4	238.1	79.4	238.1	238.1
fac_out, kHz	47.6	79.4	119.0	79.4	119.0	119.0
UC1p-p, V	21.02	19.41	12.4	19.8	12.6	5.98
UC2p-p, V	21.61	19.41	6.54	19.8	6.65	5.98
UC3p-p, V	16.08	9.7	6.18	9.92	6.29	5.98
IL1_rms, A	6.75	7.25	5.65	7.41	5.75	2.73
IL2_rms, A	6.22	6.28	2.92	6.42	2.97	2.73
IL3_rms, A	4.11	3.63	2.75	3.71	2.80	2.73
IL1_max, A	16.1	14.8	9.46	15.1	9.60	4.57
IL2_ max, A	13.2	14.8	5.01	15.2	5.09	4.57
IL3_ max, A	12.3	7.43	4.74	7.56	4.80	4.57
Symmetry of current iL1	no	yes	yes	yes	yes	yes
Symmetry of current iL2	no	no	yes	no	yes	yes
Symmetry of current iL3	no	yes	yes	yes	yes	yes

, where the parameters of the SCVM (on the basis of Reference [14] for an appropriate strategy) are included as well.

Figure 8, Figure 9 and Figure 10 present a comparison between the values of parameters of the discussed converters, and the corresponding parameter of the SCVM.

In Figure 8, the coefficients 0.06 and 0.4 are used respectively, to better visualize the undesired output voltage decrease in regard to the theoretical value of 200 V, and the lowest frequencies in the input and output current of the discussed converters compared to those in the SCVM. In each case, a lower value on the graph is better.

From the chart presented in Figure 9a, it follows that the lowest peak-to-peak (p-p) voltages, in all the strategies, are equal the voltage across capacitor C₃. Moreover, the strategies C3 and C5 show the lowest p-p voltages for all the internal capacitors (C₁–C₃). Figure 9b demonstrates that the currents of inductor L₃ are the lowest, and the strategies with the lowest inductor currents are C3 and C5.

The same qualities are visible in charts presented in Figure 10, which clearly demonstrate that the parameters of strategy C4 are nearly the same as those of strategy C2. The same refers to strategies C5 and C3.

The LCSCVMa and LCSCVMb converters can be further extended to units of higher voltage gain, similarly as in the case of the converters presented in References [13,22,25,26,29]. Taking into consideration the number of switches and diodes, as well as the frequency of the input current, both the proposed converters are very attractive for high-voltage-gain (

Table 4. Comparison of the number of switches and diodes, and the lowest frequency of the input current in selected topologies versus the voltage gain. Ref. = Reference.

Parameter		Toplogy
	Gain	LCSCVMa	LCSCVMb	Ref. [13]	Ref. [22]	Ref. [16]	Ref. [25]	Ref. [26]	Ref. [27]
No. of switches(and diodes)	4	4 (4)	3 (5)	6 (4)	8 (0)	-	8 (0)	4 (4)	4 (6)
	7	-	-	12 (7)	14 (0)	7 (5)	-	-	7 (12)
	8	6 (6)	4 (7)	14 (8)	16 (0)	-	12 (0)	6 (6)	8 (14)
fiin_min/fSmax for all gains(fSmax—in (1))		1	1	0.5	1	1/4	1	1	0.5

). It should be noticed that the converter extension is very effective in the case of the LCSCVMb concept. For voltage gain G_U = 8, it requires only four switches, which is an excellent result in comparison to other pure SC converters. Other parameters such as voltage stresses on the switches can be found in the literature.

3. Efficiency Model of the LCSCVM Converters

The analysis below concerns the LCSCVMa operating under the strategy C3 (Table 1) and LCSCVMb operating under the strategy C5 (Table 2). In both cases, there are two stages of operation. Figure 11 depicts the current paths in the LCSCVMa. In the LCSCVMb, the switch S₁ conducts the sum of currents i_L1 and i_L3 in the stage 1, whereas the current paths in the stage 2 are the same as in the LCSCVMa.

Assuming ideal power electronic switches, and a constant value of the input (U_in) and the output (U_out) voltage, as well as neglecting parasitic resistances and voltage drops across the power electronic devices, the currents in the stage 1 (Figure 11a) can be described as follows:

$$i_{L1}\left(t\right) = i_{C1}\left(t\right) = \frac{U_{\mathrm{in}}- U_{C11}}{\rho } \sin {\omega }_{0}t = I_{1\mathrm{m}} \sin {\omega }_{0}t$$

(8)

$$i_{L3}\left(t\right) = i_{C3}\left(t\right) = \frac{U_{\mathrm{in}}- U_{C11}}{2\rho } \sin {\omega }_{0}t= \frac{I_{1\mathrm{m}}}{2} \sin {\omega }_{0}t$$

(9)

$$i_{L2}\left(t\right) = i_{C2}\left(t\right) = -i_{L3}\left(t\right)$$

(10)

With the characteristic impedance and the angular resonant frequency given by

$$\rho = \sqrt{L/C}, {\omega }_0 = 1/\sqrt{LC}$$

(11)

where U_C11 is the initial voltage across capacitor C₁, and I_1m and I_2m/2 are the current amplitudes. Equation (8) presents the current of a typical series LC circuit supplied from a voltage source, and Equation (9) was obtained also taking into account the initial values of the capacitor voltages.

The values of the passive components depend on the assumed nominal power (P_nom), switching frequency (f_S), and the volume of the resonant inductor. The values of time T_pulse (1), and finally T₀ (2) and ω₀ (11), are assumed taking into account the limit of the switching losses in the converter. The capacitance of the switched capacitors is determined by the charge required to be transferred in a single switching pulse. The maximum power of the SCVM-type converter is achieved when the switched capacitors are fully discharged in a switching cycle (and then charged to the voltage equal to 2U_in). This determines the minimum capacitance, which in the SCVM composed of n switching cells is defined as follows:

C_min= 2nf_SU_in²/P_nom.

(12)

In a quasi inductiveless SCVM-type converter, the value of resonant inductance (L) is very small (L can be designed as a PCB air choke). Therefore, to achieve the assumed switching frequency, the capacitance of the switched capacitors can be selected considerably bigger than C_min (as in the case of the experimental setup presented in this paper). In the stage 2 (Figure 11b), the currents of capacitors C₁–C₃ and inductances L₁–L₃ have the same values (Equations (8)–(10)) as in the stage 1, but with the opposite signs. The voltages across the capacitors C₁, C₂, and C₃ in the stage 1 are given by

$$u_{C\text{1}}\left(t\right)=\left(U_{\text{in}}-U_{C11}\right)(1-\cos {\omega }_{\text{0}}t)+U_{C11}$$

(13)

$$u_{C2}\left(t\right)= -\frac{\left(U_{\mathrm{in}}- U_{C11}\right)}{2} (1 - \cos {\omega }_{0}t) + U_{C21}$$

(14)

$$u_{C3}\left(t\right)= \frac{\left(U_{\mathrm{in}}- U_{C11}\right)}{2} (1 - \cos {\omega }_{0}t) + U_{C31}$$

(15)

where U_C21 and U_C31 are the initial voltages across capacitors C₂ and C₃, respectively.

In the stage 2 (Figure 11b), the expressions for voltages have similar forms with appropriate signs and initial values.

Based on the formulas mentioned above, all the voltage initial values and the output voltage can be computed as a function of U_C11. For example, we obtain

$$U_{\mathrm{out}} = 5U_{\mathrm{in}}- U_{C11}$$

(16)

U_C11 can be calculated taking into account (8) and the following relation

$$I_{\mathrm{in}-\mathrm{av}} = I_{L1\mathrm{av}} = \frac{2}{\mathsf{\pi } }{I}_{1\mathrm{m}}{f}_{S\mathrm{n}} = \frac{P_{\mathrm{in}}}{U_{\mathrm{in}}}$$

(17)

$$U_{C11} = U_{\mathrm{in}} - \frac{\mathsf{\pi } \rho P_{\mathrm{in}}}{2f_{\mathrm{Sn}}{U}_{\mathrm{in}}}$$

(18)

where

$$f_{\mathrm{Sn}}= f_{\mathrm{S}}/f_0$$

(19)

From Equations (16) and (18), we have

$$U_{\mathrm{out}} = 4U_{\mathrm{in}}+ \frac{\mathsf{\pi } \rho P_{\mathrm{in}}}{2f_{\mathrm{Sn}}{U}_{\mathrm{in}}}$$

(20)

In practical converters, there are voltage drops across the circuit elements like the diodes and the transistors, which result in a variation of the output voltage with power and frequency.

The efficiency of an SCVM-type converter is determined by the resistances of its components, voltage drops on the diodes and transistors, the input voltage, power, and by the relation between the switching period T_S and period T₀ (2), which can be expressed by f_Sn (19). Therefore, it is necessary to calculate the average and rms values of the currents. It is assumed that transistors S₁ and S₃ are IGBTs, and S₂ and S₄ are MOSFETs.

$$I_{D1\mathrm{av}}= I_{D2\mathrm{av}}= \frac{I_{\mathrm{L}1\mathrm{av}}}{2} = \frac{1}{\mathsf{\pi } }{I}_{1\mathrm{m}}{f}_{S\mathrm{n}} = \frac{P_{\mathrm{in}}}{2U_{\mathrm{in}}}, I_{D3\mathrm{av}}= I_{D\mathrm{out}-\mathrm{av}}= \frac{I_{\mathrm{L}2\mathrm{av}}}{2} = \frac{I_{\mathrm{L}3\mathrm{av}}}{2} = \frac{I_{\mathrm{L}1\mathrm{av}}}{4} = \frac{P_{\mathrm{in}}}{4U_{\mathrm{in}}}$$

(21)

$$I_{\mathrm{S}2}= \frac{1}{2}{I}_{1\mathrm{m}}\sqrt{f_{\mathrm{Sn}}} = \frac{\mathsf{\pi }{P}_{\mathrm{in}}}{4U_{\mathrm{in}}\sqrt{f_{\mathrm{Sn}}}}, I_{\mathrm{S}4}= \frac{1}{4}{I}_{1\mathrm{m}}\sqrt{f_{\mathrm{Sn}}} = \frac{\mathsf{\pi }{P}_{\mathrm{in}}}{8U_{\mathrm{in}}\sqrt{f_{\mathrm{Sn}}}}$$

(22)

For the LSCVMa, we have:

$$I_{S1\mathrm{av}}= I_{D1\mathrm{av}} = \frac{P_{\mathrm{in}}}{2U_{\mathrm{in}}}, I_{S3\mathrm{av}}= I_{D3\mathrm{av}}= \frac{P_{\mathrm{in}}}{4U_{\mathrm{in}}}$$

(23)

Conduction losses, ΔPc, in both converters are

$$\mathsf{\Delta }{P}_{\mathrm{c}} = {\displaystyle \sum _k{r}_k{I}_{\mathrm{S}k}^2}+ {\displaystyle \sum _l\mathsf{\Delta }{U}_{Dl}{I}_{Dl\mathrm{av}}}+ {\displaystyle \sum _m\mathsf{\Delta }{U}_{Sm}{I}_{Sm\mathrm{av}}}+{\displaystyle \sum _n{r}_T{I}_n^2}$$

(24)

where r_k denotes the total resistance of the branch with MOSFET transistor S_k (k = 2, 4), including the resistance of the transistor. ΔU_Dl is the voltage drop across diode D_l, ΔU_Sm is the voltage drop across IGBT transistor S_m, r_T is the resistance of each circuit with an IGBT transistor, and I_n is its rms current.

It is assumed that the voltage drops across the devices remain constant in the conducting state.

We assume that all the resistances and voltage drops are the same, i.e.

$$r_2 =r_4 = r, \mathsf{\Delta }{U}_{S1} = \mathsf{\Delta }{U}_{S2} =\mathsf{\Delta }{U}_S, \mathsf{\Delta }{U}_{D1} = \mathsf{\Delta }{U}_{D2} = \mathsf{\Delta }{U}_{D3} = \mathsf{\Delta }{U}_{D4} = \mathsf{\Delta }{U}_{D\mathrm{out}} = \mathsf{\Delta }{U}_D$$

(25)

The efficiency of the LSCVMa converter can be calculated as follows. The resistive losses in the circuits containing IGBTs are:

$$\mathsf{\Delta }{P}_{\mathrm{c}2} =r_T{I}_{L11}^2 + 2r_T{I}_{L31}^2 =\frac{{3\mathsf{\pi }}^2{P}_{\mathrm{in}}^2 r_T}{32U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}}$$

(26)

Taking (21)–(26) into account, the conduction losses can be presented as

$$\mathsf{\Delta }{P}_{\mathrm{c}} = \frac{{5\mathsf{\pi }}^2{P}_{\mathrm{in}}^2 r}{64U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}} + \frac{{3\mathsf{\pi }}^2{P}_{\mathrm{in}}^2 r_T}{32U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}} + \frac{3P_{\mathrm{in}}}{2U_{\mathrm{in}}}\left(\mathsf{\Delta }{U}_D + \frac{1}{2}\mathsf{\Delta }{U}_S\right)$$

(27)

The turn-off switching loss is zero, due to the ZCS switching. However, there is a turn-on switching loss, associated with charging and discharging the transistors’ output capacitances. The total switching power loss, ΔP_sw, is

$$\mathsf{\Delta }{P}_{\mathrm{sw}}= \mathsf{\Delta }{W}_{\mathrm{sw}}{f}_{\mathrm{S}} = \mathsf{\Delta }{P}_{\mathrm{sw}0}{f}_{\mathrm{Sn}}$$

(28)

where ΔW_sw is the energy lost at turn-on in the transistor’s resistances in a single switching cycle, and ΔP_sw0 = ΔW_sw·f₀ is power loss at resonant frequency. A way of calculating these losses is presented in Reference [31].

The efficiency is (Equations (27) and (28))

$$\eta = 1 - \frac{\mathsf{\Delta }{P}_{\mathrm{c}}}{P_{\mathrm{in}}} - \frac{\mathsf{\Delta }{P}_{\mathrm{sw}}}{P_{\mathrm{in}}} = 1- \frac{{5\mathsf{\pi }}^2{P}_{\mathrm{in}}^{2}r}{64U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}} - \frac{{3\mathsf{\pi }}^2{P}_{\mathrm{in}}^2{r}_T}{32U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}}- \frac{3P_{\mathrm{in}}}{2U_{\mathrm{in}}}\left(\mathsf{\Delta }{U}_D + \frac{1}{2}\mathsf{\Delta }{U}_S\right) - \frac{\mathsf{\Delta }{W}_{\mathrm{s}w}{f}_{\mathrm{S}}}{P_{\mathrm{in}}}$$

(29)

Introducing normalized quantities:

$$r_{\mathrm{n}} = \frac{r}{U_{\mathrm{in}}^2/P_{\mathrm{in}}}, r_{T\mathrm{n}} = \frac{r_T}{U_{\mathrm{in}}^2/P_{\mathrm{in}}}, \mathsf{\Delta }{U}_{D\mathrm{n}} = \frac{\mathsf{\Delta }{U}_D}{U_{\mathrm{in}}}, \mathsf{\Delta }{U}_{S\mathrm{n}} = \frac{\mathsf{\Delta }{U}_S}{U_{\mathrm{in}}}, \mathsf{\Delta }{P}_{\mathrm{sw}0\mathrm{n}} = \frac{\mathsf{\Delta }{P}_{\mathrm{sw}0}}{P_{\mathrm{in}}}$$

(30)

We can simplify the efficiency formula to the form

$$\eta = 1 - \frac{{5\mathsf{\pi }}^2{r}_{\mathrm{n}}}{64f_{\mathrm{Sn}}} - \frac{{3\mathsf{\pi }}^2{r}_{T\mathrm{n}}}{32f_{\mathrm{Sn}}} - \frac{3}{2}\left(\mathsf{\Delta }{U}_{D\mathrm{n}} + \frac{1}{2}\mathsf{\Delta }{U}_{S\mathrm{n}}\right) - \mathsf{\Delta }{P}_{\mathrm{sw}0\mathrm{n}}{f}_{\mathrm{Sn}}$$

(31)

The efficiency of the LSCVMb can be calculated with the use of the following components:

$$I_{S1\mathrm{av}}= I_{D1\mathrm{av}} + I_{D3\mathrm{av}} = \frac{3P_{\mathrm{in}}}{4U_{\mathrm{in}}}, I_{D4\mathrm{av}}= I_{D1\mathrm{av}}=\frac{P_{\mathrm{in}}}{2U_{\mathrm{in}}}$$

(32)

where D₄ is the LSCVMb additional diode (Figure 1b).

Conduction losses, ΔPc, of LSCVMb are as follows:

$$\mathsf{\Delta }{P}_{\mathrm{c}}=\frac{{5\mathsf{\pi }}^2{P}_{\mathrm{in}}^{2}r}{64U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}}+\frac{{3\mathsf{\pi }}^2{P}_{\mathrm{in}}^2{r}_T}{32U_{\mathrm{in}}^2{f}_{\mathrm{Sn}}}+\frac{P_{\mathrm{in}}}{U_{\mathrm{in}}}\left(2\mathsf{\Delta }{U}_D+\frac{3}{4}\mathsf{\Delta }{U}_S\right)$$

(33)

and the efficiency of the LSCVMb is

$$\eta = 1 - \frac{{5\mathsf{\pi }}^2{r}_{\mathrm{n}}}{64f_{\mathrm{Sn}}} - \frac{{3\mathsf{\pi }}^2{r}_{T\mathrm{n}}}{32f_{\mathrm{Sn}}} - \left(2\mathsf{\Delta }{U}_{D\mathrm{n}}+ \frac{3}{4}\mathsf{\Delta }{U}_{S\mathrm{n}}\right) - \mathsf{\Delta }{P}_{\mathrm{sw}0\mathrm{n}}{f}_{\mathrm{Sn}}$$

(34)

It can be seen from (30), (31), and (34) that the impact of the voltage drops across the diodes on the efficiency depends only on the ratio of these voltage drops to the supply voltage. The impact of the losses in the resistances is more complex. They increase with rising resistances and rising power, and decrease with rising input voltage and frequency f_S. Switching losses are proportional to switching frequency f_S.

The relationship between the efficiency and normalized frequency f_Sn = f_S/f₀ for three values of r_n (30): 0.016, 0.0304, and 0.040, ΔU_Dn (30) = 0.008 for the LCSCVMa and the LCSCVMb is shown in Figure 12. The value of r_n = 0.0304 corresponds to, e.g., U_in = 50 V, P_in = 200 W, L = 500 nH, C = 1.5 μF, r = 380 mΩ, and ΔU_Dn is equal to 0.008 for, e.g., ΔU_D = 0.40 V and U_in = 50 V. The value of relative switching losses P_sw0n (30) = 0.0101 (Figure 12b) is valid, e.g., for ΔW_sw (28) = 11 μJ, f₀ = 183.8 kHz, and P_in = 200 W. The efficiency of the LCSCVMb is slightly lower. In both cases, it increases with increasing normalized frequency, f_Sn, and strongly depends on the circuit parasitic resistances. Therefore, it is important to minimize them, and use transistors with low values of R_DS(on) and V_CE(on).

The efficiency can be computed in a similar way for the other switching strategies. However, the calculations will be more complex in the case of the strategies with more than 2 stages.

4. Experimental Verification

This chapter presents the experimental results of the LCSCVMb converter operation. All the tests were carried out under switching strategy C5. The experimental verification confirms the proper operation of the converter, according to its concept. The measured voltage gain was on the expected level, and all the relevant waveforms were consistent with the simulation results as well.

4.1. Experimental Setup

All the parameters of the converter used during the experimental research, as well as a photograph of the investigated converter, are collected in

Table 5. The most important parameters of the laboratory converter.

Parameter	Value	The Laboratory Setup
Input voltage	50 V
Output load	200 W
Switching frequency	133 kHz
Resonant capacitors	1.5 µF (KEMET R76 series)
Resonant inductances	Planar chokes: L = 500 nH, RESR = 18 mΩ @ 100 kHz
Transistors	IKB15N65EH5 (VDS = 650 V, VCE = 1.65 V) as S1 IPB50R140CP (VDS = 550 V, RDSon = 0.14 Ω) as S2 and S4
Diodes	STTH30L06G (IF = 30 A, VF = 1.0 V, VRRM = 600 V)
PCB	2 layers, 35 µm
Laboratory equipment	Digital scope: Tektronix MDO3104, current probes: Tektronix TCP0030 150 MHz (input current measurement), Rogowsky coil (switch current measurements) voltage probes: Tektronix THDP0200 200 MHz, Tektronix P5205 100 MHz, power analyzer: Yokogawa WT 1801

. The parameters of the experimental setup correspond to the simulation model, and the major difference can be found in the inductance of the planar PCB choke. The switching frequency in the experimental measurements has been adjusted to the oscillation period of the switched capacitor currents and differs from the value selected for the simulation tests. An IGBT switch was selected as S₁ in the LSCVMb, as this switch conducts the total charging current. This current can be significant, especially when the converter contains a larger number of the switching cells. In order to generate appropriate control signals, an FPGA evaluation board (INTEL DE0) was utilized. The basic clock frequency of this device was set at 200 MHz, and the time resolution of the generated signals was 5 ns. The test setup is an example design of the converter prepared for the purpose of research, to verify its concepts and feasibility. The tests were conducted with 50 V at the input; however, the voltage range as well as power and the design concept can be rescaled to the parameters of a target application. Moreover, it is important that the prospective applications of the non-isolated DC-DC converter should comply with safety standards.

4.2. Test Results

Figure 13a,b presents the waveforms of the switching signals with the input and output current. They confirm that the converter operates correctly according to strategy C5. From the waveforms presented in Figure 13c, it follows that the converter boosts the input voltage. The measured voltage ratio is 3.65. Figure 13d,e presents the input current waveform and the voltages across the resonant capacitors. From the waveforms presented in Figure 13d, the average voltage across the capacitors can be seen. To demonstrate more clearly the magnitude of the oscillation around the average voltage value of each resonant capacitor, the voltage traces in AC coupling mode were recorded as well (Figure 13e). Figure 13f presents voltage stresses across the switches. From these results, it follows that the voltage stresses on switches are significantly below the output voltage of the converter, which is very favorable from the switching losses standpoint.

During the experimental research, the basic operation concept of the investigated converter has been checked. Furthermore, the working correctness of the examined device under different output loads was verified. The tests were carried out for three output load values: 62, 146, and 290 W, focusing especially on the transistor currents and voltages. Figure 14 present the results of the conducted tests for different output load conditions. From the results, it follows that the converter operates properly in low and medium load conditions.

Figure 15 presents the results of the spectral analysis calculated for the input and output currents. The calculations have been carried out with the use of MATLAB software, based on the recorded experimental data. The data was collected by the digital oscilloscope (Tektronix MDO3104) with the sampling rate of 1 MS/s.

The experimental results of the output voltage of the LCSCVMb converter and its efficiency are presented in Figure 16. The efficiency is on an acceptable level. The voltage and efficiency drop versus power is typical for such SC-based converters, and results from their resistive losses. It should be noticed that the presented experimental setup is optimized towards the converter cost reduction. It was designed on a two-layer PCB of 35 μm. To increase the efficiency by reducing the parasitic resistance, a more expensive PCB and switches can be selected.

5. Conclusions

The presented concepts of the new topologies, as well as the comparison of parameters presented in Table 3, and charts in Figure 8, Figure 9 and Figure 10, lead to the following conclusions:

• The major idea of the proposed new converters is based on the elimination of the number of switches in a voltage multiplier (SCVM), while maintaining its proper operation. By the modification of an SCVM, the new topology concepts LCSCVMa and LCSCVMb were proposed, with a reduced number of switching cells and redesigned functions of the diodes. Depending on the technology of practical implementation, either of these converters can be more attractive than the other.
• Various switching strategies are possible for the converters, which affect the parameters of operation related to switching losses and the sizing of the passive components of the converter, but also the required input and output filters.
• The converter operates properly with a wide range of output loads.
• From the compared results, it follows that the most effective topology, the LCSCVMb, can operate with nearly the lowest parameters of AC component in the voltages on capacitors, and the highest frequency in the input and output current. This allows for a reduction of the converter volume, especially by optimizing the input and output filters.
• The discussed converters demonstrated an improvement in the SCVM topology, which may result in a prospective cost reduction.