Multiphysics Simulation of a Novel Self-Adaptive Chip Cooling with a Temperature-Regulated Metal Pillar Array in Microfluidic Channels

Abstract

Conventional liquid cooling techniques may provide effective chip cooling but at the expense of high pumping power consumption. Considering that there is dynamic heat load in practice, a self-adaptive cooling technique is desired to reduce operational costs while preserving inherent cooling effectiveness. In this work, a novel self-adaptive cooling strategy is presented to balance the thermal and flow efficiency in accordance with the dynamic thermal load, based on temperature-regulated movement of the metal pillar array in a microfluidic channel. With an illustrative device, the effectiveness of such a strategy is investigated using multiphysics modeling and simulation. As a case study, the device is considered to be initiated with a chip power of 5 W and an inlet coolant velocity of 0.3 m/s. It is shown that the temperature-regulated movement of the metal pillar heat sink will be activated rapidly and equilibrate within 30 s. Parts of the metal pillars immerse into the coolant flow, resulting in significantly improved heat transfer efficiency. The diminished thermal resistance leads to a reduction in chip temperature rise from 225 K (without structural adaptation) to 91.86 K (with structural adaption). Meanwhile, the immersion of metal pillars into the coolant also causes an increased flow resistance in the microfluidic channel (i.e., pressure drop increases from 859.27 Pa to 915.98 Pa). Nevertheless, the flow resistance decreases spontaneously when the working power of the chip decreases. Comprehensive simulation has demonstrated that the temperature-regulated structure works well under various conditions. Therefore, it is believed that the presented self-adaptive cooling strategy offers simple and cost-effective thermal management for modern electronics with dynamic heat fluxes.

1. Introduction

Despite the vast developments in science, an unavoidable byproduct produced in integrated circuits (ICs) is heat. The amount of residual heat produced is directly proportional to the power densities used. The thermal management system employed is crucial because it controls the temperatures of the chips, which in turn affects the performance and reliability of the electronic devices [1,2]. It was estimated that about 70% of failures in electronic devices are due to thermal issues. Additionally, the failure rate doubles for every 20 °C temperature rise in the substrate [3].

Nowadays, thermal management has become one of the main challenges for the development of electronic devices and systems [4,5,6]. With the increasing device density and decrease in electronic packaging size, the power density of electronics has risen significantly [7]. Traditional air-cooling techniques fail to meet the requirement, and thus liquid cooling techniques have attracted much attention. Substantial research efforts have focused on improving the heat transfer efficiency in liquid cooling. Many new techniques have been developed in recent years, such as microchannels [8,9,10], jet cooling [11,12], micro gaps with variable pin fin densities [13], and hybrid jet-impingement/micro-channel heat sink [14,15], etc.

To date, various types of liquid cooling systems have been widely used in high-performance computing and power electronics, among others [4,16]. Consequently, liquid cooling, with its enormous energy and water consumption, has an increasingly significant environmental impact [4,16,17]. For example, the energy consumption for cooling accounts for about 30–50% of the total in data centers in China [18]. In the USA, data centers consume 24 TWh of electricity and 100 billion liters of water to satisfy their cooling demands [17], equivalent to the residential needs of a city the size of Philadelphia [4].

Kandlikar reviewed the advances in IC cooling in the last decade [7]. It was mentioned that minimizing liquid pumping power is one of the three main factors that are important in the microfluidic design of the cooling system. A lot of effort has been put forth. Numerical simulation based on CFD (computational fluid dynamics) and the conjugate heat transfer model have routinely been used and are considered to be reliable for topology optimization of fluidic channels [19,20,21]. In recent years, novel concepts for energy-efficient liquid cooling have also been presented. For example, manifold microchannels (MMCs) have been proposed to overcome the high-pressure drop associated with these straight, parallel microchannels (SPMCs) [22]. Numerical simulation based on a 2.5D model [23] and a 3D model [24] both showed a significant reduction in pumping power requirements of MMCs. Another hotspot-targeted embedded liquid cooling was presented by Sharma et al. [25]. By applying rationally distributed channels, more uniform surface temperature as well as reduced coolant pumping power were obtained.

Although there are several interesting approaches for the thermal management of microelectronic devices, most of them are appropriate for a specific thermal map, especially for steady-state conditions [26]. However, the thermal load scenario is often time-dependent in practical applications [16,26,27,28]. Conventional heat sinks are designed with fluidic channels and heat-removal capability based on the worst thermal condition, which only occurs sometimes. As a result, it often leads to bad flow efficiency and unnecessary pumping power consumption [16,26,27,28]. Thus, a self-adaptive cooling scheme, which can tailor the flow resistance characteristic by dynamic heat generation, is expected to reduce pumping power waste while ensuring sufficient cooling capacity.

In recent years, several self-adaptive cooling techniques have emerged [16,20,26,27,28,29,30]. Typically, thermal-sensitive valves were designed and applied for flow regulation. For example, the paraffin-based valve was located at the inlet of a cold plate for spacecraft thermal management, and the temperature was well controlled by the phase transition of the paraffin [27]. Shape memory alloy (SMA) was also studied for similar functions without the leakage problem [29,30]. Utilizing the difference in thermal expansion coefficient between the metal and the silicon substrate, a temperature-sensitive metal beam microvalve array was fabricated for localized hotspot cooling [30]. Most recently, hydrogels were also proposed to fabricate thermal-sensitive valves, based on which the self-adaptive cooling scheme improves the coefficient of performance by an order of magnitude while achieving similar cooling capacity [16,28].

Success in flow and thermal regulation of the existing works has well demonstrated the high feasibility and great potential of self-adaptive cooling. However, a more cost-effective and robust structure is continuously in demand. Moreover, the currently available schemes rely on embedding certain components (e.g., valves) in microfluidic channels, which may lead to additional flow or thermal resistance under low heat flux conditions. In this work, we present a novel self-adaptive cooling strategy to balance the thermal and flow efficiency based on the temperature-regulated movement of the metal pillar array in a microfluidic channel. An illustrative device is also introduced. The structure is simple and can be manufactured with commonly used material and process. Details of the design are introduced in Section 2, and the self-adaptive cooling performance is evaluated by multiphysics simulation and described in Section 3 and Section 4. It is shown that the presented strategy is able to balance the thermal and flow efficiency intelligently in accordance with the dynamic thermal load. Therefore, it provides a cost-effective but efficient manner for intelligent liquid cooling.

2. Schematic Description

The schematic of the self-adaptive cooling is illustrated in Figure 1. Several high-power chips are mounted on a chip carrier, made of a high-conductivity material like silicon or GaN. On the backside of the carrier, there is a metal heat sink with a pillar array, which helps transport heat to the coolant in microfluidic channels more efficiently. A similar design has been commonly used in LTCC (low-temperature co-fired ceramics) modules [31,32]. In a series of recent works, it was proposed to extend the thermal vias (like the metal pillars in this work) in ceramics into the coolant to obtain enhanced heat transfer [33,34,35]. Nevertheless, there is an inconvenient drawback to this technique: the large pressure drops, which involve high pumping power.

To avoid such a problem, a temperature-regulated structure is designed based on a flexible material applied between the heat sink and the microfluidic channel. On the top of the carrier, there is an enclosed cavity. Along with the air inside being heated by the chip, the increased air pressure pushes the carrier as well as the heat sink downward. Consequently, the tails of the metal pillars are immersed in the coolant, and then improved heat transfer efficiency is obtained. In case the power of the chip decreases, air pressure in the cavity will be lowered. Then, the heat sink moves back, and the flow of coolant recovers gradually. Self-adaptive cooling, which enables a balance in heat transfer efficiency and flow efficiency, is achieved in this manner.

In the following text, a specific design of the device is considered. The overall dimensions are 20 mm (width) × 30 mm (length) × 6 mm (height). There is one microfluidic channel fabricated on a PMMA (Polymethyl Methacrylate) substrate with dimensions of 0.5 mm (width) × 0.5 mm (depth). On the top of the channel, a PDMS (Polydimethylsiloxane) layer is bonded to the PMMA substrate. A thermal test chip (TTC-1002, Thermal Engineering Associates, Inc., Santa Clara, CA, USA) made of silicon with dimensions of 0.254 mm (width) × 0.254 mm (length) × 0.62 mm is located in the cavity (1 mm height) of the PDMS layer. The maximum power is 6 W, corresponding to a heat flux density of 93 W/cm². The chip is mounted on a carrier made of GaN, with dimensions of 15 mm (width) × 15 mm (length) × 0.5 mm. A copper heat sink, with seven micropillars (diameter is 0.4 mm, height is 1.5 mm), is adhered to the back side of the chip carrier. The tails of the pillars are flush with the top wall of the microfluidic wall at the initial state.

3. Modeling and Simulation

To simulate the self-adaptive cooling performance, the dominant physical processes, i.e., heat transfer in the device, flow of coolant in the channel, and the temperature-regulated movement of the components, are modeled. A commercial platform, COMSOL Multiphysics (Stockholm, Sweden), is utilized for numerical simulation.

3.1. Conjugate Heat Transfer

Due to the low thermal conductivity of PMMA and PDMS, heat transfer in the components is ignored herein. The computational domains, including the solid domains and fluid domains, were established as shown in Figure 2a. A conjugate heat transfer technique was employed, i.e., the temperature fields in both fluid and solid domains are modeled simultaneously.

In the microfluidic channel, the governing equation for the transient heat transfer can be given as [19]

$$\rho C_p\frac{\partial T}{\partial t}+\rho C_{p}u·\nabla T+\nabla ·(-k\nabla T)=\Phi$$

(1)

where T is temperature, u is the velocity, k is thermal conductivity, C_p is the specific heat capacity and Φ is the heat source term due to viscous dissipation.

In solid materials as well as the air in the cavity, heat conduction is the dominant form of thermal behavior, whose governing equation is [19]

$$\rho C_p\frac{\partial T}{\partial t}+\nabla ·(-k\nabla T)=Q$$

(2)

where Q is the general heat source term. The value of Q is equal to the electrical power for the chip and zero elsewhere.

Unless otherwise specified, the initial temperature in the device is at room temperature of 293.15 K, and the inlet temperature of the coolant is kept at 293.15 K. All the walls of the computational domain are considered to be adiabatic.

3.2. Fluid Flow

The flow of coolant in the microfluidic channel is assumed to be incompressible and laminar, and the governing equations are expressed as [16,19]

$$\nabla \cdot u=0$$

(3)

$$\rho \frac{\partial u}{\partial t}+\rho (u\cdot \nabla u)=-\nabla p+\mu {\nabla }^{2}u$$

(4)

where p is pressure and μ is dynamic viscosity. The given velocity is applied at the inlet, and the outlet is at the atmospheric pressure, as shown in Figure 2b.

3.3. Temperature-Regulated Movement

The mechanical movement of the movable components is described as [36]

$$\rho \frac{{\partial }^{2}d}{\partial t^2}-\nabla \cdot \tau =0$$

(5)

where d is the displacement field and τ is the stress tensor.

As shown in Figure 2c, the boundary conditions include three forces exerted on the component surfaces. A fluid–structure interface is applied to describe the force exerted on the metal pillars by the coolant flow (f_water). In addition, air pressure (p_air) is exerted on the top surface of the chip as well as the carrier and the elastic force by the PDMS layer on the bottom surface of the heat sink plate. According to the ideal gas law, the dynamic air pressure can be determined by

$$p_{air}=p_0\left(1-\frac{T_0}{T}\right)\frac{h}{h-d_z}$$

(6)

where p₀ and T₀ are the initial pressure and temperature, respectively, h is the height of the air cavity, and d_z is the vertical displacement of the chip carrier.

The heating of air by the chip results in an increase in air pressure which pushes the chip, the carrier, and the heat sink to move downwards. The PDMS layers below are compressed, and the elastic force is then generated.

$$f_e=\frac{E}{\delta }{d}_z$$

(7)

where E is Young’s modulus and δ is the thickness of the PDMS layer between the heat sink plate and the microfluidic substrate.

3.4. Numerical Simulation

A numerical model has been established using COMSOL Multiphysics accordingly. Three physics modules (heat transfer in solids and fluids, single-phase flow, and solid mechanics) and two multiphysics interfaces (nonisothermal flow and fluid–structure Interaction) are used to describe the aforementioned physics processes. The temperature-dependent thermo-physical properties of materials are obtained from the built-in library of the software. The Young’s modulus of PDMS, E, is 360 kPa, and the thickness of the PDMS layer, δ, is 1.5 mm. A uniform volumetric heat source with the given heat rate is applied to the chip.

The computational domains are meshed with unstructured grids based on a physics-controlled method provided by COMSOL. If the metal pillars are immersed into the coolant flow, the fluid domain is deformed. To numerically describe such behavior, we use a built-in method, i.e., the fluid domain is set as a freely moving deformed mesh, following a Yeoh mesh smoothing deformation. The mesh displacement is controlled by the structural displacement at the boundaries.

To determine the optimal mesh size, a typical condition, where the power of the chip is 5 W and the inlet velocity of the coolant (water) is 0.3 m/s, is considered. Grid independence is examined by comparing the maximum chip temperature and pressure drop in the microfluidic channel with different meshes, as shown in

Table 1. Mesh independence examination results.

Element Size	Number of Elements	Maximum Chip Temperature (K)	Pressure Drop (Pa)
Fine	55,151	383.61	878.97
Finer	124,139	386.19	915.98
Extra fine	329,525	386.52	930.51

. Accordingly, the second mesh with the finer elements, as shown in Figure 2d, is adopted in the following simulation.

To calculate the time-dependent problems in COMSOL, the backward differentiation formula (BDF) solver is used with a default adaptive time-stepping scheme, which automatically adjusts the timestep size to maintain the desired relative tolerance (0.001).

4. Results and Discussion

The above-mentioned situation (chip power is 5 W and the inlet velocity of the coolant is 0.3 m/s) is considered as a case study. Simulated results are shown in Figure 3 and Figure 4.

Along with the working of the chip, the chip itself and the surrounding air are heated, as shown in Figure 3a and Figure 4a. Due to the limited space in the cavity, air pressure increases generally, as shown in Figure 3b. Such pressure pushes the chip carrier and the heat sink to move downwards, as shown in Figure 3c. The tails of the metal pillars on the heat sink are immersed in the coolant flow, as shown in Figure 4b. Consequently, the soft PDMS layer between the hard components (the heat sink and the microfluidic substrate) is compressed, and a reactive force is generated due to the elasticity of the PDMS layer. The elastic force increases rapidly along with the downward movement of the metal pillar array heat sink. Once the force catches up with the air pressure force, a new equilibrium state will be obtained.

According to the simulation, the device takes about 30 s to achieve equilibrium. The final displacement of the metal pillar heat sink is 0.115 mm, and the average chip temperature at the equilibrium state is 385.01 K, corresponding to an overall temperature rise of 91.86 K. Noticeably, such a result is obtained under a high heat flux density (77.5 W/cm²) but ultra-low coolant supply (0.075 mL/s) condition. For comparison, the temperature rise would be 225 K for the stationary structure, i.e., the heat sink and the chip carrier are fixed at the initial position, as shown in Figure 3a. The immersion of metal pillars into the coolant not only enlarges the effective heat transfer area, but also enhances the local heat transfer efficiency by playing as protrusions in microchannel flow [36,37]. However, additional resistance will be added to the flow of coolant, thus equilibrium pressure drop is higher than that of the stationary structure.

Based on the same numerical model, more comprehensive simulations have been performed considering various operating conditions. Firstly, the device is assumed to work with different chip power levels while the coolant supply keeps constant (0.3 m/s). As shown in Figure 5a, the higher thermal load there is, the more deeply the metal pillars will immerse into the coolant flow. Correspondingly, the heat transfer efficiency will be effectively improved. The effective thermal resistance R_t (calculated by R_t = (T_c − T_l)/Q [37], where T_c is the maximum temperature of the chip and T_l is the inlet temperature of the coolant) decreases from 26.42 K/W to 17.09 K/W when the chip power increases from 2 W to 6 W. As a result, the maximum chip temperature is much lower comparing with the non-adaptive structure as shown in Figure 5a.

The device is also considered to work under different conditions of coolant supply while the chip power keeps constant (5 W). As shown in Figure 6, the chip temperature can be maintained below 423.15 K (i.e., 150 °C) with a coolant supply as low as 0.03 mL/s (inlet flow velocity of 0.12 m/s). Alternatively, the chip temperature can be lower than 373.15 K (100 °C) when the coolant flow rate is over 0.11 mL/s (inlet flow velocity is 0.44 m/s). In contrast, the stationary structure without adaptive cooling requires a much higher flow rate (1.625 mL/s according to extrapolation) to obtain a similar cooling performance.

The significantly improved cooling performance of the device by the self-adaptive structure is obtained at the expense of an increased pressure drop in the microfluidic channel (e.g., from 876.48 Pa to 915.98 Pa for chip power of 5 W and coolant velocity of 0.3 m/s) because of the immersion of metal pillars into the coolant flow, as shown in Figure 3d, Figure 5c and Figure 6b. This means higher pump power will be consumed under high thermal load conditions. However, such adaptation is spontaneously conducted by the temperature-regulated structure and will be recovered as soon as the chip power decreases.

To further illustrate such performance of the device, a dynamic chip power condition is considered. The chip power steps from 5 W to 3 W at t = 30 s, and then steps to 6 W at t = 60 s, as shown in Figure 7a. Corresponding to such a working power profile, the chip temperature increases in the first 30 s, then decreases in the next 30 s, and increases again in the final 30 s, as shown in Figure 7b. Consequently, the downward movement of the metal pillar array as well as the chip carrier increases to 0.11 mm in the first stage, then decreases to 0.079 mm in the second stage, and finally increases to 0.12 mm, as shown in Figure 7c. The decrease in chip temperature leads to a pressure drop from 920.83 Pa to 870.39 Pa in the second stage, and in turn, the increase in chip temperature in the third stage leads to an increase in pressure drop to 940.74 Pa.

5. Conclusions

In this work, we present a novel self-adaptive cooling strategy based on the temperature-regulated movement of a metal pillar array in a microfluidic channel. Air pressure in the cavity that encloses the chip is used as the driving force of the movement, and the elastic force from the compressed flexible layer is used as the resistance and reconfiguring force. In this manner, a simple and cost-effective temperature-regulated structure can be obtained. A multiphysics model has been established to describe the conjugate heat transfer and fluid–structure interaction behaviors in the device, and then the thermal and flowing performance of an illustrative device is evaluated with numerical simulation. In case the device is initiated with a chip power of 5 W and an inlet coolant velocity of 0.3 m/s, the temperature-regulated movement will be activated quickly. Parts of the metal pillars (0.115 mm at equilibrium) immerse into the coolant flow, leading to a significantly improved heat transfer efficiency, which diminishes temperature rise from 225 K (without structure adaption) to 91.86 K (with structure adaption). Meanwhile, there is an increasing pressure drop in the microfluidic channel (from 859.27 Pa to 915.98 Pa in this case), representing an increasing pump power. Comprehensive simulations demonstrated that the temperature-regulated structure works well under various conditions, resulting in improved cooling for the chip under the high thermal load conditions at the expense of increased pumping power for the coolant. As soon as the working power of the chip decreases, the required pumping power decreases spontaneously.

In conclusion, the feasibility of the presented self-adaptive cooling strategy has been well demonstrated based on multiphysics simulation. The illustrative device has been shown to be able to balance the thermal and flow efficiency intelligently in accordance with the dynamic thermal load. Therefore, we believe the presented strategy offers both cost-effective and highly efficient thermal management for modern electronics with dynamic high heat fluxes. In the near future, prototype devices will be made, and extensive experiments will be conducted for further validation.