The Preparation and Properties of a Hydrogen-Sensing Field-Effect Transistor with a Gate of Nanocomposite C-Pd Film

Abstract

The objective of this paper is to evaluate the effect of a nanostructured C-Pd film deposited in the gate area of a field-effect transistor (FET) with a carbon–palladium composite gate (C-Pd/FET) on the hydrogen-sensing properties of the transistor. The method of preparing a field-effect transistor (FET) with a C-Pd film deposited as a gate and the properties of such a transistor and the film itself are presented. The C-Pd film deposited by PVD method on the gate area serves as an active layer. The PVD process was carried out in a dynamic vacuum of 10⁻⁵ mbar from two separated sources—one containing fullerenes (C₆₀) and the other containing palladium acetate. Scanning electron microscopy (SEM), energy-dispersive X-ray spectroscopy (EDS, EDX) and electrical property studies were used to the characterize C-Pd films and FET/C-Pd structures. SEM observations revealed the topography of C-Pd films and FET/C-Pd transistors. EDS/EDX microanalysis was applied to visualize the arrangement of elements on the studied surfaces. The changes in electrical properties (resistance and relative resistance) due to the presence of hydrogen were studied in a designed and computerized experimental set-up. The enhanced properties of the FET/C-Pd transistor are demonstrated in terms of hydrogen detection.

1. Introduction

Open-gate field-effect transistors have been known and used for many years, especially in biosensing, gas sensing and chemical sensing. One type of open-gate field-effect transistor (FET) is an ion-sensitive field-effect transistor (ISFET), which is widely used in pH measurement [1], analytical and biomedical applications and water pollution monitoring [2,3,4]. This design can be used to measure the concentration of ions in various solutions [5]. When the ion concentration changes, the output current also changes accordingly. The process of producing an open-gate FET is similar to a typical MISFET (Metal Insulator Semiconductor Field-Effect Transistor), but in the case of an open-gate FET, the gate electrode is separated from the channel by an ion-sensitive barrier and has a window that allows for contact of the tested substance with the sensitive barrier. Various materials are applied as membranes, but the most common is a Si₃N₄ layer, mainly due to establishment of silicon nitride deposition technology in the microelectronics industry. However, other dielectric materials can be applied [6].

The gate length is a key parameter controlling the transport of carriers between electrodes. The gate surface can be covered with a thin film, which changes some of the electrophysical properties of the transistor.

The idea of using thin film for gate modification in FETs has often been presented for both inorganic and organic thin films. Such FET sensors allow for the simple implementation of efficient and low-cost devices that detect various gaseous, chemical and biological materials. Scientists and technologists have proposed, among others, FETs with silicon nanowires [7], carbon nanotubes (CNT) [8] or two-dimensional (2D) graphene [9]. It was shown how to achieve rapid-response hydrogen sensors by applying graphene combined with metal oxide nanoparticles (NPs) in [10]. This sensor, based on graphene transistors decorated with SnO₂ NPs, can detect low levels of H2 at room temperature.

In 1975, Lundström et al. first reported a Pd-gate hydrogen-sensitive FET [11,12]. Catalytic gate field-effect devices contain a nanolayer of catalytic metals such as palladium and platinum as the gate electrode on insulating layers in a metal–insulator–semiconductor (MIS) structure [13]. Gas detection mechanisms in catalytic gate FETs and catalytic gate field-effect devices are described in [13,14].

In this paper, we report a new type of transistor with an open gate and a palladium–carbon nanocomposite as the gate (C-Pd/FET). The transistor design was evaluated and patented by our group in 2018 [15]. The C-Pd film is a nanostructured film composed of nanograined palladium placed in a carbonaceous matrix, as stated in our previous papers [16,17,18]. The gate region is covered with a carbonaceous–palladium (C-Pd) nanocomposite film with semi-metallic or semiconductor properties. The method of producing the C-Pd nanocomposite film and its properties were described by our group in previous papers [16,17,18]. We have shown that the C-Pd film is composed of palladium nanoparticles (a few nanometers in diameter) of the fcc crystalline type with a lattice constant slightly higher than that of bulk Pd fcc crystal. These nanoparticles are placed in a carbonaceous matrix composed of carbon-ordered areas (graphene or graphite-like) with sizes of several dozen nanometers. This form of C-Pd film provides the same hydrogen adsorption/desorption mechanism as bulk palladium, but the material is much cheaper than the pure palladium typically used in hydrogen sensors. The mechanism of hydrogen diffusion in bulk palladium was studied and described in [19]. The lattice constant of palladium nanograins changes as a result of Ostwald ripening [20], in addition to the diffusion of hydrogen into the palladium lattice and the occupation of its interstitial sites. This effect for bulk metallic palladium was first described in the 19th century by Hoitsema [21]. Studies on the interaction of hydrogen with palladium nanoclusters or nanograins have been conducted by many researchers [22,23,24,25,26] due to the particular interest in hydrogen storage and detection. It was found that the morphological or structural change of the nanoclusters could affect the hydrogenation properties more compared to the bulk material. On the other hand, the problem of stabilizing Pd nanoclusters and preventing their agglomeration, leading to the formation of extensive macrostructures, has also been studied [27,28]. Graphene or carbon polymers can play this role. We have demonstrated that stabilization can be achieved by distributing nanograined palladium in a multiphase carbonaceous matrix [29]. Simultaneously, the carbonaceous matrix itself does not constitute a barrier to effective hydrogen diffusion.

Herein, we describe a facile design to achieve rapid-response, highly sensitive hydrogen sensors obtained by depositing a C-Pd nanocomposite film as a gate in a Si open-gate FET transistor (C-Pd/FET) using a PVD process. Studies on the morphology, topography, structure and composition of C-Pd/FET have shown that C-Pd film is a suitable material for a sensitive gate FET. We also present the influence of the morphology and topography of this transistor on its hydrogen detection properties. The response of this C-Pd/FET sensor is much faster, and its sensitivity is also much higher than those of C-Pd film-based resistive sensors [30].

2. Materials and Methods

2.1. Transistor Preparation

The C-Pd/FET was prepared in two steps. The first step was to obtain open-gate transistors on a Si wafer. After chip separation (each chip contained a single transistor), the PVD process was performed by depositing a C-Pd film in the gate region.

2.1.1. C-Pd Film Preparation Method

Multilayer C-Pd films were prepared by PVD (Physical Vapor Deposition) method. The process was performed from two separate sources, with the first source containing C₆₀ fullerite powder (Merck, Darmstadt, Germany, 99.5%) and the second containing palladium acetate (Merck, 99.9%). The duration of the process was 5–9 min under a dynamic vacuum of 10⁻⁵ mbar. The substrates were placed in a vacuum chamber above the sources, and the geometry of their location (source and substrate) is shown in Figure 1. The substrate temperature was measured during the process, and the final temperature (process completion) is presented in

Table 1. PVD process parameters and obtained Pd content.

Process/Transistor	t [min]	D [cm]	MC60 [W]	MPd [W]	Resistance [kOhm]
P1/T1-884	6	72	14	122	5
P2/T2-885	5	72	10	130	20
P3/T3-898	5	95	-	100	-
P4/T4-935	10	95	14	130	0.8

t—PVD process duration; D—substrate–source distance; MC60—deposition power for a source containing C60; MPd—deposition power for a source containing palladium acetate.

. To test the properties of C-Pd films, several types of samples were prepared on Si and ceramic alumina substrates produced by the PVD process with the technological parameters presented in Table 1. The powder material deposition boat was made of tantalum. The deposition source current (I_source), as well as the power of this source (defined as M = U∙I_source, where U is the voltage applied to the source), was monitored. Our PVD process was too short to observe the power fluctuations during the process. The appropriate source-to-substrate distance made it possible to obtain a uniform thickness of the deposited film on large area using the deposition geometry shown in Figure 1.

The selected set of PVD process parameters allows for the preparation of C-Pd films with various compositions and morphologies. A sample with a palladium film and a palladium film on the FET gate region were deposited and marked as samples P3 (C-Pd films on alumina ceramic and Si substrate) and T3 (C-Pd films deposited on the transistor gate area). The on-state resistance of the FET was measured to characterize the C-Pd films deposited in the gate region. The resistance was strongly related to the palladium content. From our previous studies of C-Pd films deposited on various metallic and dielectric substrates [16,17,18,23,27,28], it is known that these films consist of nanograined palladium embedded in a carbonaceous matrix. The size and distribution of these nanograins influence the electrical conductivity of the C-Pd films. When the size of the nanograins was less than 10 nm and they were densely dispersed in the film volume, the conductivity was high, and the resistance was of the order of several kOhm or lower. The palladium content in the investigated film is quite difficult to determine and cannot be taken as a specific process parameter.

Stylus profilometry measurements showed that the thickness of the film was within the range of 200–300 nm, depending on the measurement point on the selected area (films are thicker at the edges).

2.1.2. FET Preparation

In order to fabricate n channel transistors, silicon technology was used [30]. The first step of the fabrication process of FET structures is thermal oxidation in order to obtain field oxide of approx. 440 nm in thickness. A p-type, <100>-oriented silicon substrate with resistivity of 6–8 Ohmcm was used. After the first photolithography, drain and source windows for phosphorous doping were opened, and the dopant diffusion process was carried out. After the cleaning processes, 20 nm thick SiO₂ film was fabricated by thermal oxidation. Next, photolithography allowed for the preparation of a photoresist mask for the etching process. Then, windows for metallization were opened, and aluminum was deposited. The last step of MIS structure production was deposition of a C-Pd layer.

2.1.3. FET/C-Pd Preparation

A special mask was designed for deposition of C-Pd film in the transistor gate area. This mask has a set of holes of 1 mm in diameter. The mask was fixed under the silicon chips in such a way that holes were placed over the gate areas. Several transistors were attached to a plate playing the role of a carrier (Figure 1) for each PVD process. The red circles in Figure 2a represent the places where C-Pd film was deposited in the gate area. Finally, the FET structures were coupled to a specially designed double-side dPCB (Printed Circuit Board) holder, then electrically bonded using a 100 μm wire ultra-compression bonding technique. The holder allowed for the mounting of the structure as a part of an automatic stand (Figure 2b,c). Figure 2d shows the gate area. The gate width is approximately 15 µm.

2.2. Description of Material Characterization Methods

The obtained transistors were investigated using scanning electron microscopy (SEM) with energy dispersive X-ray spectrometry (EDS). The electrical response of FET/C-Pd to hydrogen was studied in a set-up prepared in the Lukasiewicz Research Network [31].

Scanning electron microscopy (SEM) observations of the surface morphology and cracks in the gate region were performed using a Hitachi SU70, Hitachi, Tokyo, Japan. Energy-dispersive X-ray spectroscopy (EDS) was also performed.

The topography and surface morphology of the C-Pd film were studied using a JEOL microscope type JSM-7600F, JEOL, Tokyo Japan. The microscope was equipped with an energy-dispersive X-ray (EDX) spectrometer using an X-MaxN Silicon Drift Detector (Oxford Instruments, Abingdon, UK). This method allowed for a comparative analysis of the palladium content in samples P1, P2, P3 and P4.

2.3. Experimental Set-Up for Testing Resistance Changes of FET/C-Pd Transistors under Gas Influence

An experimental station for testing changes in the resistance of FET/C-Pd transistors under the influence of gas was built in the Łukasiewicz Research Network, Tele and Radio Research Institute [30,31]. A schematic diagram of the experimental system is shown in Figure 3. This set-up consists of gas cylinders, flow controllers, a gas mixer, valves, a measuring chamber (50 mL in volume), a measuring system and a power supply. The system was described in [31] and is responsible for controlling valve operation, measurements and data acquisition.

Measurement results can be plotted as absolute resistance (R) or relative resistance (ΔR/R) as a function of the time of gassing and degassing of the measuring chamber with the investigated gas. The ΔR/R value is defined as follows:

$$\Delta R/R_0=\frac{R-R_0}{R_0}\cdot 100\%$$

where R₀ is the initial resistance, and R is the maximum instantaneous resistance in the cycle.

The measurement cycle consists of gassing and degassing processes of the entire volume of the measuring chamber. The full measurement cycle is presented in Figure 4. This procedure is time-consuming and increases the response time of the FET senor but allows for very precise calibration of the sensor as a function of gas concentration.

3. Results and Discussion

3.1. SEM for C-Pd Samples and FET/C-Pd Samples

SEM images of C-Pd and FET/C-Pd samples at different magnifications are presented below. SEM images of C-Pd film samples with high resistance (above 1 kOhm) show many bright objects that are Pd nanograins of various sizes but difficult to determine due to the low conductivity of the sample. The palladium grain size distribution was also very difficult to determine due to the dielectric nature of alumina ceramic substrates. An example SEM image of sample P1, a C-Pd film prepared on alumina ceramics, is presented in Figure 5a. The grain size cannot be determined in this case. It can be seen that the bright areas consist of many small objects, but the resolution of the SEM image does not allow for determination of their sizes.

Figure 5b shows an image of the C-Pd film deposited on the gate surface. The observed image can be associated with the very small size of Pd nanograins and their low density within the samples, which results in the high resistivity of the samples and, as a result, affects the contrast and resolution of the SEM image. The grain size was determined from a digitally zoomed image. The size of the grains examined in this way can range from a few nm up to several dozen nm. It is also seen that these bright areas form islands separated from each other. This structure of the sample results in high resistivity of the film.

SEM images of the low-resistance transistor (less than 1 kOhm) of the C-Pd film on alumina ceramic and on the gate surface are presented in Figure 5c,d. A microanalysis of the Pd content was performed, but its quantitative results are difficult to interpret due to the thin and non-uniform film thickness. At the power level used for EDX testing, the electron beam penetrates the film and the substrate simultaneously. In this case, the result contains information about all elements in the penetrated volume. The palladium content in samples P4 and T4 determined on the basis of the EDX spectrum is only qualitative and cannot be taken into account when comparing the Pd content in the studied samples. We estimated that they constitute 44–47 wt.% and ~45 wt.%, respectively. Additionally, results from different samples can be compared when the experimental conditions and film thickness are comparable. Comparing this result with EDX for samples P1 and P2, we find that the Pd content is higher for the P4 film. However, these results and the SEM observation results can explain the extent of the samples’ resistance changes. When the Pd nanograins are small and sparsely deposited in the film, the sample’s resistance is high. The resistivity decreases as the distance between the nanograins decreases. This situation is observed in the case of the P4 film sample and transistor T4. It can be concluded that the palladium content in these samples is higher than in other samples.

The C-Pd films deposited on an alumina ceramic substrate and on the gate surface are presented in Figure 5c,d. Despite the higher palladium content in these films, the image contrast is not improved because the observed C-Pd film is deposited on the aluminum ceramic, and we were unable to determine the size distribution of the observed area. The C-Pd film deposited in the gate area of the transistor generates SEM images with better contrast, which is related to its higher content of palladium on the conducting substrate where the alumina electrodes are conducting media. An analysis of the Pd grain size distribution is presented in Figure 5e.

This structure of the samples also confirms the results of resistance measurements. The resistance of these samples is high, and this effect may be caused by the poor redistribution of very small Pd grains in the dielectric carbonaceous matrix

The EDX results for samples P1 and P2 on the Si wafer, as well as T1 and T2, provide us with qualitative information on the Pd content. We found that this content was 38–41 wt.%.

In Figure 6, we present a schematic view of the transistor design for a better understanding of the EDS results. The EDS mapping is presented in Figure 5f. The images show the distribution of elements in the gate area for the C-Pd film (T4). For better measurement conditions, a sample obtained in the deposition process using only palladium acetate was used. Several elements were observed in EDS spectra, namely C, Pd, P, Si and O. Palladium and carbon are associated with the deposition process, and the area covered with these elements is observed on the transistor surface where the gate is located. The remaining elements come from the transistor technology process. Phosphorus is found everywhere, which is related to the transistor preparation technology; oxygen is related to SiO₂; and Si is the basic component of the substrate. The signal from silicon is present in all observed fragments, and it is slightly weaker at the SiO₂ layer. It was clearly observed that the C-Pd film is deposited over a larger area than the gate film.

3.2. Resistive Response in the Presence of Hydrogen

The hydrogen detection capabilities of transistors with a C-Pd film on the gate surface were studied. The sensing mechanism responsible detection in the C-Pd/FET sensor is related to the change in the resistance of the C-Pd layer during the hydrogen absorption/desorption process. The layer consists of nanopalladium grains placed in a carbonaceous matrix. When hydrogen is incorporated into the grain network, PdH_x is formed, with x depending on the amount of hydrogen introduced, and this phenomenon causes an increase in resistance. The decomposition of PdH_x is observed as a result of hydrogen desorption. The absorption/desorption process is reversible, without the need to heat the sensor [23].

Changes in the charge of the H₂-sensitive C-Pd layer translate into changes in the channel area, which causes drain current (channel resistance) changes. As the transistor structures operate based on electric field influence, small changes in charge in the gate area are clearly visible in the parameters of these devices.

The best sensing properties are observed when the resistance of the C-Pd layer is approximately 1–5 kOhm [17,23].

Various resistances were observed that are directly related to the palladium content. The specific initial resistances of the studied films deposited on the transistor are presented in Table 1. All measurements (gassing and degassing process) were performed at atmospheric pressure and room temperature.

Changes in resistance due to hydrogenation of the measuring chamber were studied for all transistors. The best sensing properties were obtained for the film with the lowest initial resistance (below 1 kOhm), i.e., for sample T4. The response of the C-Pd film transistor is stable and reversible, without the need for additional operations such as heating of the transistor for degassing or outgassing by pumping. No response to hydrogen was observed for sample T3. The response was weak for samples T1 and T2 (relative resistance was less than one percent) and very noisy. The gassing and degassing processes were not reversible. The response of FET/C-Pd to hydrogen for sample T4 is presented in Figure 7a,b. It can be seen that the sensitivity versus time graphs increase with the increase in hydrogen concentration (which occurs when filling the measuring chamber with gas). This behavior can be interpreted as the effect of the formation of PdH_x nanograins in the film volume. This effect can be very a fast phenomenon due to the nanometer size of the Pd nanograins, which facilitates the penetration of hydrogen into the grains. The superficial hydrogen absorption coefficient of Pd nanograins is similar to the volumetric absorption coefficient. The sensitivity of this transistor is very high, which allows for the measurement of very low hydrogen concentrations.

The response time is short, as is the relaxation time. A fragment of the changes in relative resistance and response time specific for sample T4 is presented in Figure 8. The response time (t90) is ~10 s, and the relative change in resistance exceeds 25%. It can be assumed that the effective response time is much shorter, taking into account the specificity of the measurement method (the measuring chamber must be filled with a gas, which increases the response time).

The dependence of resistance on concentration for transistor T4 is presented in Figure 9. This characteristic covers a very wide range of H₂ concentrations (from 0.3 up to 4%). This characteristic allows for simple and very fast detection of hydrogen concentration in the immediate vicinity of the transistor. The possibility of obtaining such broad characteristics is also due to the nanostructured nature of the C-Pd film.

4. Conclusions

In summary, a new type of field-effect transistor with a C-Pd film (FET/C-Pd) deposited as a gate was demonstrated. Transistors with different palladium contents in the gate area were obtained. The palladium content and the palladium nanograin size can be related to the resistance of the C-Pd film. The best hydrogen detection properties were obtained for the highest palladium content in the FET/C-Pd gate region. Hydrogen-sensing properties occur for such a transistor when the on-state resistance of the FET/C-Pd is less than 1 kOhm.

Comparison of these results with those previously published in our papers shows that the transistor sensor with a C-Pd layer has significantly better sensitivity than the resistive sample. It was shown that the related resistance changes reach 25%, and for some samples, they are even better, while for resistive sensors, they reach 10–15%. The sensitivity of our transistors sensor covers a wide range of hydrogen concentrations from 250 ppm up to 4%. Quantitative comparison is difficult due to the measurement method, taking into account the filling time of the measuring chamber, which results in an extended response time. The response time can only be estimated. On the other hand, it is much lower. Comparison of the sensitivity and response time of the FET/C-Pd sensor with literature data for traditional palladium sensors shows that it is better than other palladium-based sensors. The FET/C-Pd transistor can be applied as a very sensitive and fast hydrogen sensor for a very wide range of hydrogen concentrations. It is assumed that with the high sensitivity of the transistor, a hydrogen concentration of the order of ppm could be measured. Hydrogen absorption is reversible and does not require heating, while degassing in air is sufficient to restore the transistor to its initial state.

The structural properties of FET/C-Pd were investigated, while the properties of the film itself can be partially predicted based on previous work. The topography and morphology of C-Pd films deposited on the transistor as a gate are not modified compared to the process of deposition on other substrates. Palladium nanograins in C-Pd film are evenly dispersed in the film and have a size ranging from a few to 20 nm.