Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing
Abstract
:1. Introduction
- Noise: low-frequency (flicker) noise affects cells behavior, as random electron traps are located in the cell lattice, especially in the amorphous region.
- Time drift: cell conductance tends to decrease due to amorphization and relaxation phenomena of the crystal lattice.
- Uncertainty of the initial conductance value: different cells respond differently to the same programming pulses. Moreover, the response of the same cell to subsequent programming cycles shows a large variability. This leads to dispersion and inaccuracy of the conductance levels.
2. Material and Methods
2.1. PCM Test Chip and Evaluation Board
2.2. Programming Pulses Parameters
- a SET pulse is a trapezoidal current pulse, composed of an initial melting phase, followed by a slow crystallization phase;
- a RESET pulse consists in a higher current flow and it is applied in order to melt the central portion of the cell. The molten material quenches into the amorphous phase, producing a cell in the high-resistance state.
- the SET pulse can be modulated in amplitude (AS), width of the flat portion (TON,S), and decaying slope (ΔI/ΔT);
- the RESET pulse can be modulated in amplitude (AR) and width TON,R.
2.3. Readout Voltage Choice
3. Results and Discussion
3.1. PCM Cell Characterization Using Single-SET Pulses
3.1.1. Noise
3.1.2. Time Drift
3.2. PCM Cell Characterization Using Multiple Pulses
3.2.1. Conductance Tunability
3.2.2. Drift-Induced Dispersion
4. A Programming Algorithm for AIMC
5. Conclusions
Author Contributions
Funding
Institutional Review Board Statement
Conflicts of Interest
References
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Parameter | Minimum | Maximum | Resolution | Order of Magnitude |
---|---|---|---|---|
AS 1 | AS0 | ≈6 AS0 | ≈AS0/10 | 10–100 μA |
TON,S | TON,S0 | 2 TON,S0 | TON,S0/2 | 100 ns |
ΔI | ΔI0 | 2 ΔI0 | ΔI0 | 10 μA |
ΔT | ΔT0 | 2 ΔT0 | ΔT0/2 | 10 ns |
AR 1 | AR0 | ≈6 AR0 | ≈AR0/10 | 10–100 μA |
TON,R | TON,R0 | 2 TON,R0 | TON,R0/10 | 10 ns |
Normalized Conductance Target | Number of Steps | Estimated Programming Time | |||
---|---|---|---|---|---|
Minimum | Maximum | Mean | Mean | Maximum | |
1/6 | 2 | 20 | 6 | 900 ns | 3 µs |
1/3 | 2 | 45 | 10 | 1.5 µs | 6.75 µs |
1/2 | 2 | 64 | 22 | 3.3 µs | 9.6 µs |
2/3 | 3 | 95 | 36 | 5.4 µs | 9.75 µs |
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Antolini, A.; Franchi Scarselli, E.; Gnudi, A.; Carissimi, M.; Pasotti, M.; Romele, P.; Canegallo, R. Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing. Materials 2021, 14, 1624. https://doi.org/10.3390/ma14071624
Antolini A, Franchi Scarselli E, Gnudi A, Carissimi M, Pasotti M, Romele P, Canegallo R. Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing. Materials. 2021; 14(7):1624. https://doi.org/10.3390/ma14071624
Chicago/Turabian StyleAntolini, Alessio, Eleonora Franchi Scarselli, Antonio Gnudi, Marcella Carissimi, Marco Pasotti, Paolo Romele, and Roberto Canegallo. 2021. "Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing" Materials 14, no. 7: 1624. https://doi.org/10.3390/ma14071624
APA StyleAntolini, A., Franchi Scarselli, E., Gnudi, A., Carissimi, M., Pasotti, M., Romele, P., & Canegallo, R. (2021). Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing. Materials, 14(7), 1624. https://doi.org/10.3390/ma14071624