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Article

150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers

by
Feng-Tso Chien
1,*,
Zhi-Zhe Wang
1,
Cheng-Li Lin
1,
Tsung-Kuei Kang
1,
Chii-Wen Chen
2 and
Hsien-Chin Chiu
3
1
Department of Electronic Engineering, Feng Chia University, Taichung 407, Taiwan
2
Department of Electronic Engineering, Minghsin University of Science and Technology, Hsinchu 304, Taiwan
3
Department of Electronic Engineering, Chang Gung University, Taoyuan 333, Taiwan
*
Author to whom correspondence should be addressed.
Micromachines 2020, 11(5), 504; https://doi.org/10.3390/mi11050504
Submission received: 23 March 2020 / Revised: 5 May 2020 / Accepted: 13 May 2020 / Published: 15 May 2020
(This article belongs to the Special Issue Miniaturized Transistors, Volume II)
Browse Figures
Versions Notes

Abstract

:
A rating voltage of 150 and 200 V split-gate trench (SGT) power metal-oxide- semiconductor field-effect transistor (Power MOSFET) with different epitaxial layers was proposed and studied. In order to reduce the specific on-resistance (Ron,sp) of a 150 and 200 V SGT power MOSFET, we used a multiple epitaxies (EPIs) structure to design it and compared other single-EPI and double-EPIs devices based on the same fabrication process. We found that the bottom epitaxial (EPI) layer of a double-EPIs structure can be designed to support the breakdown voltage, and the top one can be adjusted to reduce the Ron,sp. Therefore, the double-EPIs device has more flexibility to achieve a lower Ron,sp than the single-EPI one. When the required voltage is over 100 V, the on-state resistance (Ron) of double-EPIs device is no longer satisfying our expectations. A triple-EPIs structure was designed and studied, to reduce its Ron, without sacrificing the breakdown voltage. We used an Integrated System Engineering-Technology Computer-Aided Design (ISE-TCAD) simulator to investigate and study the 150 V SGT power MOSFETs with different EPI structures, by modulating the thickness and resistivity of each EPI layer. The simulated Ron,sp of a 150 V triple-EPIs device is only 62% and 18.3% of that for the double-EPIs and single-EPI structure, respectively.

1. Introduction

Trench power MOSFETs have become a superior device in the medium-to-low voltage power application field. In conventional trench MOSFETs, the gate is isolated from the drain region only by the gate oxide. This results in that trench MOSFETs exhibit large switching losses due to a high gate-to-drain capacitance (Cgd), which limits its application. In order to reduce the device-switching losses, many studies, such as a thick-bottom oxide layer (TBOX) design, W-gated, and RESURF stepped oxide (RSO) MOSFET, were proposed [1,2,3,4]. All of these structures feather a thick oxide between gate electrodes and drain area, to reduce device Cgd. The RSO structure uses a thicker oxide at the lower portion of the trench, to reduce Cgd, while it applies a thinner one at the upper portion of the trench, to be the gate oxide. Because the stepped gate electrode plays a role as an extended field plate (FP) to modulate the electric field (EF) around it, this structure not only reduces the feedback capacitance but also the Ron, by using a low-resistivity epitaxial layer. Although RSO design can reduce the Cgd, switching losses are still a big issue when a device is used in a high-frequency application. Split-gate trench (SGT) devices overcame that problem by adding a source electrode located between the gate and drain [5,6,7,8,9]. There are two parts in the trenches for a split-gate structure: The upper electrode is the gate, and the lower one is connected by a separate contact to the source, to play as a field plate to balance the charge in the n- drift epitaxy region. This field plate is surrounded with a thick oxide to be a MOS structure that induces a silicon depletion region once the electrode is biased at a more negative potential than the n- silicon region [10,11,12]. Furthermore, the extended field plate along the drift epitaxy layer shapes the electric field in the drift region that enables the drift depletion area to support a higher drain voltage by using a lower resistivity epitaxy layer to reduce device specific on-resistance [5,13]. In addition, the Cgd of an SGT can be reduced significantly because the gate electrodes are shielded from the drain region by these FPs [10,14,15].
Even RSO and SGT power MOSFETs can provide an effective way to reduce device feedback capacitance and Ron simultaneously. The on-state resistance for a device used in a higher voltage system (100 to 200 V) increases sharply, owing to a high-resistivity epitaxial layer. For 20–30 V low-voltage SGT devices, the channel resistance portion is dominant and amounts to over 60%–85% of the total device resistance. However, this channel resistance is reduced to only 30%–20% for 60–70 V middle-voltage-rating devices [16,17]. When the device rating voltage reaches 150–200 V, the drift resistance occupies about 90% of the total device resistance [16,18]. To achieve a high breakdown voltage (VBR) design without increasing the Ron too much, a gradient, two-stepped oxide or multiple stepped oxide designs were applied to the trenches and shown to improve device performance effectively [18,19,20,21]. Since the potential of the field plate (bottom gate) on the oxide around it is different everywhere, that leads to a different depletion strength and electric field between two trenches along the cell depth, [18,19,20,21] use oxide engineering to improve device performance. On the other hand, double split-gate resurf stepped oxide UMOS can overcome the non-uniform problem [15]; however, the oxide and poly process in the trenches is too complicated. The abovementioned methods could make the drift region have a more uniform EF distribution to sustain a higher VBR. However, these structures required multiple depositions and etching steps that complicate the fabrication process. Superjunction structures and wide bandgap SiC material devices are alternative ways to provide high-voltage and low-Ron,sp solutions [22,23,24,25]. However, the built-in superjunction depletion layer limits the scalability to lower voltages (<500 V) [3]. In addition, besides cost issues, low channel mobility owing to a high density of SiC/SiO2 interface traps and undesirable higher turn on voltage of the body diode of a wide bandgap SiC power MOSFET make SiC devices less attractive than Si ones for lower-voltage applications [26,27,28]. Lower-voltage SiC power MOSFETs have not yet been demonstrated [10]. For a device structure with a rating voltage below 200 V, Si SGT power MOSFET dominates and plays an important role in reducing the device Ron,sp in power applications.
In this study, we proposed a 150 V SGT power MOSFET with multiple EPIs, to improve the device characteristics, and applied the same way to design a 200 V SGT power device. The single-EPI structures are wildly used in the low-voltage (<50 V) SGT power MOSFETs design. When required device rating voltage is up to 50–100 V, single-EPI device makes this scheme suffer a sharply increased Ron. A double-EPI-layers structure was used to improve device Ron characteristics in some studies [29,30]. Compared to the single-EPI one, the double-EPIs device has a higher device output current than the single one. This unique merit allows for the possibility of the double-EPIs design to reduce Ron,sp, as well as its power consumption. In this study, we wanted to design and modify the EPI structures rather than the complicated fabrication ways mentioned in [15,18,19,20,21], to reduce device Ron and sustain a high VBR at the same time. When device ranting voltage is designed to over 100 V, we find that the Ron of double-EPIs structure is no longer satisfying our expectations. Therefore, a triple-EPIs structure was applied, to modify the EF distributions between two trenches, instead of only depending on its magnitude supported by the bottom EPI. This design makes us have more flexibilities in designing the bottom EPI with a lower resistivity specification, to achieve a lower Ron,sp device. In double-EPIs design, the bottom EPI layer is used to support the VBR, and the top one could be used to modify the EF and reduce the Ron. For a triple-EPIs structure, the top and bottom EPI layers play the same roles as those is the double-EPIs device. The middle one is used to lower the Ron,sp if the top and bottom EPI layers can be properly designed. We applied ISE-TCAD to simulate and investigate by analyzing device potential and EF distributions with different epitaxial layers for all devices [31]. The Ron,sp of a triple-epitaxial-layer structure is much lower than those applied with a single- or double-epitaxial layer based on the same fabrication process.

2. Device Structure and Simulation

Multiple EPI structures were applied in this study. Figure 1 shows the trench location related to each structure with different epitaxial layers designs. The process steps of simulation for a three-epitaxial-layer device are shown in Figure 2. We started with a designed three EPIs above an n+ substrate. Detailed layers’ information is listed in Table 1. A trench was first defined and etched to the top of the bottom EPI. An oxide and polysilicon (Poly-Si) were sequentially deposited. After that, the deposited Poly-Si was etched back, to form a bottom gate. Then, the gate oxide was grown thermally, and a Poly-Si layer was deposited to fill the trenches and then etched to play the gates. Next, the device was implanted to accomplish the p--well and n+-well as the channel and the source region, respectively. After an oxide was deposited and contact holes were opened, an etching process was applied, and a p+ implantation was employed to improve the device’s ruggedness. Finally, a metal was formed to be the source electrode. Figure 3 shows the cross-section of this SGT power MOSFET structure with three epitaxial layers.

3. Results and Discussion

First, we constructed a 150 V device by using a double-EPIs structure. The trench depth we used here was 6 µm, from the top to the bottom EPI. For a double-EPIs structure, to improve its VBR, a thicker thickness or a higher-resistivity bottom EPI is required. However, it will increase Ron significantly. Then, we apply the same EPI thickness and trench depth as double-EPIs structure to all devices in the simulation. For comparison, we adopted the same bottom EPI specification for the double structure used as for the single-EPI device. For a triple-EPIs device, the EPI specifications are adjusted to achieve a balance to have a maximum VBR and a minimum Ron,sp. The EPI information for all structures is list in Table 2. All the devices simulated here use the same trench depth (6 µm). Different top- and middle-EPI-thickness designs are studied for a triple-EPIs device. Figure 4a shows the EF distributions with different top- and middle-EPI-thickness designs. We can see that the EF distributions between two trenches can be modified by different top and middle EPI thickness. Our approach to improving the EF distributions between two trenches is similar to that proposed in [15]. We used triple EPIs and [15] double split-gates with different bias in the trenches, to achieve the same purpose. The Ron is not affected by the top EPI too much; however, different electric field distributions with different EPI combinations here give us more room to design a high VBR device. One can expect that the highest breakdown voltage can be obtained in the largest area of the EF integration, with respect to the cell depth [19,22]. In our study, the best top-and middle-EPI-thickness ratio to sustain a high VBR device is 1:2. Figure 4b presents the simulated VBR and Ron,sp with different EPI-thickness designs.
Figure 5 and Figure 6 show the simulated potential and EF distributions for all structures under the same total EPI thickness. From the simulation, it is obvious that the triple-EPIs device can sustain a higher VBR easily than the others. A middle EPI layer is used to increase the EF magnitudes and then enhance the breakdown, as well as lower the Ron,sp simultaneously. In addition, it offers us more flexibility to adjust the resistivity of the bottom EPI, to further reduce its Ron,sp. The EF distribution curves in the cell center for all structures are shown in Figure 7. From this figure, the triple-EPIs design shows it has more uniform EF distributions between two trenches to sustain a higher VBR. In Figure 7, it is obvious that the two-layer structure can increase the device top electric field between two trenches; however, it decreases to a low value at p--well/n-EPI as the single one does. A triple-EPIs structure is designed to enhance the device EF between two trenches at the top and p- well/n− EPI area between two trenches to enhance device breakdown voltage. From Figure 7, we can observe a more uniform electric field distribution and the largest area under EF integration along the cell depth can be found in the triple-EPIs design. Therefore, the breakdown voltage of a triple-EPIs device can be improved. All devices’ performances are summarized in Table 3. By using the same EPI thickness, the triple-EPIs design has the highest breakdown voltage than other EPI structures.
Then we modified single-EPI and double-EPIs specifications to sustain the same VBR that a triple design can achieve. To increase the VBR of these two devices, the thickness and resistance of each EPI layer, as well as the trench depth, have to be increased. The EPI information for all structures is list in Table 4. Figure 8 shows the potential profiles for all devices. It can be seen that, in order to sustain a higher rating voltage, the thickness and resistivity of the single-EPI and double-EPIs structure must be thickened and increased to achieve a high VBR. The EF magnitude distributions of all structures are shown in Figure 9 and Figure 10. We can find that, the less EPI layers that are used, the lower the electric field valley, which weakens the support of a high VBR with a small Ron,sp. The triple-EPIs structure uses a middle EPI to enhance its electric field in the middle of the trench, where there is an EF valley observed in other structures. Therefore, a triple-EPIs structure is much easy to sustain a high VBR than other devices.
Figure 11 shows the output characteristics for all structures with the same VBR of 164 V. It can be observed that the Ron of a triple-EPIs design is much lower than those of the others. The triple-EPIs structure can sustain a higher VBR, owing to a more uniform electric field distribution between two trenches that is attributed to top- and middle-EPI design. It makes a triple-EPIs device more flexible on resistivity and thickness design for bottom EPI to achieve a low Ron characteristic. Table 5 demonstrates the Ron,sp for all devices with the same VBR. The simulated Ron,sp of a triple-EPIs device with a rating voltage of 150 V is only 62% and 18.3% of the one for the double-EPIs and single-EPI structure, respectively. Although a double-EPIs structure has better Ron,sp than the single one, the long trench depth, accompanied by a long top EPI thickness, makes it is hard to maintain a uniform electric field between two trenches. Therefore, a higher resistivity bottom EPI spec is required to sustain a high rating voltage that results in a higher Ron than the triple-EPIs design. Compared with other methods mentioned in [15,18,19,20,21], the multiple-EPIs structure does not complicate the process in manufacturing, and a higher-VBR and a lower-Ron,sp device can be achieved.
We also use the same method to construct 200 V SGT devices with different EPI designs. Similar electrical field distributions and output characteristics with Figure 10 and Figure 11 can be obtained, respectively, if we modify the best epitaxial specification. Table 6 lists the parameters that we used for all 200 V SGT devices’ simulation and shows their characteristics. Again, the triple-EPIs structure demonstrates more flexibility to achieve a lower Ron,sp than the single-EPI and double-EPIs devices under the same breakdown voltage design.
Figure 12 compares the specific on-resistance performance of our proposed SGT devices with that of the other middle-voltage devices reported in [4,15,21,32,33,34,35,36,37,38,39,40], ideal silicon limit, and super junction (SJ) limit for cell pitch = 5 and 10 µm in the 50–200 V range. Form Figure 12, we observe that the triple-EPIs structure and those using a double split-gate device [15] and stepped oxide SGTs [18,20,21] can achieve a very low Ron,sp in the middle-voltage range because they all can maintain more uniform EF distributions between two trenches. Compared with a double split-gate device and stepped oxide ones, our triple-EPIs devices do not require the complicated double split-gate or oxide-engineering process in the trenches and is compatible with the conventional SGT process.

4. Conclusions

A 150–200 V rating voltage triple-EPIs SGT-power MOSFET was proposed, studied, and compared with a single-EPI and double-EPIs structure. The middle EPI in the triple-EPIs structure is used to increase the low electric field between two trenches, thereby increasing the breakdown voltage and reducing the on-resistance. Compared with the single-EPI and double-EPIs structures, the triple-EPIs SGT-power MOSFET had a lower on-resistance. The simulated Ron,sp of a triple-EPIs device with a rating voltage of 150 V is only 62% and 18.3% of the one for the double-EPIs and single-EPI structure, respectively.

Author Contributions

Conceptualization, F.-T.C.; formal analysis, F.-T.C. and Z.-Z.W.; methodology, F.-T.C., Z.-Z.W., C.-L.L., and T.-K.K.; resources, F.-T.C. and C.-L.L.; software, F.-T.C., Z.-Z.W., and C.-W.C.; writing—original draft, F.-T.C. and Z.-Z.W.; writing—review and editing, F.-T.C., Z.-Z.W., C.-L.L., T.-K.K., C.-W.C., and H.-C.C. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the Ministry of Science and Technology of Taiwan, Grant MOST. no. 108-2221-E-035-039.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Takaya, H.; Morimoto, J.; Hamada, K.; Yamamoto, T.; Sakakibara, J.; Watanabe, Y.; Soejima, N. A 4H-SiC trench MOSFET with thick bottom oxide for improving characteristics. In Proceedings of the 25th International Symposium on Power Semiconductor Devices & ICs, Kanazawa, Japan, 26–30 May 2013; pp. 43–46. [Google Scholar]
  2. Darwish, M.; Yue, C.; Lui, K.H.; Giles, F.; Chan, B.; Chen, K.i.; Pattanayak, D.; Chen, Q.; Terrill, K.; Owyang, K. A new power W-gated trench MOSFET (WMOSFET) with high switching performance. In Proceedings of the 15th International Symposium on Power Semiconductor Devices & ICs, Cambridge, UK, 14–17 April 2003; pp. 24–27. [Google Scholar]
  3. Gajda, M.A.; Hodgkiss, S.W.; Mounfield, L.A.; Irwin, N.T.; Koops, G.E.J.; Dalen, R.V. Industrialisation of resurf stepped oxide technology for power transistors. In Proceedings of the 18th International Symposium on Power Semiconductor Devices & ICs, Naples, Italy, 4–8 June 2006; pp. 109–112. [Google Scholar]
  4. Koops, G.E.J.; Hijzen, E.A.; Hueting, R.J.E.; Zandt, M.A.A. RESURF stepped oxide (RSO) MOSFET for 85V having a record-low specific on-resistance. In Proceedings of the 16th International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, Japan, 24–27 May 2004; pp. 185–188. [Google Scholar]
  5. Goarin, P.; Koops, G.E.J.; Van Dalen, R.; Cam, C.L.; Saby, J. Split-gate resurf Oxide (RSO) MOSFETs for 25V applications with record low gate-to-drain charge. In Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs, Jeju, Korea, 27–30 May 2007; pp. 61–64. [Google Scholar]
  6. Vershinin, K.; Moens, P.; Bauwens, F.; Narayanan, E.M.S.; Tack, M. A new method to improve tradeoff performance for advanced power MOSFETs. IEEE Electron. Device Lett. 2009, 30, 416–418. [Google Scholar] [CrossRef]
  7. Baliga, B.J. Power Semiconductor Devices having Improved High Frequency Switching and Breakdown Characteristics. U.S. Patent 5998833, 7 December 1999. [Google Scholar]
  8. Zeng, J. Ultra Dense Trench-Gated Power Device with the Reduced Drain-Source Feedback Capacitance and Miller Charge. U.S. Patent 6 683 346, 27 January 2004. [Google Scholar]
  9. Zhang, W.; Ye, L.; Fang, D.; Qizo, M.; Xizo, K.; He, B.; Li, Z.; Zhang, B. Model and experiments of small-size vertical devices with field plate. IEEE Trans. Electron. Devices 2019, 66, 1416–1421. [Google Scholar] [CrossRef]
  10. Williams, R.K.; Darwish, M.N.; Blanchard, R.A.; Siemieniec, R.; Rutter, P.; Kawaguchi, Y. The trench power MOSFET: Part I—history, technology, and prospects. IEEE Trans. Electron. Devices 2017, 64, 674–691. [Google Scholar] [CrossRef]
  11. Kobayashi, K.; Sudo, M.; Omura, I. Power loss analysis of 60 V trench field-plate MOSFETs utilizing structure based capacitance model for automotive application. In Proceedings of the 10th International Conference on Integrated Power Electronics Systems, Stuttgart, Germany, 20–22 March 2018; pp. 122–127. [Google Scholar]
  12. Kobayashi, K.; Sudo, M.; Omura, I. Structure-based capacitance modeling and power loss analysis for the latest high-performance slant field-plate trench MOSFET. Jpn. J. Appl. Phys. 2018, 57(4S), 04FR14. [Google Scholar] [CrossRef] [Green Version]
  13. Peake, S.T.; Rutter, P.; Hodgskiss, S.; Gajda, M.; Irwin, N. A fully realized ‘field balanced’ trenchMOS technology. In Proceedings of the 20th International Symposium on Power Semiconductor Devices & ICs, Orlando, FL, USA, 18–22 May 2008; pp. 28–31. [Google Scholar]
  14. Williams, R.K.; Darwish, M.N.; Blanchard, R.A.; Siemieniec, R.; Rutter, P.; Kawaguchi, Y. The trench power MOSFET—Part II: Application specific VDMOS, LDMOS, packaging, and reliability. IEEE Trans. Electron. Devices 2017, 64, 692–712. [Google Scholar] [CrossRef]
  15. Wang, Y.; Hu, H.F.; Dou, Z.; Yu, C.H. Way of operation to improve performance for advanced split-gate resurf stepped oxide UMOSFET. IET Power Electron. 2014, 7, 2964–2968. [Google Scholar] [CrossRef]
  16. Park, C.; Havanur, S.; Shibib, A.; Terrill, K. 60 V rating split gate trench MOSFETs having best-in-class specific resistance and figure-of-merit. In Proceedings of the 28th International Symposium on Power Semiconductor Devices & ICs, Prague, Czech Republic, 12–16 June 2016; pp. 387–390. [Google Scholar]
  17. Takaya, H.; Miyagi, K.; Hamada, K.; Okura, Y.; Tokura, N.; Kuroyanagi, A. Floating island and thick bottom oxide trench gate MOSFET (FITMOS)—A 60V ultra low on-resistance novel MOSFET with superior internal body diode. In Proceedings of the 17th International Symposium on Power Semiconductor Devices & ICs, Santa Barbara, CA, USA, 23–26 June 2005; pp. 1–4. [Google Scholar]
  18. Park, C.; Azam, M.; Dengel, G.; Shibib, A.; Terrill, K. A new 200 V dual trench MOSFET with stepped oxide for ultra low RDS(on). In Proceedings of the 31st International Symposium on Power Semiconductor Devices & ICs, Shanghai, China, 19–23 May 2019; pp. 95–98. [Google Scholar]
  19. Chen, Y.; Liang, Y.C.; Samudra, G.S. Design of gradient oxide-bypassed superjunction power MOSFET devices. IEEE Trans. Power Electron. 2007, 22, 1303–1310. [Google Scholar] [CrossRef]
  20. Kobayashi, K.; Kato, H.; Nishiguchi, T.; Shimomura, S.; Ohno, T.; Nishiwaki, T.; Aida, K.; Ichinoseki, K.; Oasa, K.; Kawaguchi, Y. 100-V class two-step-oxide field-plate trench MOSFET to achieve optimum RESURF effect and ultralow on-resistance. In Proceedings of the 31st International Symposium on Power Semiconductor Devices & ICs, Shanghai, China, 19–23 May 2019; pp. 99–102. [Google Scholar]
  21. Kobayashi, K.; Nishiguchi, T.; Katoh, S.; Kawano, T.; Kawaguchi, Y. 100 V class multiple stepped oxide field plate trench MOSFET (MSO-FP-MOSFET) aimed to ultimate structure realization. In Proceedings of the 27th International Symposium on Power Semiconductor Devices & ICs, Kowloon Shangri-La, Hong Kong, 10–14 May 2015; pp. 141–144. [Google Scholar]
  22. Daniel, B.J.; Parikh, C.D.; Patil, M.B. Modeling of the coolMOS/sup TM/ transistor—Part I: Device physics. IEEE Trans. Electron. Devices 2002, 49, 916–922. [Google Scholar] [CrossRef]
  23. Lorenz, L.; Deboy, G.; Knapp, A.; Marz, M. COOLMOS/sup TM/-a new milestone in high voltage power MOS. In Proceedings of the 11th International Symposium on Power Semiconductor Devices & ICs, Toronto, ON, Canada, 26–28 May 1999; pp. 3–10. [Google Scholar]
  24. Kondekar, P.N.; Parikh, C.D.; Patil, M.B. Analysis of breakdown voltage and on resistance of super junction power MOSFET CoolMOS/sup TM/ using theory of novel voltage sustaining layer. In Proceedings of the 33rd Annual IEEE Power Electronics Specialists Conference, Cairns, QLD, Australia, 23–27 June 2002; pp. 1769–1775. [Google Scholar]
  25. Tian, K.; Hallén, A.; Qi, J.; Shenhui, M.; Fei, X.; Zhang, A.; Liu, W. An improved 4H-SiC trench-gate MOSFET with low on-resistance and switching loss. IEEE Trans. Electron. Devices 2019, 66, 2307–2313. [Google Scholar] [CrossRef]
  26. Chen, L.; Guy, O.J.; Jennings, M.R.; Igic, P.; Wilks, S.P.; Mawby, P.A. Study of 4H–SiC trench MOSFET structures. Solid State Electron. 2005, 49, 1081–1085. [Google Scholar] [CrossRef]
  27. Palmour, J.W.; Cheng, L.; Pala, V.; Brunt, E.V.; Lichtenwalner, D.J.; Wang, G.; Richmond, J.; O’Loughlin, M.; Ryu, S.; Allen, S.T.; et al. Silicon carbide power MOSFETs: Breakthrough performance from 900 V up to 15 kV. In Proceedings of the 26th International Symposium on Power Semiconductor Devices & ICs, Waikoloa, HI, USA, 15–19 June 2014; pp. 79–82. [Google Scholar]
  28. Li, X.; Tong, X.; Huang, A.Q.; Tao, H.; Zhou, K.; Jiang, Y.F.; Jiang, J.N.; Deng, X.C.; She, X.; Zhang, B.; et al. SiC trench MOSFET with integrated self-assembled three-level protection schottky barrier diode. IEEE Trans. Electron. Devices 2018, 65, 347–351. [Google Scholar] [CrossRef]
  29. Wang, Q.; Li, M.; Sharp, J.; Challa, A. The effects of double-epilayer structure on threshold voltage of ultralow voltage trench power MOSFET devices. IEEE Trans. Electron. Devices 2007, 54, 833–839. [Google Scholar] [CrossRef]
  30. Li, M.; Crellin, A.; Ho, I.; Wang, Q. Double-epilayer structure for low drain voltage rating n-channel power trench MOSFET devices. IEEE Trans. Electron. Devices 2008, 55, 1749–1755. [Google Scholar] [CrossRef]
  31. ISE-TCAD Manuals; Release 10.0; Integrated Systems Engineering: Zurich, Switzerland, 2004.
  32. Yamaguchi, H.; Urakami, Y.; Sakakibara, J. Breakthrough of on-resistance Si limit by Super 3D MOSFET under 100V breakdown voltage. In Proceedings of the 18th International Symposium on Power Semiconductor Devices & ICs, Naples, Italy, 4–8 June 2006. [Google Scholar]
  33. Hattori, Y.; Nakashima, K.; Kuwahara, M.; Yoshida, T.; Yamauchi, S.; Yamaguchi, H. Design of a 200V super junction MOSFET with n-buffer regions and its fabrication by trench filling. In Proceedings of the 16th International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, Japan, 24–27 May 2004; pp. 189–192. [Google Scholar]
  34. Weber, Y.; Morancho, F.; Reynes, J.; Stefanov, E. A New Optimized 200V Low On-Resistance Power FLYMOSFET. In Proceedings of the 20th International Symposium on Power Semiconductor Devices & ICs, Orlando, FL, USA, 18–22 May 2008; pp. 149–152. [Google Scholar]
  35. Miura, Y.; Ninomiya, H.; Kobayashi, K. High performance superjunction UMOSFETs with split p-columns fabricated by multi-ion-implantations. In Proceedings of the 17th International Symposium on Power Semiconductor Devices & ICs, Santa Barbara, CA, USA, 23–26 May 2005; pp. 1–4. [Google Scholar]
  36. Van Dalen, R.; Rochefort, C. Electrical characterisation of vertical vapor phase doped (VPD) RESURF MOSFETs. In Proceedings of the 16th International Symposium on Power Semiconductor Devices & ICs, Kitakyushu, Japan, 24–27 May 2004; pp. 451–454. [Google Scholar]
  37. Nitta, T.; Minato, T.; Yano, M.; Uenisi, A.; Harada, M.; Hine, S. Experimental results and simulation analysis of 250V super trench power MOSFET (STM). In Proceedings of the 12th International Symposium on Power Semiconductor Devices & ICs, Toulouse, France, 22–25 May 2000; pp. 77–80. [Google Scholar]
  38. Kurosaki, T.; Shishido, H.; Kitada, M.; Oshima, K.; Kunori, S.; Sugai, A. 200V multi RESURF trench MOSFET (MR-TMOS). In Proceedings of the 15th International Symposium on Power Semiconductor Devices & ICs, Cambridge, UK, 14–17 April 2003; pp. 211–214. [Google Scholar]
  39. Chen, X.B.; Mawby, P.A.; Board, K.; Salamab, C.A.T. Theory of a novel voltage-sustaining layer for power devices. Microelectron. J. 1998, 29, 1005–1011. [Google Scholar] [CrossRef]
  40. Chen, Y.; Liang, Y.C.; Samudra, G.S. Theoretical analyses of oxide-bypassed superjunction power metal oxide semiconductor field effect transistor devices. Jpn. J. Appl. Phys. 2005, 44(2R), 847. [Google Scholar] [CrossRef]
Micromachines 11 00504 g001 550
Figure 1. Split-gate trench power MOSFET structure with (a) single EPI, (b) double EPIs, and (c) triple EPIs.
Figure 1. Split-gate trench power MOSFET structure with (a) single EPI, (b) double EPIs, and (c) triple EPIs.
Micromachines 11 00504 g001
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Figure 2. Main simulated fabrication process for the triple-EPIs SGT power MOSFET: (a) three designed epitaxial layers; (b) defining the trench, bottom gate, and gate; (c) forming the channel and the source areas; (d) opening the contact holes and implanting the p+; (e) depositing the metal pads.
Figure 2. Main simulated fabrication process for the triple-EPIs SGT power MOSFET: (a) three designed epitaxial layers; (b) defining the trench, bottom gate, and gate; (c) forming the channel and the source areas; (d) opening the contact holes and implanting the p+; (e) depositing the metal pads.
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Figure 3. The cross-section diagram of a triple-EPIs SGT power MOSFET.
Figure 3. The cross-section diagram of a triple-EPIs SGT power MOSFET.
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Figure 4. (a) The simulated electric field curves in the middle of the cell and (b) the simulated VBR and Ron,sp with different top- and middle-EPI-thickness designs with the same total and bottom EPI thickness.
Figure 4. (a) The simulated electric field curves in the middle of the cell and (b) the simulated VBR and Ron,sp with different top- and middle-EPI-thickness designs with the same total and bottom EPI thickness.
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Figure 5. The simulated potentials for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at the same EPI thickness. The color bars are scaled on the same degree.
Figure 5. The simulated potentials for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at the same EPI thickness. The color bars are scaled on the same degree.
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Figure 6. The simulated electric fields for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at the same EPI thickness. The color bars are scaled on the same degree.
Figure 6. The simulated electric fields for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at the same EPI thickness. The color bars are scaled on the same degree.
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Figure 7. The simulated electric field curves for all devices with single EPI, double EPIs, and triple EPIs with the same total EPI thickness.
Figure 7. The simulated electric field curves for all devices with single EPI, double EPIs, and triple EPIs with the same total EPI thickness.
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Figure 8. The simulated potentials for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at 150 V rating voltage. The color bars are scaled on the same degree.
Figure 8. The simulated potentials for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at 150 V rating voltage. The color bars are scaled on the same degree.
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Figure 9. The simulated electric fields for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at 150 V rating voltage. The color bars are scaled on the same degree.
Figure 9. The simulated electric fields for the split-gate trench power MOSFET with (a) single EPI, (b) double EPIs, and (c) triple EPIs at 150 V rating voltage. The color bars are scaled on the same degree.
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Figure 10. The simulated electric field curves for the split-gate trench power MOSFET with single EPI, double EPIs, and triple EPIs at 150 V rating voltage.
Figure 10. The simulated electric field curves for the split-gate trench power MOSFET with single EPI, double EPIs, and triple EPIs at 150 V rating voltage.
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Figure 11. The output characteristic of the split-gate trench power MOSFET with single EPI, double EPIs, and triple EPIs.
Figure 11. The output characteristic of the split-gate trench power MOSFET with single EPI, double EPIs, and triple EPIs.
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Figure 12. The comparison of Ron,sp against VBR relationship of middle-voltage SGT structures, super junction devices, ideal silicon limit and super junction (SJ) limit (cell pitch = 5 and 10 µm).
Figure 12. The comparison of Ron,sp against VBR relationship of middle-voltage SGT structures, super junction devices, ideal silicon limit and super junction (SJ) limit (cell pitch = 5 and 10 µm).
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Table
Table 1. The simulation parameters that were used for the triple-EPIs structure.
Table 1. The simulation parameters that were used for the triple-EPIs structure.
ParameterValue
Cell pitch3.24 µm
Thickness of top EPI4 µm
Resistance of top EPI0.9 Ω·cm
Thickness of middle EPI2 µm
Resistance of middle EPI0.16 Ω·cm
Thickness of bottom EPI4 µm
Resistance of bottom EPI0.68 Ω·cm
Depth of trench6 µm
Width of trench1.8 µm
Thickness of bottom oxide0.8 µm
Thickness of gate oxide0.06 µm
Table
Table 2. The parameters that were used for the single-, double-, and triple-EPI structure simulation.
Table 2. The parameters that were used for the single-, double-, and triple-EPI structure simulation.
DeviceEPI Thickness (µm)EPI Resistance (Ω·cm)
Single EPI101.4
Double EPIsTop EPI = 6Top EPI = 0.35
Bottom EPI = 4Bottom EPI = 1.4
Triple EPIsTop EPI = 4Top EPI = 0.9
Middle EPI = 2Middle EPI = 0.16
Bottom EPI = 4Bottom EPI = 0.68
Table
Table 3. The characteristics of single-EPI, double-EPIs, and triple-EPIs SGT power MOSFET with the same total EPI thickness.
Table 3. The characteristics of single-EPI, double-EPIs, and triple-EPIs SGT power MOSFET with the same total EPI thickness.
DeviceBreakdown Voltage (V)Ron (mΩ·mm2)EPI Thickness (µm)
Single EPI130.93181.1610
Double EPIs153.8598.2310
Triple EPIs164.4967.7910
Table
Table 4. The parameters that were used for the single-EPI, double-EPIs, and triple-EPIs structure simulation.
Table 4. The parameters that were used for the single-EPI, double-EPIs, and triple-EPIs structure simulation.
DeviceEPI Thickness (µm)EPI Resistance (Ω·cm)Trench Depth (µm)
Single EPI1528
Double EPIsTop EPI = 9Top EPI = 0.358
Bottom EPI = 4Bottom EPI = 1.4
Triple EPIsTop EPI = 4Top EPI = 0.96
Middle EPI = 2Middle EPI = 0.16
Bottom EPI = 4Bottom EPI = 0.68
Table
Table 5. The characteristic of single-EPI, double-EPIs, and triple-EPIs 150 V rating voltage split-gate trench power MOSFET at the same cell pitch.
Table 5. The characteristic of single-EPI, double-EPIs, and triple-EPIs 150 V rating voltage split-gate trench power MOSFET at the same cell pitch.
DeviceBreakdown Voltage (V)Ron (mΩ·mm2)Cell Pitch (µm)
Single EPI164.2369.853.24
Double EPIs164.23109.563.24
Triple EPIs164.4967.793.24
Table
Table 6. The parameters that were used for the single-EPI, double-EPIs, and triple-EPIs structure simulation.
Table 6. The parameters that were used for the single-EPI, double-EPIs, and triple-EPIs structure simulation.
DeviceEPI Thickness (µm)EPI Resistance (Ω·cm)Breakdown Voltage (V)Ron (mΩ·mm2)
Single EPI164.8222.79729.7
Double EPIsTop EPI = 6Top EPI = 0.3221.73286.47
Bottom EPI = 9Bottom EPI = 3
Triple EPIsTop EPI = 4Top EPI = 0.8221.33184.36
Middle EPI = 2Middle EPI = 0.17
Bottom EPI = 7.5Bottom EPI = 2.1

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MDPI and ACS Style

Chien, F.-T.; Wang, Z.-Z.; Lin, C.-L.; Kang, T.-K.; Chen, C.-W.; Chiu, H.-C. 150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers. Micromachines 2020, 11, 504. https://doi.org/10.3390/mi11050504

AMA Style

Chien F-T, Wang Z-Z, Lin C-L, Kang T-K, Chen C-W, Chiu H-C. 150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers. Micromachines. 2020; 11(5):504. https://doi.org/10.3390/mi11050504

Chicago/Turabian Style

Chien, Feng-Tso, Zhi-Zhe Wang, Cheng-Li Lin, Tsung-Kuei Kang, Chii-Wen Chen, and Hsien-Chin Chiu. 2020. "150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers" Micromachines 11, no. 5: 504. https://doi.org/10.3390/mi11050504

APA Style

Chien, F. -T., Wang, Z. -Z., Lin, C. -L., Kang, T. -K., Chen, C. -W., & Chiu, H. -C. (2020). 150–200 V Split-Gate Trench Power MOSFETs with Multiple Epitaxial Layers. Micromachines, 11(5), 504. https://doi.org/10.3390/mi11050504

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