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Article

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET

1
School of Artificial Intelligence, Xidian University, Xi’an 710126, China
2
Hangzhou Research Institute of Technology, Xidian University, Hangzhou 311231, China
*
Author to whom correspondence should be addressed.
Micromachines 2024, 15(3), 411; https://doi.org/10.3390/mi15030411
Submission received: 16 February 2024 / Revised: 6 March 2024 / Accepted: 15 March 2024 / Published: 19 March 2024
(This article belongs to the Special Issue Power Semiconductor Devices and Applications, 2nd Edition)

Abstract

:
This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (RON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV2/RON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-RON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results.

1. Introduction

Power MOSFETs play a crucial role in power management and energy conversion systems. The superjunction (SJ) theory, utilizing a vertical P-N junction in the drift region, has been widely adopted in the design of vertical discrete power MOSFETs rated from 300 V to 1000 V. This approach achieves notably low specific ON resistance (RON,sp) and high breakdown voltage (BV), surpassing the conventional MOSFET silicon limit defined by RON,sp = 8.3 × 10−9 BV2.5 [1]. To further optimize performance, integrating a deep trench and an extended gate offers potential RON,sp reduction by minimizing device pitch and inducing an accumulation layer [2,3,4]. However, this improvement is hindered by the diminishing electric field (E-field) beneath the trench, and blocking voltage faces limitations due to charge balance issues [5,6].
Several strategies have been proposed to tackle this issue. One approach suggests the use of high-K (HK) dielectric in the drift region, as seen in prior studies [6,7,8]. However, the distribution of the E-field in the drift region is significantly affected by the presence of HK dielectric materials, making the complete optimization of the device’s overall E-field challenging. Another method involves enhancing the BV in UMOS by combining high aspect ratio trenches with high-resistance semi-insulating poly-crystalline silicon (SIPOS) structures [9]. This innovative combination offers UMOS the potential to achieve high BV while maintaining an ultra-low RON,sp.
Recent research has seen a surge in innovative approaches using machine learning techniques for device modeling and optimization [10,11,12,13,14,15,16]. For example, Klemme [12] developed a machine learning method for accurately predicting the transfer characteristics of negative-capacitance FinFET devices. Wang [13] improved an artificial neural network (ANN) model for general transistors by enhancing data pre-processing. Xu [14] introduced a machine-learning regression approach for single-electron transistors (SETs), training a neural network to effectively model SET pulse currents. These studies collectively illuminate the diverse applications of machine learning in device modeling and performance optimization. Zhang [15] proposed a concise modeling method for collaborative optimization and path searching in advanced design techniques using machine learning. Mehta [16] demonstrated the possibility of predicting full transistor current–voltage (IV) and capacitance–voltage (CV) curves using machines trained by technology computer-aided design (TCAD) generated data. These studies collectively illuminate the diverse applications of machine learning in device modeling and performance optimization.
This paper presents a physics-informed and machine learning-based model of the SIPOS (S) pillar-modulated structure in superjunction (SJ) UMOS (SSJ-UMOS), as depicted in Figure 1a,b. The explicit analytical model, grounded in Poisson’s solution, includes the E-field modulation effect, potential distributions, and charge-coupling effects. The model is constructed through a two-step process. Initially, it is derived using closed-form analytical expressions, incorporating Poisson’s solution to capture the basic physical mechanism of the device. Subsequently, machine learning techniques, such as Gaussian process regression (GPR), are employed for the figure of merit (FOM = BV2/RON,sp) prediction and hyperparameter optimization, fine-tuning the model parameters for optimal performance. This combined approach ensures an accurate representation of device behavior, refining predictions of characteristics like the optimal BV-RON,sp tradeoff, and surpassing the SJ silicon limit [17,18,19]. This hybrid modeling strategy synergizes analytical and machine learning methodologies, yielding a robust and precise device model. The analytical approach of this model can guide the optimization design for MOSFET devices with SIPOS E-field modulation.

2. Working Principle and Machine Learn Based Analytical Model

2.1. Charge-Coupling Effect of SIPOS Modulated Drift Region

Ref. [19] provides the revised optimum doping concentration (ND,SJ) for the N-pillar of the conventional SJ as
N D , S J = 2 E C U ε S i / q W N
where WN is the width of the N-pillar, and ECU is the critical E-field for breakdown with a uniform distribution. In contrast, the doping concentration in the drift region of the SSJ-UMOS (ND,SSJ) is determined by the two-dimensional charge coupling of the SJ structure and MIS structure SIPOS/oxide/Si. To achieve an effective charge-coupling effect, the highly doped N-pillar region with the total charge QN,SSJ,total must be completely depleted by the P-pillar of SJ structure with the charge QSJ,P and the MIS structure of SIPOS/oxide/Si with the charge QSIPOS,C, as the drain bias approaches the BV, given by
Q N , S S J , t o t a l = Q P , S J + Q C , S I P O S
When both the N-pillar and P-pillar are simultaneously depleted, and the E-field at junction JSJ reaches ECU, indicating breakdown in the case of a uniform E-field distribution as
Q   P , S J = q N D , S J W N = q N A , S J W P = 2 ε S i E C U
where ND,SJ represents the equivalent doping concentration for depleting the P-pillar within the N-pillar. QSIPOS,C denotes the charge of the equivalent plate capacitor for the Si/oxide/SIPOS structure, equating to the partial charge with the equivalent doping concentration of ND,SJ in the N-pillar as
Q C , S I P O S = Δ V ε S i L D / t O X = q N D , S J W N L D
where ΔV represents the potential difference across the thin oxide layers between the SIPOS pillar and the N-pillar. εOX and εSi denote the permittivity of the oxide and Silicon. tOX is the oxide thickness. The total doping concentration of the N-pillar due to SIPOS modulation of SSJ-UMOS structure can be obtained as
N D , S S J = N D , S J + N D , S J = ε S i ( 2 t O X E C U + Δ V ) / q W N t O X

2.2. Electric Field of SIPOS Modulated Drift Region

Assuming a reverse bias VR is applied, and the drift region is fully depleted, the electrostatic potential ϕ must satisfy the following Poisson equation with appropriate boundary conditions [20].
2 ϕ = 2 ϕ ( x , y ) x 2 + 2 ϕ ( x , y ) y 2 = χ ε S , 0 y L D
χ = q N D , t o t a l ,   ε = ε S i   when   W N / 2 x W N / 2 χ = 0 , ε = ε o x   when   W N / 2   < x t O X + W N / 2
Considering strong coupling and electric displacement continuity at the semiconductor–dielectric interface, appropriate boundary conditions in the y-direction can be established as
ϕ ( x , y ) x x = 0 = ϕ ( 0 , y ) x = E ( 0 , y ) ,   E ( 0 , y ) = E L ϕ ( x , y ) x x = W 2 = E ( W N 2 , y ) ,   E ( W N 2 , y ) = E Si-OX , S S J + E L , S S J
where E (0, y) represents the vertical E-field along the dotted line A-A′ (x = 0, Figure 2), where the lateral E-field component is zero. E L represents the vertical potential E-field component generated under the drain bias of VR. At position x = WN/2, the E-field comprises the vertical potential E-field component E L , S S J and the lateral plate capacitive potential E-field component E Si-OX , S S J , expressed as
ε S i E Si-OX , S S J = ε O X E O X = ε O X Δ V / t O X E Si-OX , S S J = α E C U ,   ( 0 < α < 1 ) E L , S S J = β E C U ,   ( 0 < β < 1 )  
where ΔV is the potential difference across the thin oxide layers, between the voltage on the N-pillar ϕ S i ( y ) and the voltage on the SIPOS pillar ψ SIPOS ( y ) . α and β are coefficients of SSJ-UMOS with values between 0 and 1. The potential in the SIPOS layer is assumed to be linearly distributed in the drift region based on the ohmic behavior of the SIPOS layer as
Δ V = ϕ S i ( y ) ψ S I P O S ( y )   , ψ S I P O S ( y ) = V D ( y / L D ) ϕ S i ( y = 0 ) = 0   , ϕ S i ( y = L D ) = V D
The potential function is approximated by a second-order Taylor expansion formula. By solving the 2-D Poisson’s equations with the boundary conditions (6)–(8), a general differential equation for the potential distribution function in the N-pillar drift region is obtained as
2 ϕ ( 0 , y ) d y 2 ϕ ( 0 , y ) T S 2 = q N e f f ε S i , 0 y L D
where Ts is expressed as
T S = W N 2 ( W N 4 + ε S i ε O X t O X )
Neff is the effective doping concentration of the N-drift region. Solving (11) with constraints (8)–(10) gives the potential distributions in the N-pillar as
ϕ ( x , y ) = [ 1 x 2 2 T S ] [ q N e f f T S 2 ε S i q N e f f T S 2 ε S i sinh ( y T S ) + sinh ( L D y T S ) sinh ( L D T S ) + V D sinh ( y T S ) sinh ( L D T S ) ]
In the scenario where the E-field extends through the entire length of the drift region, the magnitude of the E-field in the y-direction E(y) along the middle line of the N-drift region is given by
E ( 0 , y ) = V D T S cosh ( y T S ) sinh ( L D T S ) + q N e f f T S ε S i cosh ( L D y T S ) sinh ( L D T S ) cosh ( y T S ) sinh ( L D T S )
For the SSJ-UMOS structure with Neff = ND,SSJ (5), ESSJ (y) is expressed as
E S S J ( y ) = Δ V + 2 E C U t O X W N t O X T S e y / T S , S J + ( V D T S Δ V + 2 E C U t O X W N t O X T S ) e ( y L D ) / T S
Combining (9) an optimum expression for TS can be derived under the criterion that the E-field at the junction JSJ and at the bottom of the trench are equal at the breakdown, for the condition as
E ( y = 0 ) = E ( y = L D ) = E C U E L , S S J 2 + E Si-OX , S S J 2 = E C U
The BV of SSJ-UMOS is expressed as
B V = λ E C U L D ,   0 < λ < 1
where λ is a coefficient with values between 0 and 1. Combined with the solution of (11), (14), and (16), the optimum TS,OP is given by
T S , O P = ε S i B V 2 q N e f f
Utilizing Equations (5), (12), and (18), we determine the optimal oxide thickness tOX,OP for SIPOS SJ-UMOS as
t O X ,   O P = ε O X ε S i [ B V ( 2 + α ε S i / ε O X ) E C U W N 4 ]

2.3. Figure of Merit BV-RON,sp Model for SSJ-UMOS

Combining the SJ and MIS structures enables the SSJ-UMOS to achieve ultra-low RON,sp. The total drift region resistance is analyzed in two components: one from the highly doped N-pillar drift region and the other from the carrier accumulation layer due to positive gate bias on the MIS structure SIPOS/oxide/Si. The RSJ,sp contributed by the N-pillar drift region is expressed as
R S J , s p = ρ L D W C e l l W N = 1 q μ N N e f f L D W C e l l W N
where WCell is half the width of the cell (WN + WP + WI). ρ is the resistivity of the N-pillar drift region. μN is the electron mobility. When (5) and (20) are combined, the RSJ,sp contributed by the N-pillar in SSJ-UMOS is expressed as
R S J , s p = W C e l l L D μ N ε S i ( 2 t O X E C U + Δ V / t O X )
The schematic cross-section illustrates the SIPOS pillar modulated SJ drift region and the carrier accumulation layer along the trench surface in the N-pillar drift region. Due to the uniform resistivity of the SIPOS layer, the voltage across the SIPOS at position y is denoted as V(y)
V ( y ) = [ ( V D V G ) / L D ] y + V G
The specific resistance RA,sp of the accumulation layer is obtained by integrating the dRA,sp, is expressed as
R A , S P = 0 L D W C e l l μ N C O X ( V ( y ) V t h )   d y
In the ON state, the threshold voltage (Vth) signifies the initiation of the accumulation layer formation. Substituting (22) into (23), we obtain the integrated result for RA,sp as
R A , S P = ln ( V D V t h ) ln ( V G V t h ) V D V G W C e l l , S J μ N C O X L D  
As the total RON,sp contributed by the drift region and the accumulation layer is in parallel, the overall RON,sp,SSJ for the SSJ-UMOS comprises two components, RSJ,sp and RA,sp as
R O N , s p , S S J = R S J , s p | | R A , s p
Combining (21), (24) and (25), the RON,sp,SSJ is obtained as
R O N , s p , S S J = W C e l l M L D μ N C O X + ε S i M ( 2 t O X E C U + Δ V / t O X ) M = ln ( V D V t h ) ln ( V G V t h ) V D V G
When applying Baliga’s formula for the impact ionization coefficient, αSi, to a two-dimensional charge-coupling silicon device, as referenced in [19], we derive an expression for the critical electric field in scenarios characterized by a uniform electric field as
0 L D α Si   d x = 1 ,   α Si = 3.51 × 10 35 E C U 7 E C U = 8.36 × 10 4 L D 1 / 7
When (9), (17), (26), and (27) are combined, the RON,sp,SSJ is given by
R O N , s p , S S J = W C e l l M μ N C O X + ε S i M E C U ( 2 t O X + α ε S i / ε O X ) B V 7 / 6 5.53 × 10 5 λ 7 / 6
The mobility μN is influenced by the silicon-oxide interface property. In practical processes, the SSJ-UMOS resistance is increased due to side-wall mobility degradation. The RON,sp,SSJ surpasses the superjunction UMOS Silicon limit mentioned in Ref. [19], which is given by
R O N , s p ( Ideal   SJ ) = 3.27 × 10 12 B V 4 / 3 W N ε S μ N

2.4. Hyperparameters Optimization Based on Gaussian Process Regression Model

Figure 1b illustrates a phased approach for optimizing hyperparameters (α, β, λ) using Gaussian processes. Figure 2 shows the schematic representation of the GPR. Following device model establishment, we analyze the electrical mechanism and conducted Sentaurus TCAD simulations to generate a dataset containing 1000 samples. Subsequently, GPR is applied to construct a FOM = BV2/RON,sp prediction model and identify optimal hyperparameters. Structural parameters such as LD, ND, tOX, WN, closely linked to FOM, are considered during hyperparameter optimization. GPR, a non-parametric Bayesian regression method, assumes the target variable FOM follows a multivariate Gaussian distribution, avoiding specific assumptions about the fitting function F and treating FOM at any data point x as a random variable. Combining (16), (27) and (28), the FOM calculation formula is the target formula to be optimized for the GPR model, expressed as
F O M = B V 2 R O N , s p , S S J = 6.99 × 10 9 μ N λ 2 L D 5 / 7 C O X + M t O X [ q W N N D , S S J + α E C U ε S i 2 ε O X ( 1 t O X 1 ) ] W C e l l M , α 2 + β 2   1
After establishing the device model, TCAD simulations are employed to generate device data for different combinations of LD, ND,SSJ, tOX, WN. Subsequent data processing leads to the dataset as
D = { ( L D i , N D , S S J i , t o x i , W N i , F O M i ) } i = 1 N
where LDi, NDi, tOXi, WNi denote the features of the i-th data point, corresponding to the target value FOMi, representing the FOM of the i-th device.
The mean function m(x) represents the average behavior of the target value FOM given the features LD, ND,SSJ, tOX, WN. The covariance kernel function k (x, x′) represents the correlation between different data points x and x′ in the feature space as
F O M ~ N ( m ( x ) , k ( x , x ) )
We then define the likelihood function based on the derived (32) to express the probability of observing the data given the parameters α, β, λ. In GPR, the likelihood function is represented using a Gaussian distribution and expressed as
L ( α , β , γ ) = P ( α , β , γ ) = i = 1 N P ( F O M i | L D i , N D i , t O X i , W N i , α , β , λ )
For each data point, we employ a multivariate Gaussian distribution as the probability distribution, calculating the mean and variance from the dataset. The likelihood function is obtained through maximum likelihood estimation, and a gradient descent optimization algorithm is applied to optimize the three hyperparameters α, β, and λ resulting in the final values αbest, βbest, and λbest.

3. Results and Discussion

3.1. Off-State Characteristics

Numerical results obtained through TCAD simulations and analytical results from the model are compared. To validate the model, simulation results are calibrated to breakdown characteristic (ID-VD) data extracted from fabricated SJ-VDMOS [21], as depicted in Figure 3a. The TCAD simulation results, with a single set of self-consistent parameters, align well with experimental data. Additionally, the OFF state characteristics of SJ-UMOS and SSJ-UMOS are illustrated in Figure 3a. As the resistivity of the SIPOS layer equals 1.0 × 1010 Ω·cm, the leakage current of SSJ-UMOS increases from 10−12 to 10−10 A due to the SIPOS field plate acting as a high-resistor parallel to the drift region. In the OFF state, there is a uniform potential difference (ΔV) between the SIPOS layer and the vertical surface of the N-drift region for and SSJ-UMOS, as shown in Figure 3b.
Figure 4a shows the optimum effective doping concentration (Neff) predicted by expressions (5), (18), and (19) as a function of the WN with the BV as a parameter. Notably, the optimum dose decreases with increasing WN. SSJ-UMOS exhibits a higher optimum Neff than SJ-UMOS, attributed to the enhanced charge coupling effect of SIPOS pillars. In Figure 4b, the dependence of BV and RON,sp on ND for SSJ-UMOS and SJ-UMOS is illustrated. In SSJ-UMOS, SIPOS-assisted depletion of N-pillars reduces RON,sp and increases BV. Compared to SJ-UMOS, the BV of SSJ-UMOS decreases gradually when doping concentration is imbalanced, owing to the E-field modulation of SIPOS pillars.

3.2. Gaussian Process Regression

The Gaussian process regression model exhibits exceptional performance in this study. Key evaluation metrics, as shown in Table 1, include a mean squared error (MSE) of 953.56, a root mean squared error (RMSE) of 30.88, and a mean absolute percentage error (MAPE) of only 4.5%. These metrics unequivocally attest to the model’s exceptional predictive accuracy.
These results highlight the Gaussian process regression model’s reliability in fitting and prediction, underscoring the crucial role of parameter optimization in enhancing model performance. We utilized visual representations to showcase the model’s performance. In Figure 5a, a confidence interval plot illustrates the model’s precision in predicting the target variable and the associated uncertainty. The model demonstrates low uncertainty, indicating high reliability in predictions, especially near the forecasted values. Figure 5b presents the results of parameter sensitivity analysis, revealing optimal hyperparameters: α = 0.8503, β = 0.5261, and λ = 0.7837. Notably, α significantly influences fitting results, highlighting its sensitivity. This insight provides valuable guidance for further parameter optimization, with the potential to improve both fitting quality and predictive accuracy.
Analytical expression (15) is applicable in SSJ-UMOS with modifications to Neff based on Equations (5) and (7). In Figure 6a,b, numerical and analytical profiles of vertical E-field and potential for SSJ-UMOS and SJ-UMOS in the middle of the N-pillar along the y-direction (A-A’, Figure 1a) are presented. In comparison to SJ-UMOS without the SIPOS layer, the high E-field peak (EPK) at the gate trench bottom is reduced and BV is improved from 607 V to 725 V. Analytical results for SSJ-UMOS align with numerical results for various TOX values. Optimizing the oxide layer thickness (TOX = 0.05 μm) in SSJ UMOS effectively enhances device performance.
Figure 7a,b present the optimum oxide thicknesses and N-pillar width for SSJ-UMOS with various breakdown voltages, as predicted by the analytical model (18) and (19). The trench oxide thickness increases for devices with larger blocking voltages, staying within practical limits for device processing and fabrication. For a breakdown voltage of 1000 V, the optimal trench oxide thickness is 0.05 μm with a mesa width of 1.0 μm for SSJ-UMOS, aligning with the obtained numerical results.

3.3. ON State and Dynamic CHARACTERISTIC

Figure 8a displays electron current density distributions in the drift region and output characteristics of SSJ-UMOS and SJ-UMOS. The threshold voltage Vth of the two devices are about 1.2 V. In SSJ-UMOS, drift region resistance (RD) is the parallel connection of the accumulation layer resistance (RA). The maximum electron current density of SSJ UMOS reaches 8.23 × 104 A/cm2, significantly higher than that of SJ UMOS. At a high drain voltage, the second term M in (26) becomes dominant, leading to a strong dependence on ΔVG = VDVG as shown in Figure 8b. Additionally, reducing the pitch Wcell can decrease RON,sp,SSJ.
Figure 9a presents a dynamic performance comparison between SIPOS SJ-UMOS and the conventional SJ-UMOS. The SIPOS pillars increase gate capacitance, generating a surface deep-depletion layer in the drift region in the OFF state, leading to switching delays in SIPOS SJ-UMOS. The turn-on speed is comparable between the two devices, while the turn-off speed of SIPOS SJ-UMOS is slower than that of the conventional model. Nonetheless, MOSFETs with SIPOS terminations have demonstrated resilience under harsh conditions, such as a gradient of 10 kV/μs. In Figure 9b, a comparison of the RON,sp and BV relationships is presented for the three structures, including references [2,3,17,21,22,23,24,25]. Optimum tOX, WN, LD, and ND values for SSJ-UMOS and S-UMOS are chosen for this analysis. For the RON,sp analysis of SSJ-UMOS, VDS is set to 10 V at VGS of 5 V. The plot in Figure 9b clearly indicates that the SSJ-UMOS structure outperforms other structures, surpassing the SJ silicon limit [19].

4. Conclusions

This paper introduces a machine learning-based figure of merit model of SSJ-UMOS featuring a modulated drift region utilizing SIPOS pillars. The tradeoff characteristics between BV and RON,sp have been theoretically derived, breaking the SJ Silicon limit by applying three methods for the additional E-field modulation effect, charge coupling effect and majority carrier accumulation, simultaneously. In the analytical model, the optimal structure parameters of the drift region, oxide thickness, and E-field modulation coefficients are also discussed in the analytical model. GPR is employed for an accurate figure of merit prediction and hyperparameter optimization, which can give guidance for the design of power MOSFETs with SIPOS. The proposed model’s validity is robustly confirmed through comprehensive verification against TCAD simulation results.

Author Contributions

Methodology, Z.C.; resources, Q.S.; writing—original draft preparation, Z.C., Q.S. and C.M.; writing—review and editing, Z.C., Q.S. and C.M.; supervision, B.H. and L.J.; project administration, Z.C., B.H. and L.J. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported in part by the National Natural Science Foundation of China under Grant No. 62104176 and 62171347, in part by the Fundamental Research Funds for the Central Universities under Grant No. XJSJ23083, in part by the Proof of Concept Foundation of Xidian University Hangzhou Institute of Technology under Grant No. GNYZ2023XJ0409-1, in part by the Shaanxi Higher Education Teaching Reform Research Project under Grant No. 23ZZ014, and in part by the China Postdoctoral Science Foundation under Grant No. 2019M663637.

Data Availability Statement

The original contributions presented in the study are included in the article, further inquiries can be directed to the corresponding author.

Conflicts of Interest

The authors declare no conflicts of interest.

References

  1. Udrea, F.; Deboy, G.; Fujihira, T. Superjunction power devices, history, development, and future prospects. IEEE Trans. Electron Devices 2017, 64, 713–727. [Google Scholar] [CrossRef]
  2. Wu, L.; Chen, X.; Zeng, J. Novel accumulation mode superjunction device with extended superjunction gate. IEEE Trans. Electron Devices 2022, 69, 2560–2565. [Google Scholar] [CrossRef]
  3. Duan, B.; Wang, Y.; Sun, L. Accumulation-mode device: New power MOSFET breaking superjunction silicon limit by simulation study. IEEE Trans. Electron Devices 2020, 67, 1085–1089. [Google Scholar] [CrossRef]
  4. Saito, W. Breakthrough of drain current capability and on-resistance limits by gate-connected superjunction MOSFET. In Proceedings of the 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), Chicago, IL, USA, 13–17 May 2018; IEEE: Piscataway, NJ, USA, 2018; pp. 36–39. [Google Scholar]
  5. Williams, R.K.; Darwish, M.N.; Blanchard, R.A. The trench power MOSFET: Part I—History, technology, and prospects. IEEE Trans. Electron Devices 2017, 64, 674–691. [Google Scholar] [CrossRef]
  6. Luo, X.; Jiang, Y.H.; Zhou, K. Ultralow specific on-resistance superjunction vertical DMOS with high-K dielectric pillar. IEEE Electron Device Lett. 2012, 33, 1042–1044. [Google Scholar] [CrossRef]
  7. Guo, Y.; Yao, J.; Zhang, B. Variation of lateral width technique in SoI high-voltage lateral double-diffused metal–oxide–semiconductor transistors using high-k dielectric. IEEE Electron Device Lett. 2015, 36, 262–264. [Google Scholar] [CrossRef]
  8. Cao, Z.; Wang, Q.; Jiao, L. Analytical study on a 700 V triple RESURF LDMOS with a variable high-K dielectric trench. IEEE Trans. Electron Devices 2021, 68, 2872–2878. [Google Scholar] [CrossRef]
  9. Cao, Z.; Duan, B.; Shi, T. A superjunction U-MOSFET with SIPOS pillar breaking superjunction silicon limit by TCAD simulation study. IEEE Electron Device Lett. 2017, 38, 794–797. [Google Scholar] [CrossRef]
  10. Li, X.; Wu, Z.; Rzepa, G.; Karner, M.; Xu, H.; Wu, Z.; Wang, W.; Yang, G.; Luo, Q.; Wang, L.; et al. Overview of Emerging Semiconductor Device Model Methodologies: From Device Physics to Machine Learning Engines. Fundam. Res. 2024. [Google Scholar] [CrossRef]
  11. Ghoshhajra, R.; Biswas, K.; Sarkar, A. A review on machine learning approaches for predicting the effect of device parameters on performance of nanoscale MOSFETs. In Proceedings of the 2021 Devices for Integrated Circuit (DevIC), Kalyani, India, 19–20 May 2021; pp. 489–493. [Google Scholar]
  12. Klemme, F.; Prinz, J.; Van Santen, V.M. Modeling emerging technologies using machine learning: Challenges and opportunities. In Proceedings of the 39th International Conference on Computer-Aided Design, Online, 2–5 November 2020; pp. 1–9. [Google Scholar]
  13. Wang, J.; Kim, Y.H.; Ryu, J. Artificial neural network-based compact modeling methodology for advanced transistors. IEEE Trans. Electron Devices 2021, 68, 1318–1325. [Google Scholar] [CrossRef]
  14. Xu, C.; Liu, Y.; Liao, X. Machine Learning Regression-Based Single-Event Transient Modeling Method for Circuit-Level Simulation. IEEE Trans. Electron Devices 2021, 68, 5758–5764. [Google Scholar] [CrossRef]
  15. Zhang, L.; Chan, M. Artificial neural network design for compact modeling of generic transistors. J. Comput. Electron. 2017, 16, 825–832. [Google Scholar] [CrossRef]
  16. Mehta, K.; Wong, H.Y. Prediction of FinFET current-voltage and capacitance-voltage curves using machine learning with autoencoder. IEEE Electron Device Lett. 2020, 42, 136–139. [Google Scholar] [CrossRef]
  17. Zhang, W.; Zhang, B.; Li, Z. Theory of superjunction with NFD and FD modes based on normalized breakdown voltage. IEEE Trans. Electron Devices 2015, 62, 4114–4120. [Google Scholar] [CrossRef]
  18. Fujihira, T. Theory of semiconductor superjunction devices. Jpn. J. Appl. Phys. 1997, 36, 6254. [Google Scholar] [CrossRef]
  19. Baliga, B.J. Advanced Power MOSFET Concepts; Springer Science & Business Media: Berlin/Heidelberg, Germany, 2010. [Google Scholar]
  20. Zhou, J.; Huang, C.F.; Cheng, C.H. A comprehensive analytical study of dielectric modulated drift regions—Part I: Static characteristics. IEEE Trans. Electron Devices 2016, 63, 2255–2260. [Google Scholar] [CrossRef]
  21. Ye, Z.Y.; Liu, L.; Yao, Y. Fabrication of a 650V superjunction MOSFET with built-in MOS-channel diode for fast reverse recovery. IEEE Electron Device Lett. 2019, 40, 1159–1162. [Google Scholar] [CrossRef]
  22. Saito, W.; Omura, I.; Aida, S. A 15.5 m Ω cm2-680V Superjunction MOSFET Reduced On-Resistance by Lateral Pitch Narrowing. In Proceedings of the 2006 IEEE International Symposium on Power Semiconductor Devices and IC’s, Naples, Italy, 4–8 June 2006; IEEE: Piscataway, NJ, USA, 2006; pp. 1–4. [Google Scholar]
  23. Kushwaha, P.K.; Nautiyal, P.; Gupta, A. An improved SJ UMOS with modified gate electrode to reduce gate charge. In Proceedings of the 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference (IEMECON), Jaipur, India, 13–15 March 2019; IEEE: Piscataway, NJ, USA, 2019; pp. 81–84. [Google Scholar]
  24. Shibata, T.; Noda, Y.; Yamauchi, S. 200V trench filling type super junction MOSFET with orthogonal gate structure. In Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC’s, Jeju, Republic of Korea, 27–31 May 2007; IEEE: Piscataway, NJ, USA, 2007; pp. 37–40. [Google Scholar]
  25. Lin, Z.; Huang, H.; Chen, X. An improved superjunction structure with variation vertical doping profile. IEEE Trans. Electron Devices 2014, 62, 228–231. [Google Scholar] [CrossRef]
Figure 1. (a) Schematic cross-sectional view of SSJ-UMOS, (b) machine learning-based modeling methods.
Figure 1. (a) Schematic cross-sectional view of SSJ-UMOS, (b) machine learning-based modeling methods.
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Figure 2. Schematic representation of the Gaussian process regression model.
Figure 2. Schematic representation of the Gaussian process regression model.
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Figure 3. (a) Reverse leakage current versus VDS of SSJ-UMOS, SJ-UMOS, and simulation results calibrated to breakdown characteristics (IDS-VDS) data from the fabricated SJ-VDMOS [21]. (b) Electric potential difference (ΔV) between the drift region and the SIPOS pillar of SSJ-UMOS.
Figure 3. (a) Reverse leakage current versus VDS of SSJ-UMOS, SJ-UMOS, and simulation results calibrated to breakdown characteristics (IDS-VDS) data from the fabricated SJ-VDMOS [21]. (b) Electric potential difference (ΔV) between the drift region and the SIPOS pillar of SSJ-UMOS.
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Figure 4. (a) Optimum doping concentration for two-dimensional charge-coupling, and (b) dependence of BV and RON,sp on ND for SSJ-UMOS and SJ-UMOS.
Figure 4. (a) Optimum doping concentration for two-dimensional charge-coupling, and (b) dependence of BV and RON,sp on ND for SSJ-UMOS and SJ-UMOS.
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Figure 5. (a) Fitting performance of Gaussian process regression model on FOM. (b) Hyperparameter sensitivity analysis of α, β and λ.
Figure 5. (a) Fitting performance of Gaussian process regression model on FOM. (b) Hyperparameter sensitivity analysis of α, β and λ.
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Figure 6. Simulated and analytical (a) E-field, and (b) potential distributions of SIPOS SJ UMOS and SIPOS UMOS (along the line A-A’).
Figure 6. Simulated and analytical (a) E-field, and (b) potential distributions of SIPOS SJ UMOS and SIPOS UMOS (along the line A-A’).
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Figure 7. Optimum (a) oxide thickness tOX and (b) N-pillar width WN for SSJ UMOS.
Figure 7. Optimum (a) oxide thickness tOX and (b) N-pillar width WN for SSJ UMOS.
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Figure 8. (a) Electron current density distribution and output characteristics for SSJ-UMOS and SJ-UMOS. (b) Simulated and analytical RON,sp,SSJ at the different ΔVG and WCell for the SSJ-UMOS.
Figure 8. (a) Electron current density distribution and output characteristics for SSJ-UMOS and SJ-UMOS. (b) Simulated and analytical RON,sp,SSJ at the different ΔVG and WCell for the SSJ-UMOS.
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Figure 9. (a) Switching waves of SIPOS SJ-UMOS and the conventional SJ-UMOS at the same VDD = 100 V. (b) Comparison of theoretical predictions of RON,sp versus BV relationship of SSJ-UMOS, SJ-UMOS and other published devices with the ideal silicon limit and the SJ silicon limit line in the BV range of 10–1000 V.
Figure 9. (a) Switching waves of SIPOS SJ-UMOS and the conventional SJ-UMOS at the same VDD = 100 V. (b) Comparison of theoretical predictions of RON,sp versus BV relationship of SSJ-UMOS, SJ-UMOS and other published devices with the ideal silicon limit and the SJ silicon limit line in the BV range of 10–1000 V.
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Table 1. Model Fitting Evaluation Metrics.
Table 1. Model Fitting Evaluation Metrics.
Evaluation MetricMetric Value
MSE953.56
RMSE30.88
MAPE4.5%
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MDPI and ACS Style

Cao, Z.; Sun, Q.; Ma, C.; Hou, B.; Jiao, L. Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET. Micromachines 2024, 15, 411. https://doi.org/10.3390/mi15030411

AMA Style

Cao Z, Sun Q, Ma C, Hou B, Jiao L. Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET. Micromachines. 2024; 15(3):411. https://doi.org/10.3390/mi15030411

Chicago/Turabian Style

Cao, Zhen, Qi Sun, Chuanfeng Ma, Biao Hou, and Licheng Jiao. 2024. "Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET" Micromachines 15, no. 3: 411. https://doi.org/10.3390/mi15030411

APA Style

Cao, Z., Sun, Q., Ma, C., Hou, B., & Jiao, L. (2024). Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET. Micromachines, 15(3), 411. https://doi.org/10.3390/mi15030411

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