Synchronization of Analog-Discrete Chaotic Systems for Wireless Sensor Network Design

Abstract

The current work is focused on studying the performance of the Pecora–Carroll synchronization technique to achieve synchronization between the analog and discrete chaos oscillators. The importance of this study is supported by the growing applications of chaotic systems for improving the security of data transmission in various communication layers, primarily on the physical layer. The hybrid analog-discrete approach of implementing chaos oscillators opens new possible communication schemes for wireless sensor network (WSN) applications. The analog implementation of chaos oscillators can benefit the simpler sensor node (SN) integration, while the discrete implementation can be used on the gateway. However, the core of such chaos-based communications is synchronizing analog and discrete chaos oscillators. This work studies two key parameters of analog-discrete chaotic synchronization: chaotic synchronization noise immunity and synchronization speed. The noise immunity study demonstrates the quality of synchronization at various noise levels, while the synchronization speed demonstrates how quickly the analog-discrete synchronization is achieved, along with how quickly the two systems diverge when synchronization is no longer present. The two studies use both simulation-based and hardware-based approaches. In the simulation case, the analog oscillator’s circuit is modeled in LTspice XVII, while in the hardware case, the circuit is implemented on the PCB. In both simulation and hardware studies, the discrete model of the oscillator is implemented in MATLAB R2023b. The studies are performed for two pairs of different chaos oscillators to widen the proposed approach application potential: the Vilnius and RC chaos oscillators. The oscillators have been selected due to their simplicity and similar dynamic behavior for model-based and electrical circuit implementation. The proposed approach also allows us to compare the synchronization of different oscillators in the analog-discrete implementation.

1. Introduction

The previous decade has seen the rapid growth of wireless smart IoT devices, contributing to the expansion of WSN and its integration to various levels of the industry. The Ericsson mobility report [1] forecasts that the number of IoT devices will exceed 16 billion in 2024 and surpass 38 billion by 2029. Such tight integration of wireless devices poses a security challenge. Data transmission security has received considerable attention on the higher layers, with the focus taking directions such as encryption [2], Blockchain technology [3], and fog computing [4]. However, the lowest level, hardware, has received less attention, with the main security measure being the challenges in detecting the transmitted signal.

The new direction in developing communication systems with increased hardware layer security began with the development of chaos theory. Chaotic systems are known for their sensitivity to the initial conditions and the noise-like signal waveforms. The more widely studied applications of chaotic systems include the development of new encryption schemes [5,6] and random number generators [7,8].

Another emerging application of chaos is its integration into communication by using the signals of chaotic sources to carry information. These systems can be classified as coherent and non-coherent. Due to the sensitivity to initial conditions, the identical chaos sources are asynchronous. Two coherent chaos-based systems require chaotic synchronization as they use the chaos waveform to detect the received information signal [9,10]. The non-coherent chaotic systems do not require such synchronization, as the detection is conducted using the signal level [11] or using the delay, like in the differential chaos shift-keying (DCSK) case [12]. The non-coherent systems are simpler in implementation and have better noise immunity, but the coherent systems are more secure due to the presence of chaotic synchronization driven by the transmitting part. This development in chaos-based communication systems is not exclusive to IoT systems and includes radar communication applications [13,14].

The various approaches to generating chaotic signals are divided into analog and discrete. The analog techniques mainly consist of continuous-time generators that exhibit chaotic behavior. Circuits like [15,16], known as chaos oscillators or chaos generators, are specially designed for this purpose. Other circuits, like DC-DC converters [17], are not intended to generate chaotic signals yet can act as chaos sources under specific parameters. The discrete approaches mainly consist of chaotic maps—nonlinear functions that exhibit chaotic behavior. Another discrete approach is the digital implementation of chaotic circuits [18]. Chaotic oscillators are classically implemented as analog circuits using such elements as diodes, capacitors, coils, transistors, resistances, and operational amplifiers, which can ensure a cheap and simple source of chaos. Digital implementations of chaotic circuits are relatively novel, and have rapidly emerged in recent years. In many applications, those can provide significant advantages over analog circuits, such as determined behavior, control over the system’s initial conditions, and lack of instabilities caused by the performance fluctuations and finite nominal tolerances of analog components.

Previously, the proposed chaos-based communication systems used a single type of chaos source: a pair of chaos oscillators or chaotic maps. This approach is sufficient for a case of a small number of devices, but for developing a WSN, a more elaborate solution is desirable. This work proposes a hybrid analog-digital chaos approach for a star-topology WSN. Figure 1 introduces the WSN communication system’s design that utilizes the analog chaos oscillator circuits in the individual SNs, and the discrete model of the chaos oscillator implemented as an FPGA or microprocessor-based embedded circuit in the gateway device. Chaos oscillators are simple analog circuits that are a cost-effective solution for implementing multiple SNs. The discrete implementation of the chaos oscillator in the gateway device is a more versatile approach since several discrete models can be implemented in a single chip and can synchronize and exchange information with multiple SNs using chaotic waveforms. The embedded implementation of the gateway also contributes to the security of information transfer.

The most critical part of the given design is the ability of the discrete chaos oscillator to synchronize with the analog chaos oscillator and vice-versa. In terms of chaotic synchronization, two main techniques are commonly used. The first one is the Pecora–Carroll procedure [19], where synchronization is achieved by substituting the state variable of one chaotic system with the state variable of the other chaotic system. The second technique is error feedback control [20], where the difference of asynchronous chaos signals is used to adjust the state of one chaotic system. Several works [21,22,23,24] have explored the approaches for chaos oscillators’ synchronization. The Pecora–Carroll technique is simpler in implementation but requires one state variable of the chaotic system to act as a synchronization signal. The error feedback is more elaborate in implementation, but the synchronization signal is not limited to only ensuring synchronization.

The attention towards synchronizing an analog chaos oscillator to its discrete counterpart and vice versa has received more attention in recent years. Two studies [25,26] explored only the discrete-analog synchronization of Rossler chaos oscillator. The current work studies the performance of analog-discrete and discrete-analog chaotic synchronization using the Pecora–Carroll technique for the Vilnius and RC chaos oscillators. The first study explores the quality of analog-discrete and discrete-analog synchronization in noisy conditions. As synchronization is applied in wireless data transmission, the question of synchronization’s noise immunity is relevant and is commonly explored for chaos-based communications [27,28]. The second study explores the speed of analog-discrete and discrete-analog synchronization and desynchronization. This study is necessary to understand the time required for synchronization to occur and the time for the chaos oscillator to diverge.

This work has multiple novelty points. First, the Vilnius [29] and RC [30] chaos oscillators were not widely explored regarding analog-discrete model development and synchronization. The second is that the two studies have simulation-based and experimental approaches. The simulation approach uses LTspice to model the behavior of the analog chaos oscillator, while the experimental approach uses the hardware prototype of the oscillator implemented in PCB. This allows for comparing the behavior of the LTspice and hardware models. The third novelty point is the synchronization and desynchronization speed study. To the best of the author’s knowledge, the given direction was generally overlooked, especially in the discrete-analog and analog-discrete cases, with one prime work being [31]. The results of this work open wide possibilities for the further development of chaos-based communication systems, making the proposed chaos-based WSN system possible, considering the previously developed chaos-based communication systems by the research group [32,33,34].

The paper is organized as follows: Section 2 describes the chaos oscillators used in this work, their discrete and LTspice models, as well as the hardware prototype. Section 3 presents the study on the performance of Pecora–Carroll analog-discrete and discrete-analog synchronization noise immunity. The section details the implementation of the study and analyzes the acquired results. Section 4 presents the study on the performance of Pecora–Carroll analog-discrete and discrete-analog synchronization and desynchronization time, elaborating on the experiment setup and analyzing the acquired results. The final section discusses the results of the two studies and their future impact on the development of chaos-based communication systems and concludes the work.

2. Chaos Oscillators, Discrete Models and Chaotic Synchronization

This section is devoted to chaos oscillators used in the study. The section presents the circuits of chaos oscillators with their respective mathematical models describing the dynamics; these models are used to derive the discrete representation of the circuit. The given chaos oscillators are also implemented in LTspice to simulate the work of the analog circuit; the hardware circuit is developed as well. The work uses three different realizations of the oscillators; hence, the phase portraits (attractor projections) are compared to demonstrate the similarity of behavior. Finally, the section elaborates on the Pecora–Carroll synchronization technique applied to achieve analog-discrete and discrete-analog synchronization of the oscillators. These specific oscillators were chosen due to the similarity of behavior in different realizations.

2.1. RC Chaos Oscillators

The first chaos oscillator for this work is the “RC chaos oscillator” [30]. The circuit diagram, LTspice model, and fabricated prototype of this oscillator are shown in Figure 2.

The dynamics of the circuit are described with a system of differential equations in (1). The state variables are voltages across the capacitors $C_1$, $C_2$, and $C_3$.

$$\{\begin{array}{l}\frac{dx}{dt}=-x+\left(k_1-1\right)·y-\left(k_1-1\right)·z,\\ \frac{dy}{dt}=-x+\left(k_1-2\right)·y-\left(k_1-1\right)·z,\\ \frac{dz}{dt}=y{k}_1+\left(k_1+\alpha \right)·z+\beta ·\left(z-1\right)·H(z-1).\end{array}$$

(1)

$$\begin{array}{cccccccc}x=\frac{v_{C_1}}{v*},& y=\frac{v_{C_2}}{v*},& z=\frac{v_{C_3}}{v*},& v*=\frac{v_0}{\left(k_2-1\right)},& \alpha =\frac{R}{R_6},& \beta =\frac{R}{R_8},& k_1=\frac{R_3}{R_4}+1,& k_2=\frac{R_7}{R_8}+1,\end{array}$$

(2)

where $v_{C_1}$, $v_{C_2}$, and $v_{C_3}$ are voltages across the capacitors $C_1$, $C_2$, and $C_3$, respectively; $v_0$—voltage across the diode $D_1$; $k_1$—gain of the operational amplifier $O{A}_1$; $k_2$—gain of the operational amplifier $O{A}_2$; $H()$—Heaviside function. The elements have the following values: $R=R_1=R_2=$ 11 kΩ; $R_3=$ 9.1 kΩ; $R_4=$ 2 kΩ; $R_5=R_7=$ 2.7 kΩ; $R_6=$ 1.1 kΩ; $R_8=$ 780 Ω; $C=C_1=C_2=C_3=$ 1.3 nF. The implemented prototype in Figure 2b uses the 1N4148 diode and TL082 operational amplifiers. These are general off-the shelf components, as the circuit has no specific criteria for these elements.

The system (1) describes the dynamics of the oscillator in continuous time (the analog circuit). In this case, the fundamental frequency of oscillations is defined by the time constant $\tau$(4). The discrete model of the oscillator would represent the digital circuit that exhibits similar behavior as its analog counterpart. To derive a discrete model of the oscillator, several modifications to (1) must be made. First, the differentiation is taken over θ, which is the time t scaled by the time constant τ.

$$\{\begin{array}{l}\frac{dx}{d\theta }=-x+\left(k_1-1\right)·y-\left(k_1-1\right)·z,\\ \frac{dy}{d\theta }=-x+\left(k_1-2\right)·y-\left(k_1-1\right)·z,\\ \frac{dz}{d\theta }=y{k}_1+\left(k_1+\alpha \right)·z+\beta ·\left(z-1\right)·H(z-1).\end{array}$$

(3)

$$\begin{array}{cc}\theta =\frac{t}{\tau },& \tau =R·C\end{array}$$

(4)

The second step applies the Euler–Cromer numerical integration [35], acquiring the approximate discrete solution of the system (5).

$$\{\begin{array}{l}{x}_{n+1}=\left(1-\Delta \theta \right)·x_n+\left(k_1-1\right)·y_n·\Delta \theta -\left(k_1-1\right)·z_n·\Delta \theta ,\\ y_{n+1}=-x_n·\Delta \theta +\left(\left(k_1-2\right)·\Delta \theta +1\right)·y_n-\left(k_1-1\right)·z_n·\Delta \theta ,\\ z_{n+1}=y_n{k}_1·\Delta \theta +\left(\left(k_1+\alpha \right)·\Delta \theta +1\right)·z_n+\beta ·\left(z_n-1\right)·H(z_n-1)·\Delta \theta ,\end{array}$$

(5)

where Δθ is the time step and n is the index of the discrete solution.

The system (5) represents the circuit’s dynamics in discrete form. In this case, the frequency of chaotic oscillations is not defined by τ but by the discrete circuit’s clock frequency. The Δθ does not represent real time in this case and is dimensionless but must be selected carefully to ensure chaotic behavior. It is important to note that this research works with the discrete model itself, and not its full implementation as a digital circuit. For this reason, the discrete model based on system (5) was implemented in MATLAB.

The fabricated prototype of the circuit is shown in Figure 2b. The variable resistor is used to set the 780 Ω resistance.

This work also uses the LTspice model of the circuit (Figure 2c). In the LTspice model, the 1N4148 diode model is based on the Berkeley SPICE semiconductor diode [36]. The opamp model is built with several transistor stages. LTspice computes a numerical ordinary differential equation (ODE) when conducting transient analysis, using the Newton–Raphson method at each time step to solve the non-linear elements [35]. The time step of the solver is variable, making interpolation of the results crucial to acquiring data at a fixed time step.

Figure 3, Figure 4 and Figure 5 demonstrate the attractor projections of the circuit acquired from the abovementioned models. The state variable signals acquired from LTspice and recorded from hardware are scaled by amplitude and time using (2) and (3) to match the discrete model. The figures demonstrate that the attractors are similar across the models, with the differences being in the amplitudes and offsets of the signals.

2.2. Vilnius Chaos Oscillator

The second chaos oscillator for this work is “A simple chaotic oscillator for educational purposes” [26], which is referred to as “Vilnius chaos oscillator”. The circuit diagram, LTspice model, and fabricated prototype of this oscillator are shown in Figure 6.

The dynamics of the oscillator are described with a system of differential equations in (6). The state variables are the voltages across the capacitors $C_1$ and $C_2$ as well as the current through the inductor $L_1$.

$$\{\begin{array}{l}{C}_1\frac{d{v}_{C_1}}{dt}=i_{L_1},\\ L_1\frac{d{i}_{L_1}}{dt}=(k-1)R_1{i}_{L_1}-v_{C_1}-v_{C_2},\\ C_2\frac{d{v}_{C_2}}{dt}=i_0+i_{L_1}-i_D,\end{array}$$

(6)

where $i_D$ is the current of the diode $D_1$; $i_0$ is the current of the resistor $R_4$; $k$ is the gain of $OA$. The nominals and parameters of the other elements are: $C_1=$ 1 nF; $C_2=$ 150 pF; $L_1=$ 1 mH; $R_1=$ 1 kΩ; $R_2=$ 10 kΩ; $R_3=$ 6 kΩ; $R_4=$ 20 kΩ; $V_1=$ 5 V; $k=\frac{R_2}{R_3}$. The nonlinearity of the system is introduced with the diode current’s equation in (7).

$$i_D=i_s·(\exp (\frac{e{V}_{C_2}}{k_{B}T})-1),$$

(7)

Like in the previous case, the dimensionless variables in (9) are introduced, resulting in (8). Next, the differentiation is taken over θ—time t scaled by the time constant τ (10) and (11).

$$\{\begin{array}{l}\frac{dx}{dt}=y,\\ \frac{dy}{dt}=a·y-x-z,\\ \epsilon ·\frac{dz}{dt}=b+y-c(\exp (z)-1),\end{array}$$

(8)

$$\begin{array}{ccc}x=\frac{v_{C_1}}{V_T},& y=\frac{\rho ·i_{L_1}}{V_T},& z=\frac{v_{C_2}}{V_T},\\ V_T=\frac{k_{B}T}{e},& \rho =\sqrt{\frac{L_1}{C_1}},& \epsilon =\frac{C_2}{C_1},\\ a=(k-1)\frac{R_1}{\rho },& b=\frac{\rho ·i_0}{V_T},& c=\frac{\rho ·i_S}{V_T},\end{array}$$

(9)

$$\{\begin{array}{l}\frac{dx}{d\theta }=y,\\ \frac{dy}{d\theta }=a·y-x-z,\\ \epsilon ·\frac{dz}{d\theta }=b+y-c(\exp (z)-1),\end{array}$$

(10)

$$\begin{array}{cc}\theta =\frac{t}{\tau },& \tau =\sqrt{L_1·C_1}\end{array}$$

(11)

Finally, the Euler–Cromer numerical integration [35] is taken, acquiring the approximate discrete solution of the system in (12).

$$\{\begin{array}{l}{x}_{n+1}=a·y_n·\Delta \theta +x_n,\\ y_{n+1}=y_n·(1+a·\Delta \theta )-x_n·\Delta \theta -z_n·\Delta \theta ,\\ z_{n+1}=\frac{\Delta \theta }{\epsilon }·(b+y_n-c·(\exp (z_n)-1))+z_n,\end{array}$$

(12)

Like the RC oscillator, the following circuit was implemented in hardware shown in Figure 6b. The discrete model based on system (11) was implemented in MATLAB, as well as LTspice (Figure 6c). Figure 7, Figure 8 and Figure 9 demonstrate the attractor projections of the circuit acquired from the abovementioned models. The state variable signals acquired from LTspice and recorded from hardware are resampled and scaled to match the discrete model like with the RC chaos oscillator. The figures demonstrate that the attractors are similar across the models, with the differences being in the amplitudes and offsets of the signals.

2.3. Pecora–Carroll Chaotic Synchronization

This work studies the performance of Pecora–Carroll chaotic synchronization [19] for synchronizing the analog chaos oscillator to its discrete model and vice versa. This synchronization technique is outlined in Figure 10. The synchronization principle is as follows: the state variable $y_1$ of the drive chaos oscillator replaces the $y_2$ state variable of the response chaos oscillator. As a result, the response system follows the behavior of the drive system—the $x_2$ state variable repeats the behavior of $x_1$, and $z_2$ repeats $z_1$. Figure 10a demonstrates that for the analog-discrete chaotic synchronization the analog-to-digital converter (ADC) is required to apply the synchronization signal of the drive analog chaos oscillator to the response discrete oscillator. The digital-to-analog converter (DAC) is required for the discrete-analog synchronization to apply the synchronization signal from the discrete chaos oscillator to its analog counterpart in Figure 10b. For the Vilnius and RC chaos oscillators, the $y$ state variable is used for synchronization, as it was found that synchronization can be achieved using only this state variable.

The previous work [37] verified the possibility of synchronization between continuous and discrete time Vilnius chaos oscillators experimentally without analyzing the performance. An example in Figure 11 shows the time diagrams of the Vilnius chaos oscillator hardware circuit and discrete model after $y_1$ of the hardware circuit was applied to the discrete model. The figure demonstrates that synchronization occurs even if the initial conditions of the two oscillators differ.

3. Study on Synchronization Noise Immunity

The first study on the performance of Pecora–Carroll analog-discrete and discrete-analog synchronization is synchronization noise immunity. This study aims to assess the influence of noise on the quality of chaotic synchronization in each case. The following subsections elaborate more on the simulation (using the LTspice and discrete models) and experimental (using the hardware and discrete models) setups and analyze the acquired results.

3.1. Analog-Discrete Synchronization

The first part of this study is evaluating the analog-discrete synchronization noise immunity. Figure 12 outlines the experiment in block diagrams. The drive chaos oscillator is the LTspice model in one case and the hardware model in the other case, while the response oscillator is the discrete model. The band-limited white Gaussian noise (B.L. AWGN) is added to the chaotic signals of the drive chaos oscillator. Each noise signal is formed individually for each chaotic signal by applying the low-pass filters with the cut-off frequency matched to the bandwidth of the chaotic signals. The assumption that the noise signal’s presence in the same bandwidth as the signal is made.

Table 1. Cut-off frequencies for forming the B.L. AWGN for each chaotic signal.

Chaos Oscillator	Model	Cut-Off Frequency of the Filter for Forming n1 (Noise for x)	Cut-Off Frequency of the Filter for Forming n2 (Noise for y)	Cut-Off Frequency of the Filter for Forming n3 (Noise for z)
Vilnius	Discrete	0.25	0.40	0.69
	LTspice	0.40	0.40	0.76
	Hardware	0.29	0.37	0.58
RC	Discrete	0.60	0.67	1.00
	LTspice	0.50	0.83	0.93
	Hardware	0.60	0.67	1.00

compiles cut-off frequencies of filters for all signals. The table also shows that chaotic signals of the different models have mostly similar bandwidths. More information on how the cut-off frequency was selected is available in Appendix A.

The quality of synchronization is evaluated using the correlation coefficient. The correlation is computed using (13). Here the example correlation is computed for arbitrary $A$ and $B$.

$$\beta =\frac{{\displaystyle \sum _m\left(A_m-\overline{A}\right)·\left(B_m-\overline{B}\right)}}{\sqrt{{\displaystyle \sum _m{\left(A_m-\overline{A}\right)}^2·{\displaystyle \sum _m{\left(B_m-\overline{B}\right)}^2}}}},$$

(13)

where $\beta$—correlation coefficient and $m$—array index.

Correlation equals 1 for the identical signal when synchronization is achieved and 0 when there is no similarity between the signals (no synchronization). The case of correlation equal −1 is for the case of opposite signals; however, the negative values of the correlation should not occur in this study. The work estimates the 1000 $\theta$ correlation time variations applying N = 1000 long sliding window. The final result is obtained as an average of 100 Monte-Carlo iterations.

The added noise signal will influence the level of synchronization, decreasing the quality of synchronization with the increase of the noise power relative to signal power. The signal-to-noise ratio (SNR) formula used in the work is given in (14).

$$SNR(dB)=10·{\log }_{10}\left(\frac{P_{signal}}{P_{noise}}\right).$$

(14)

Figure 13 demonstrates the implementation of the block diagrams in Figure 12. Figure 13a shows the discrete model synchronization with LTspice noise immunity. The LTspice signals are exported to MATLAB, where they are resampled and scaled. Then, the noise signals of a defined SNR are added to the signals, after which the $y_1+n_2$ is passed to the discrete model. Finally, the correlation is calculated for $x_2$, $x_2+n_1$ and $z_2$, $z_1+n_3$.

Figure 13b demonstrates the discrete model synchronization with hardware noise immunity. The analog discovery PRO ADP3450 oscilloscope channels are used to record the chaotic signals of the chaos oscillators; the figure demonstrates the example with the RC chaos oscillator. Similarly, the signals are resampled and scaled before passing the synchronization signal to the discrete model and estimating correlation.

3.2. Discrete-Analog Synchronization

The second part of this study evaluates the discrete-analog synchronization noise immunity. Figure 14 outlines the experiment in block diagrams. The drive chaos oscillator is the discrete model, while the response oscillator is the LTspice model in one case and the hardware prototype in the other case. Like in the first part, the band-limited white Gaussian noise (B.L. AWGN) is added to the chaotic signals of the drive chaos oscillator. The cut-off frequencies are taken from Table 1.

Figure 14 demonstrates the implementation of the block diagrams in Figure 14. Figure 15a demonstrates the LTspice model synchronization with discrete model noise immunity. In MATLAB the discrete signals are resampled and scaled; the noise signals of required SNR are also added before exporting to LTspice. For estimating the correlation, all signals are scaled again to the discrete model parameters.

Figure 15b demonstrates the hardware prototype synchronization with the discrete model. In this case, the signal generator channel of the ADP3450 is used to pass the noisy synchronization signal of the discrete model to the hardware chaos oscillator. The oscilloscope channels are used to record back the chaotic signals of the chaos oscillator. Similarly, the recorded hardware chaotic signals are scaled before estimating correlation with the noised signals of the discrete model.

3.3. Results Analysis

This subsection summarizes the results of the analog-discrete and discrete-analog synchronization noise immunity study; the results are grouped by the oscillators. The results using the approximated curves for the RC chaos oscillator are presented in Figure 16 and the results for the Vilnius chaos oscillator are presented in Figure 17.

Figure 16 and Figure 17 demonstrate the change of correlation coefficient $\beta$ over the noise levels. As expected, the correlation level is mostly 0.8 to 0.95 for 30 dB SNR, and the correlation level decreases with the decrease in SNR (i.e., increase of the noise level) down to 0.1 to 0.2 for 0 dB SNR. Analyzing the results compiled in the two figures, the match between the LTspice and hardware results is exceptionally close, with the differences explained by the additional noises and mismatches introduced in hardware. The overall close match between the LTspice and hardware means that the LTspice is precise in terms of synchronization performance in hardware. The difference between the $x$ and $z$ in terms of noise immunity was expected due to the difference in waveforms of the signals.

The RC chaos oscillator results in Figure 16a,b show little difference in the behavior of $x$ and $z$ state variables and close match between the analog-discrete and discrete-analog chaotic synchronization performance. The Vilnius results in Figure 17a,b shows that the $z$ state variable has lower correlation than $x$ for the given noise levels. This means that this state variable is more sensitive to noise due to the signal’s waveform. Comparing the results of the two chaos oscillators, the RC chaos oscillator demonstrates better synchronization for the two state variables.

4. Study on Synchronization and Desynchronization Time

The second study on the performance of Pecora–Carroll analog-discrete and discrete-analog synchronization is synchronization and desynchronization time. This study assesses the time required for the synchronization and desynchronization at different noise levels. The following subsections elaborate more on the study details and analyze the acquired results.

4.1. Analog-Discrete and Discrete Simulation and Experimetnal Setup

The given study is based on the setup of the first study (Figure 12 and Figure 14), with one key addition that allows the study to be performed: a switch that controls when the synchronization signal is applied. Figure 18 demonstrates the example with analog-discrete synchronization, where the noised synchronization signal is passed to the controlled switch before applying it to the discrete model.

In case the synchronization occurs in LTspice or MATLAB, only minor functional modifications are required. The only major addition is the discrete-analog synchronization using the hardware prototype demonstrated in Figure 19. The DG419 [38] analog switch circuit is introduced to perform the study. The synchronization signal from the discrete model is passed to the first input In₁ of DG419 from the signal generator of ADP3450, while the second input In₂ is left open. The switch control input is connected to the second signal generator channel of ADP3450. The generated 2 kHz rectangular control signal has 5 V on high and 0 V on low levels. The switch control signal is recorded on the 3rd channel of the oscilloscope to assist with getting the start times of the synchronization and desynchronization intervals.

Figure 20 and Figure 21 demonstrate examples of the change in correlation coefficient over time while applying a synchronization signal to the response oscillator. The synchronization and desynchronization time for every noise level is taken as the average of 10 synchronization and desynchronization times. The case of RC hardware prototype synchronization with the discrete model using setup in Figure 19 is demonstrated in Figure 20. The measurements record 12 synchronization intervals, of which 10 are taken to estimate the times. The dashed lines show the detected start times of synchronization and desynchronization intervals. The synchronization time is taken as the time between the start of synchronization (control signal rising) and the moment when correlation $\beta$ reaches 80% of the average level at the given noise level. The desynchronization time is measured similarly: the time is taken between the end of the synchronization signal application and the moment when correlation $\beta$ reaches 20% of the average level. The first study acquired the synchronization levels and compiled them in Figure 16 and Figure 17. In Figure 20 and Figure 21, this threshold is marked with a horizontal dashed line.

The case of synchronization acquired in software like in Figure 21, where the synchronization of the discrete model to the hardware the oscillators are kept synchronous for 10$\theta$; the time between the synchronization is 30$\theta$. The time before the first synchronization is 50$\theta$, and the total time is 440$\theta$. In this case, the start of synchronization and desynchronization are set in software and do not need additional detection. It is important to note that Figure 20 and Figure 21 demonstrate how the synchronization and desynchronization times are measured in simulation and hardware. The results of this study are presented and analyzed in the next subsection.

4.2. Results Analysis

This subsection compiles and analyzes the results of the analog-discrete and discrete-analog synchronization and desynchronization time. The results are grouped by chaos oscillators and the state variables in Figure 22 and Figure 23. The benefit of using $\theta$ (time scaled by the time constant of the oscillator) is that the results for two chaos oscillators become comparable despite the different frequencies of oscillations.

Analyzing the results of the two figures, the synchronization and desynchronization times change very little over at the high SNR levels. Decreasing the SNR demonstrates two types of behavior. The first behavior is the decrease of the synchronization and desynchronization time (Figure 22 and Figure 23c,d), which is attributed to the lower level of synchronization, i.e., the lower the synchronization level, the less time is required to reach 80% of the synchronization level threshold. The cases demonstrating the increase in synchronization and desynchronization times (Figure 23a,b) are when the synchronization level is so low (less than 0.2) that it barely stands out from the noise present when the oscillators are not synchronized.

The results also demonstrate that chaotic synchronization takes more time than desynchronization. The Vilnius chaos oscillator is the fastest in terms of analog-discrete synchronization, while the RC chaos oscillator is faster in terms of analog-discrete desynchronization. The RC chaos oscillator is also faster in terms of discrete-analog synchronization and desynchronization, making this oscillator the fastest overall in synchronization and desynchronization speed.

Like in the first study, the use of LTspice to model the behavior of the hardware circuit produces similar results in most cases, but there are exceptions like the Figure 23a,b, where the desynchronization time shows a completely different behavior in LTspice than the hardware circuit.

5. Conclusions

The current work aimed to study the performance of the Pecora–Carroll synchronization technique to achieve synchronization between the analog and discrete chaos oscillators. The two key parameters of the chaotic synchronization, synchronization noise immunity and synchronization speed, were investigated. The noise immunity study demonstrated the quality of synchronization at various noise signal power levels present during the synchronization, while the synchronization speed demonstrates how quickly the analog-discrete synchronization is achieved, along with how quickly the two systems diverge when the synchronization signal is no longer applied.

The discrete chaos oscillator was implemented as the discrete solution of the chaos oscillator circuit; MATLAB was used to simulate the discrete model. The analog chaos oscillator was implemented in PCB, but the study also used an LTspice model of the oscillator to compare the behavior of analog-discrete and discrete-analog synchronization using a real prototype and its model in the commonly commercial software such as LTspice. The work also performed two studies on different chaos oscillators—RC chaos oscillator and Vilnius chaos oscillator—to compare the analog-discrete and discrete-analog chaotic synchronization performance of different chaos oscillators. The acquired synchronization results were in favor of the RC chaos oscillator.

The hybrid analog-discrete approach of implementing chaos oscillators opens new possible communication schemes for IoT applications. The analog implementation of chaos oscillators can benefit the simpler sensor node (SN) integration, while the discrete implementation can be used on the gateway. The acquired results, developed models and prototypes will serve as the foundation for further developing the hybrid chaos-based communication system. This future development in this direction will be aided by the knowledge and the competencies gained in the previous works [32,33,34] when developing analog chaos oscillator-based communication systems.