1. Introduction
DC-DC converters are electronic subassemblies used in a huge amount of equipment in numerous fields of activity. The online knowledge of the behavior of the circuits or components and the knowledge of their state-of-health serve in operation as a prerequisite both for the adjustment and adaptation of the control of the converters and for predictive maintenance [
1,
2]. In the design and operation of DC-DC converters, it is important to model them, completely or partially, i.e., only some of the main components, mostly the output filter capacitor [
3]. It can be found both at buck [
4] and boost converter [
5]. The filter capacitor behavior is described by models with schemes of varying complexity, depending on the details of the physical phenomena with impact on the system functioning [
6,
7,
8,
9]. The most used model is the R-C series one [
10,
11,
12].
The R-C series simplified model is suitable for capacitor functions in a low-band frequency [
3]. Regarding the monitoring of a capacitor, the equivalent series resistance (ESR) and the equivalent capacitance are frequently used as diagnostic parameters [
13]. Always, in applications, the ESR and capacitance vary over a frequency range determined by the spectrum of the current corresponding to the operating regime [
13]. In this context, the “equivalent” attribute underlines, in addition to the “effective” attribute used, for example, in [
14], the fact that the estimated values of the two parameters characterize the behavior of the capacitor across an entire operating regime [
15].
Condition monitoring of capacitors basically includes two phases: the estimation of the equivalent parameters, followed by the use of the estimated values to assess the capacitor condition [
2,
16,
17]. The classifications of estimation techniques and evaluation methods are also addressed in papers [
3,
18]. In [
19], attention is paid to the classification of condition monitoring techniques for aluminum electrolytic capacitors (AEC) in offline, online, and quasi-online techniques.
In control systems engineering and system analysis, mathematical models called observers are frequently used to estimate individual or hybrid variables (combinations of states and input signals) from real systems, called master systems. The inputs of an observer are the measurable inputs and outputs of the master system [
20]. Observers are essentially subsystems tracking one or more measurable outputs of the master system.
Numerous studies on DC-DC converters and their components imply observers for estimation, performance control, and fault detection [
1,
21,
22,
23,
24,
25,
26]. In [
21], specific observers are used in a buck converter for the fault diagnosis, inductance, and capacitance estimations. In reference [
22], the observer serves to control a switching-mode DC-DC converter. The study [
25] proposes distinct observers for the ESR and for the capacitance C of the output capacitor of a boost converter. In [
1], a state observer is proposed to counterbalance the errors with an ideal model of a boost converter. The paper [
23] introduces a piecewise linear observer designed for fault-sensitive detection filters for power electronics systems and exemplified for a dual-redundant buck converter. The study in [
24] focuses on the design, analysis, and experimental integration of an enhanced robust adaptive parameter identifier for DC-DC converter applications, based on a closed-loop linear switched state observer. This identifier is designed considering for the capacitor a simple C-model. An observer for estimating the load resistance of a DC-DC buck converter is presented in [
26].
In [
15] is proposed a new type of observer, distinct from those typically employed in control systems, in particular from those used in DC-DC converters, designed to estimate the time constant of a first-order system. The PO was implemented by the authors to estimate the capacitor parameters of a buck converter based on discharging the capacitor in two stages: over the load resistance in the first stage and over the load resistance connected in parallel with additional resistance in the second stage [
27]. The PO uses as input only the measured output of the master system, namely, the voltage at the terminals of the filter capacitor.
This article aims to introduce novel DC-DC buck converter schemes provided with the capability to estimate the equivalent parameters of one or more filter capacitors using a parameter observer (PO).
The main contribution of this paper consists of:
(i) The proposal of two new schemes of DC-DC buck converters from the category of those estimating the parameters of the R-C series capacitor impedance model using the principle of non-periodic large-signal charging/discharging profiles [
17]. From the point of view of the contribution of the monitored capacitor to the filtering operation during the estimation of the parameters, the schemes are working in a quasi-online mode of operation.
(ii) The implementation of a new monitoring principle for the equivalent parameters with PO based on a capacitor discharge/charge process. Compared to the converter in [
26], where the PO monitors a two-stage discharge process, in the new scheme the time to disconnect the capacitor and the load from the converter is reduced. Also, compared to the technique described in [
19], current injection into the capacitor is avoided.
(iii) The implementation of the monitoring principle with PO by performing the filtering with two capacitors connected in parallel instead of a single capacitor.
(iv) The experimental validation of the proposed principles on converters with electrolytic filter capacitors.
The following sections of the paper comprise: the theoretical and analytical support of the POs used in DC-DC buck converters (
Section 2), the principles of designing the novel schemes (
Section 3.1), and the depiction of the converters’ schematics along with their experimental validation methods (
Section 3.2 and
Section 3.3), discussing the theoretical and experimental results (
Section 4), and finally summarizing the conclusions. The article ends with an
Appendix A, important in terms of outlining the conditions that must be met to reduce the estimation errors of the filter capacitors’ equivalent parameters.
3. Two Schemes of DC-DC Buck Converter with Estimation of Equivalent Parameters of Filter Capacitor Using PO
The two buck converter configurations proposed in the principle schemes in
Figure 7a,d are obtained by adding a variable electrical network (VEN) [
28] and a microcontroller to a switching regulator circuit based on the LM2596 integrated circuit [
29]. They allow the implementation of the measurement process, the mentioned observers, and the management of the VENs. In the first scheme, an auxiliary source of stabilized DC voltage is included as well. The schemes are shown in
Section 3.2 and
Section 3.3. The part represented in black corresponds to the basic scheme in [
29], and the part represented in red includes the performed adaptations. The POs are implemented in the microcontroller in the discrete-time system version (8).
3.1. Principle Schemes
From the point of view of the continuous supply of the converter load, the proposed schemes are of two categories: schemes with short-term disconnection of the load from the converter and schemes without disconnection of the load from the converter. The schemes in
Figure 7a,b belong to the first category, and those in
Figure 7c,d to the second category. The load and the filter capacitor are connected to the converter via terminal T. In all schemes, the filter capacitor is modeled by the serial equivalent circuit
−
. POs are implemented in the measurement and processing (EMP) device. They calculate the estimates
and
by processing the voltage at the capacitor terminals denoted, as appropriate, by
. The values of
,
,
and
are chosen considering the requirements mentioned at the end of
Appendix A. Schemes in the second category have the advantage of not including the converter load in the capacitor discharge sequences, thereby not being constrained by the requirements of
Appendix A.
In the schemes of the first category, the parameters of the capacitor are obtained during a discharge/charge process using PO2 of Equation (8). The charging of the capacitor is carried out at the voltage from a stabilized voltage source and not from the converter. When switches sw1 and sw2 are in the ON position and sw3 is in the OFF position, the circuits are in normal operation mode (DC-DC mode). Switching sw1 from the OFF position to the ON position results in transients at the load level.
Figure 8 illustrates the
signal in an estimation cycle associated with a discharge/charge process corresponding to the schemes in
Figure 7a,b. During the I interval, the schemes operate in DC-DC mode. In intervals III and V, PO2 estimates the equivalent time constants. In intervals II and IV, of duration
, PO2 acquires the voltage
but does not calculate
and
. The VI interval corresponds to a transient regime of DC-DC mode restoration.
Table 2 shows the sequence of switch states and regimes for an estimation cycle of the scheme in
Figure 7a.
In second-category schemes, capacitor parameters are obtained using the discrete-time variant of PO (2) during two separate discharges of the capacitor through resistors
and
, which have different values. Between discharges, the monitored capacitor is recharged via the T terminal from the converter when the T-sw1 switch is closed and the LM2596 is ON. Reconnections of the capacitor to the converter result in this case also with transient regimes at the load level. In
Figure 7d, the filtering is performed using a capacitance created by connecting two capacitors in parallel. Each capacitor is monitored separately. During monitoring of one capacitor, the other capacitor provides filtering by remaining connected to the converter. This option is advantageous for at least two reasons: (i) the scheme ensures filtering throughout the estimation; (ii) the transients caused by the disconnection and reconnection of the capacitors to the converter are mitigated. The principle can be generalized for batteries of filter capacitors or schemes where “dividing” the filter capacity in at least two capacities can offer technical benefits.
Table 3 shows for the scheme in
Figure 7d the sequence of regimes that occur when estimating the parameters of capacitor 1 (regimes R1–R9) and of capacitor 2 (regimes R1’–R9’). The manner in which time is handled during discharges is detailed below within
Section 3.3. in the explanations regarding the proposed converter as an application to the diagram in
Figure 7d.
3.2. Scheme Based on the Implementation of the Principle from Figure 7a
The proposed scheme is the one in
Figure 9. The converter supplies the resistive load
and
is the filtering capacitor. It is a
electrolytic capacitor. Its frequency characteristics, measured using a BK Precision RLC-bridge, are illustrated in
Figure 10a,b. The transistors T-sw1, T-sw2, and T-sw3 are used to realize the switches sw1, sw2, and sw3 in
Figure 7a. The LDO is a voltage regulator that provides the voltage
for charging
through the resistor
. A microcontroller with computing power based on the Cortex
®-M7 architecture was used for measuring and processing. The signal
was acquired with the sampling time
. The microcontroller sends signals towards the LM2596 circuit and switches using the digital ports P1, P2, P3, and P4 and measures the voltage
at capacitor and load terminals using the analog port AIN. To estimate the capacitor’s equivalent parameters, the microcontroller executes the successive operation of the regimes R1–R7 in
Table 2. In stages III and V (
Figure 8), PO2 implemented in the microcontroller calculates
,
,
and
. To achieve a more accurate diagnosis of the capacitor’s condition, a sensor S
θ is thermally coupled with the capacitor and interfaced with the microcontroller. The measured result is sent together with the estimated values of the capacitor parameters using a serial SOUT interface towards external assessment of
.
Below are some practical results that validate the structure in
Figure 9. Experimentally, by commuting and maintaining the
Figure 9 scheme in the R4 regime from
Table 2, a value of
was obtained. To determine the values of
and
six sets of 25 discharge/charge experiments of
were performed. In each set, the experiments were repeated with a frequency of
. Each discharge/charge process took 40 ms. In
Figure 11a is illustrated how the voltage
varies in an experiment, and in
Figure 11b the corresponding characteristics
and
are represented. The values resulting from the experiment are
and
. From the perspective of
Figure 1, for
Figure 11a:
s,
s,
s. The calculation of the characteristics
and
is turned off when the condition in Equations (10) and (11) is met, resulting in the moments
and
. The time
is an arbitrary time according to the series of experiments mentioned below. The time
, when the capacitor commutes from discharging to charging corresponds to the moment when
reaches the value of
, so that for the calculation of
remains available a voltage interval of approx.
. Time
corresponds to the moment when
is obtained. It is observed that the value of
from the moment when OP2 provides
is approx.
. If
had been associated with this moment, then for the calculation of
there would have been a rather small tension interval available, of approx.
.
Figure 11.
capacitor charging/discharging signal in
Figure 9 and the result of its processing with PO2: (
a) The signal
on capacitor terminal; (
b)
and
,
characteristics generated by PO2.
Figure 11.
capacitor charging/discharging signal in
Figure 9 and the result of its processing with PO2: (
a) The signal
on capacitor terminal; (
b)
and
,
characteristics generated by PO2.
Across the 150 experiments, the parameters fell within the ranges in
Table 4, corresponding to the average values indicated by (14).
According to the frequency characteristics in
Figure 10a,b, the equivalent values
and
from (14) correspond to frequencies of approx. 55.6 Hz and 59.5 Hz, respectively.
To investigate the impact of
’s assignment errors on the values of
and
obtained with PO2, six series of 25 capacitor discharge/charge experiments were performed for six different
values within the range [3.2836, 3.3036]. The parameter
of PO2 was set to the values of 7000
for the discharge phase, and
for the charge phase. The experiments confirmed the aspects revealed by
Figure 5 and
Appendix A:
is increased due to the increase of
,
variations are reduced,
is pronouncedly increased, and the dispersion intervals of the parameters are reduced.
3.3. Scheme Based on the Implementation of the Principle from Figure 7d
The proposed scheme has the configuration of
Figure 12. The converter supplies a load that is not purely resistive. The circuit was made for
and
. In
Figure 7d, the switches sw
ij were implemented with T-sw
ij transistors. Each of the capacitors
and
of the filter capacitor bank independently discharges across the resistors of the VEN, initially across the resistance
, then across the resistance
. Any discharge of a capacitor is immediately followed by a recharge of it from the converter, triggered when the PO completes the determination of the discharge time constant. Equivalent parameters
and
of the two capacitors
are calculated as solutions of the systems of Equation (15). The load impedance does not appear in the equations.
Unlike the scheme in
Figure 9, the scheme in
Figure 12 contains two temperature sensors
and
that measure the operational temperature of each capacitor.
The proposed scheme has three key advantages: (i) The load is permanently connected to the buck converter; (ii) The time constants and , are determined on the beginning portions of the discharge waves , i.e., on the portions least affected by acquisition errors, with a favorable signal/noise ratio; (iii) The duration of an estimation process is of the order of the time constant.
A more complete picture of the behavior of the scheme in
Figure 12 is given by the validation experiments presented below. The two stages differ in the nature of the converter load. In both stages, the parameter
of the PO was set to the value
.
Stage 1: Background: The converter feeds a resistive load
at a voltage
. Filtering is performed with the pair of electrolytic capacitors
,
having the frequency characteristics in
Figure 13. The external resistances of VEN have the values
and
. For processing, the same microcontroller as in
Figure 9 was used, the signal
being acquired with an equivalent sampling time
.
Figure 14 shows an estimation process. Portions ①, ②, ③ and ④ in
Figure 14a represent the characteristics,
,
,
and
provided by PO by processing the voltage
during the progress of the four partial discharges in
Figure 14b. The values of
, …,
from Equation (15) are given by the amplitudes of
, …,
from the final moments of the portions when the conditions of Equations (10) and (11) are checked. However, the moments of fulfillment of these conditions define the durations of the portions ①, ②, ③ and ④ not being necessary to monitor the time or voltage level V
0. The time intervals between portions (① and ②, …, ③ and ④) correspond to the charging of the capacitors and the transient regimes in the PO. Within these intervals, PO monitors the voltage
but does not calculate
and
. The effect of connecting/disconnecting capacitors
and
on the voltage
measured from the load terminals of the microcontroller is shown in
Figure 14c. The average voltage at the load terminals,
, has different values depending slightly on the active filtering capacitor:
in portions ① and ② where filtering is performed with
,
in portions ③ and ④ where filtering is performed with
and
in normal operation when filtering is completed with both capacitors.
In
Table 5, the results obtained for six sets of 25 experiments are systematized. The average values of the parameters on the set of 150 experiments have the values in (16). Each set of experiments was repeated again with a period
. Also, the duration of an experiment did not exceed 40 ms.
The values
and
roughly correspond to the frequency range
from the frequency characteristics in
Figure 13a,b. The different values of the frequencies are due to the non-sinusoidal nature of the experimental regime and from the measurement errors mentioned in
Appendix A.
Stage 2: Context: The converter feeds a resistive-inductive load. In series with the load resistance
were connected separately, in series, then in parallel, two coils with
and
. For each of the 4 cases, six series of 25 experiments were performed. On the set of 600 experiments, the average values were obtained:
,
for
and
,
for
. The equivalent capacitance values are practically within ±1% of those in
Table 5, while the ESR values are within much higher limits.
4. Discussion
1. The paper proposes two new DC-DC buck converter schemes shown in
Figure 9 and
Figure 12. They are intended for real-time simultaneous estimation of the equivalent capacitance and the ESR of the converter filter capacitor. In both schemes, a PO coded on a microcontroller is used for estimation purposes. The schemes differ from the original converter scheme [
29] by adding a microcontroller, some VENs composed of discharge or charge resistors with the related switches and temperature sensors, and in the first case also a stabilized voltage source. The VEN resistances are adopted taking into account the recommendations in
Appendix A. Failure to comply with these recommendations results in high values of the dispersion of
, therefore, ESR calculation. Both schemes work in a quasi-online mode. This means that while estimating, the connection between the monitored capacitor and the converter load is interrupted for a few milliseconds. From the point of view of the continuity of the connection between the load and the converter during estimation, the first scheme operates in a quasi-online mode, while the second operates in an online mode.
2. The first scheme (
Section 3.2) provides the equivalent parameters of the capacitor based on the estimation with a PO2 of the values of the equivalent time constants related to the discharge/charge process of the capacitor. The VEN only serves to charge the capacitor. Its discharge is carried out through the load resistance of the converter. Estimating the time constant of the charging process with a PO2 (
Section 2.1) is a novel approach that requires prior experimental calibration of the
parameter, according to the capacitor charging conditions (
Section 2.2). During parameter estimation, the scheme is in quasi-online mode of operation, characterized by the short-term disconnection (approx. 0.040 s) of the capacitor and the load from the converter. This means that the proposed scheme can trigger the estimation of the capacitor parameters only when the load is disconnected from the converter. Depending on the power load tolerance, this can be performed intermittently, more or less often, or when the converter is off.
Compared to the conditions in
Appendix A, in the experiments presented in the paper, we worked with
and
. As such, the condition
was met, while the condition for
to be as close as possible to 1 could not be met for reasons of limiting the current through the circuit. This fact influenced the dispersion of the calculated
values, the average value being 6.58677%. Consequently, the experiments with the scheme in
Figure 9 show that PO2 can determine with a very good approximation the value of the equivalent capacity through a single discharge/charge process. Since the value of
is small, the determination of the ESR value, however, requires performing a series of successive experiments and averaging the obtained values.
3. The second DC-DC buck converter configuration (
Section 3.3) uses a pair of capacitors for filtering, connected in parallel, and a VEN consisting of two resistors. The estimation of the parameters of each capacitor is completed alternatively by processing the discharge voltage of each capacitor across each of the resistances of the VEN. The novelty of the proposed scheme lies in the sequential investigation of the two capacitors. The estimation of the equivalent parameters is completed for one capacitor at a time, while the load, together with the second capacitor, remains connected to the converter output. As a result, the scheme operates in a quasi-online measurement regime during which neither the filtering operation nor the load supply from the converter is interrupted. In this process, the filtering capacity changes in steps.
From the perspective of the conditions in
Appendix A, the scheme used in the experiments was characterized by
and
for the
capacitor
and
for the
capacitor
. In this case also, the scheme lends itself to determining with a good approximation the value of the equivalent capacities. For a purely resistive load of the converter, the impact of the higher values of
and
, in relation to the diagram in
Figure 9 is visible: the dispersion of
values are 1.31531%, and that of
only 0.307099%. As a result, the values of the equivalent parameters of the filter capacitors, obtained in the mentioned experimental conditions, confirm the validity of the proposed scheme.
Theoretically, the proposed converter scheme can be applied regardless of the type of load: resistive or resistive-inductive. Experimentally, it was found that in the presence of the resistive-inductive load, the dispersion ranges of the values of and increased by approx. 5 times. The experiments carried out in this context failed to identify a cause that could explain this effect.
Finally, it should be noted that the method underlying the scheme in
Figure 12 can also be used when the output filter of the converter is a battery of at least two capacitors connected in parallel.
4. Both schemes estimate equivalent parameters
and measure operating temperatures
or
and
of the filter capacitors and send them out. The operating temperature is necessary to take into account its influence on the estimated values of the equivalent parameters [
2]. Since the estimating process of the capacitor parameters with POs takes less than one second, the temperature of the investigated capacitor can be considered constant during the estimation.
5. The proposed DC-DC buck converter schemes are designed by completing the basic scheme of the converter (represented in black in
Figure 9 and
Figure 12) with new components, including a microcontroller (represented in red in the two figures). This means additional costs for the converter. However, they offer the benefit of enabling predictive maintenance for the converter, leading to reduced operational costs in applications where increased reliability is required.
6. Each of the DC-DC buck converter schemes proposed in this paper is suitable for integration into a specialized integrated circuit. For example, in
Figure 12, the integration can be based on the segmentation in
Figure 15. The components within the boxed part of
Figure 15 have been selected both for their technological integration feasibility and because they do not require parameterization in the application design process. Outside the integrable part are connected components that cannot be integrated (Load and coil L
1) and components whose parameters depend on the application (capacitors
,
, external resistors
,
and temperature sensors
and
).
5. Conclusions
The article proposes two novel DC-DC buck converter schemes designed to monitor the ESR and equivalent capacitance of filter capacitors. For this purpose, parameter observers are used to calculate the equivalent parameter values of the capacitors quasi-online.
In the first scheme, the capacitor parameters are calculated by real-time processing of the voltage at the capacitor terminals during a discharge/charge process. By using the charging sequence, the duration of the estimation operation is reduced.
The second scheme achieves the output filtering by using two or more capacitors connected in parallel. In this way, the monitoring of the filter capacitors receives the advantage of the continuous supply of the load from the converter. The advantage of this connection type is that at least one filter capacitor remains connected and assures a non-interrupted supply of energy to the load. The equivalent parameters of each component capacitor are estimated in real time using two monitored discharges.
The experiments performed with both schemes, using electrolytic filter capacitors, shows that: (i) the estimation processes take approx. 40 ms; (ii) the equivalent capacity value is estimated with a precision of less than 0.25%; (iii) the estimation of the ESR value is performed with a precision dependent on both ESR and VEN resistor values.
The implementation of both schemes is associated with the acceptance of some compromises, such as limitations in the design of VENs imposed by the correlated values of the load resistance, as well as transient regimes of small amplitude occurring during the monitoring of the filter capacitor.
The estimation principles used in the two schemes are not limited to the proposed DC-DC buck converters. They are applicable in similar situations that need capacitor monitoring. Several future research opportunities open in this context, primarily by the application of the principles described in the proposed schemes for power converters and by the implementation of one of the two monitoring principles.