Adaptive On-Time Control Buck Converter with a Novel Virtual Inductor Current Circuit

Abstract

This study presents a new virtual inductor current circuit to reduce circuit complexity, which is not necessary to sense inductance current directly. The buck converter was designed to produce an output voltage of 1.0–2.5 V for a 3.0–3.6 V input voltage. The load current range was from 100 mA to 500 mA. It was simulated and verified by SIMPLIS and MathCAD. The simulation results of this buck converter show that the voltage error is within 1%, and the recovery time is smaller than 2 μs for step-up and step-down load transients. Additionally, it achieves less than 26 mV overshoot at full-load step transient response. The circuit topology would be able to fabricate using TSMC 0.35 μm 2P4M CMOS technology. The control mechanism, implementation, and design procedure are presented in this paper.

1. Introduction

Nowadays, the DC–DC buck converter is widely used in mobile phones and other portable electronic devices [1]. In order to improve the competitiveness of products, these portable devices often have more functions, but it also means more power consumption. The power supply of these devices is the battery. Reducing the power consumption of electronic devices can increase the standby time. Therefore, high conversion efficiency and fast response are the key points of power management design [2]. At present, in the power conversion technology, the control mode is roughly divided into voltage mode [3] and current mode [4,5,6,7,8]. As can be seen from Figure 1a, the voltage mode is single-loop control—the voltage loop [3]. In contrast, in Figure 1b, the current mode is dual-loop control—a voltage loop and a current loop. Compared to voltage mode, the current mode has more feedback paths from inductance current; therefore, the current mode has a faster transient response and better voltage regulation than the voltage mode. Therefore, current mode control is widely used in power management IC. With the above two control modes, there are many new control topologies that have been proposed to achieve high speed, low power, high efficiency, and small size. For example, constant on-time (COT) control technology or adaptive on-time (AOT) control technology is used in many converters.

COT control has a feature of high light-load efficiency [9,10,11]. COT control is a variable-frequency control. Under the discontinuous conduction mode (DCM), the switching frequency is naturally lowered, and the efficiency is higher; while the switching frequency increases during the load transient or voltage tracking. The variable switching frequency will affect the overall conversion efficiency due to the switching and conduction losses. The main disadvantage of the COT control scheme is the limitation of the duty cycle. The ON time always follows the preset minimum off time, which depends on the power stage and control logic. This causes the maximum duty cycle to be limited by the ON time during load transient.

Although the variable switching frequency can improve the efficiency in DCM, it will also make the other blocks in the system hard to control the electromagnetic interference (EMI) [12,13,14]. Since the operation principle of the switching power converter is to control the switch on/off, the EMI of the converter is inevitable.

In contrast, in Reference [15], the ON time is designed in inverse/direct proportional to input/output voltage to realize virtually constant-frequency operation, which is known as adaptive on-time (AOT) control. The conventional AOT control scheme is shown in Figure 2. The adaptive on-time control can improve the frequency instability of the COT control. Moreover, there is no subharmonic oscillation issue in AOT current-mode control; therefore, slope compensation is not needed. There are many studies in the literature about the AOT control solutions that have been published [15,16,17,18,19,20,21]. In Reference [17], the on-time AOT control is modulated by the output of the error amplifier rather than fixed voltage. However, the frequency of AOT control is still easily affected by the input voltage and load current changes.

No matter the AOT or COT scheme, as long as it is the current-mode control, the current sensor is usually required [22,23,24,25]. As can be seen from Figure 1b, the Ri represents the current sensor. At present, many current sensors have been proposed [4,12,15,26,27,28,29,30,31,32,33]. Among these current sensors, Hall-effect current sensors are very sensitive to the EMI of the converter [29]. However, the feature of the Hall sensor is to ensure that the power circuit and sensor can be electrically isolated. Aiello et al. [30] use a split-drain MOS transistor (MagFET) to realize an EMI-immune contactless current sensor. The low-cost isolation current sensors based on the giant magnetoresistance effect are proposed in [31,32]. Hall-effect current sensor with EMI immune is proposed in [33].

Typically, contactless current sensors are mainly used for current sensing and measuring in smart grids or in situations where electrical isolation is required [29,30,31,32,33]. Therefore, from the perspective of application and integration, the contactless current sensor solutions may not be suitable for low-power conversion IC.

Studies in the literature [23,24] proposed a sensorless solution, which uses a predictive method to estimate inductor current. The sensing methods proposed in [4,6,15,26,27,28,34] are summarized in what follows.

In Figure 3, the sensing method in [26,34] employed the resistor R_sense in series with the inductor to measure I_L by sensing resistive voltage. This sensing technique breaks the origin loop and inserts the sensing component. The disadvantage of this method is that the system power consumption will increase due to the resistor.

Another current-sensing method, shown in Figure 4, is to parallel a set of low-pass filters (i.e., R_S, C_S) in the inductor L. The disadvantage is that additional components, Rs and Cs, are needed at off-chip [15]. This sensing technique obtains the inductor current information without breaking the origin loop.

In Figure 5, an active current-sensing (ACS) technique was proposed by Chen et al. to sense inductor current [27]. The ACS senses the voltage across the inductor and converts the current information into V_SEN. Therefore, the ACS also obtains the inductor current information without breaking the origin loop. Unfortunately, the switching voltage V_P, V_N will cause the voltage V_X to change between 0 and V_IN. Due to the large variation of voltage Vx and the off-chip sensing, the sensed V_SEN would include some non-ideal effects.

Similarly, Hwang et al. [6] proposed the optimum damping control in Figure 6 to improve the dynamic response. The sensing points are the same [27], and the voltage V_X changes between 0 and V_IN. Additionally, this sensing technique is a no-break loop method.

Chen et al. [28] proposed an active current-sensing technique for hysteresis-current-controlled (HCC) buck converter, as shown in Figure 7. However, the sample and hold circuits are required in this control scheme, and the ACS will generate sparks, which affect the transient response [4].

This paper presents a novel inductor current sensing circuit. The proposed current sensor obtains the virtual inductor current by switching. The voltage of the proposed sensing point is more stable than the other methods in [4,6,15,26,27,28,34]. Moreover, the circuit is simple and can be integrated into existing control schemes such as AOT and COT. Since the sensor is integrated into the chip, the proposed control scheme provides a more stable control signal with less interference from the off-chip environment.

The paper is organized as follows: Section 2 describes conventional current mode COT/AOT control schemes. Section 3 presents the proposed scheme and implementation. Section 4 introduces the design procedure and modeling analysis with MathCAD. Section 5 shows the SIMPLIS simulation results. Finally, conclusions are given in Section 6.

2. Conventional Control Scheme Descriptions

2.1. Current Mode COT (CM-COT) Operating Principle

Figure 1b shows the conventional current mode COT control scheme. The operation of Figure 1b is described as follows: when the triangle wave V_SEN is lower the voltage V_CMP, the comparator is high. Then, the block, named “Ton” in Figure 1b, produces a constant ON time, which turns on switch S1. The state of switches S1 and S2 are complementary and non-overlapping. This means the control scheme turns on S1 for a fixed ON time and then turns off until the V_SEN drops to its limit voltage V_CMP, and then turns on S1 again. The block named “EA” means the error amplifier, which includes the trans-conductor and the compensation network. The main purpose of the EA is to regulate Vo and determine OFF time.

In contrast to the pulse width modulation (PWM) control schemes, this control scheme does not need additional slope compensation in the current loop to ensure stability. However, since the switching frequency is allowed to change, the switching control signal looks more jittery in valley current mode control.

Conceptually, in the current control mode, the inductor becomes a controlled current source due to the current loop. Therefore, the whole system becomes a first-order system instead of a second-order system. The phase lag caused by the poles of the power stage is reduced from 180 degrees to 90 degrees. Smaller phase delay makes the compensation of voltage sensing path much easier. The power supply is not so sensitive to variations in capacitance or inductance [35].

2.2. Current Mode AOT (CM-AOT) Operating Principle

The AOT control scheme in Figure 2 is derived from the COT structure. Therefore, the operation principle of the AOT scheme is roughly the same as the COT scheme. The main difference is that the ON time is controlled by the voltage V_CMP, rather than constant.

3. Proposed Control Scheme and Implementation

3.1. Operating Principle

Figure 8 shows the proposed control scheme, which is a current mode AOT control. The basic operating principle is the same as the AOT control scheme, described in Section 2.2. Different from [4,6,15,26,27,28], a novel current sensing technique is proposed in this control scheme. In Figure 8, the proposed virtual inductor current (VIC) senses V_IN and V_O to generate V_SEN instead of V_X and V_O. Since V_IN is more stable than V_X, the VIC sensing results are expected to be better than [27].

3.2. Proposed Virtual Inductor Current Sensor

The proposed VIC sensor is shown in Figure 9. As is commonly known, the voltage and current on the inductor can be expressed as Equation (1), where L is the inductance, V_L and I_L are the voltage and current on the inductor, respectively. From Equation (1), the current variation ΔI_L will be proportional to V_L. Figure 10 illustrates the relation of inductor current and voltage, where S1, V_x, and V_o are shown in Figure 8. Conceptually, I_L waveform is similar to current charging/discharging a capacitor. Therefore, as long as V_x, V_o can be included in the charging/discharging current, I_L can be converted to V_SEN. However, this paper does not sense V_x but senses V_IN voltage. Nevertheless, it can also meet the requirements through S3 in Figure 9.

$$\Delta I_L=\frac{V_L}{L}·\Delta t$$

(1)

In Figure 9, V_IN, V_O, V_P, V_SEN are defined as terminals and represented by I/O pin symbols. In order to clearly present the implementation of the VIC sensor, the VIC sensor is combined into the proposed control scheme and shown in Figure 11.

4. Design Procedure

4.1. Buck Converter Modeling

To analyze the stability of the system, we need to obtain the closed-loop transfer function and understand the position of zeros and poles and their influence on the system. The open-loop modeling method for current-mode control is described in [36,37,38]. In fact, it is not easy to develop an accurate small-signal model of current-mode converters. At present, the current-mode converter model proposed by Ridley is the most common small-signal model [39]. In recent years, a more effective and intuitive circuit model for current-mode controls was also proposed by Li et al. [40].

In Figure 12, the modulator G_p(s) consists of the comparator, the inductor, the switches, and the on-time block. In the modeling process, all of them are modeled as a single entity rather than breaking them into parts. By the modeling method described in [39], the transfer function from the signal V_CMP to the output signal V_O can be presented as Equation (2).

$$G_P\left(s\right)=\frac{v_o\left(s\right)}{v_{CMP}\left(s\right)}\approx \frac{1}{R_i}·\frac{1}{1+\frac{s}{Q·\omega }+\frac{s^2}{{\omega }^2}}·\frac{R_{LOAD}\left(R_{ESR}{C}_{o}s+1\right)}{\left(R_{LOAD}+R_{ESR}\right)C_{o}s+1}$$

(2)

where $R_i$ is the current sensing gain, $\mathsf{\omega }=\raisebox{1ex}{$\pi $}\!\left/ \!\raisebox{-1ex}{$T_{on}$}\right. \mathrm{and} Q=\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$\pi $}\right.$. It is evident from Equation (2) that a double-pole condition may lead to system instability.

4.2. Crossover Frequency f_C Determination

Higher bandwidth will have a fast transient response. However, the bandwidth increase will sacrifice the circuit stability, which makes the circuit more susceptible to switching noise. Therefore, how to balance the stability margin and transient response is very important. In fact, due to the current sampling effect, the current-mode control also introduces double poles at ½ f_sw [39]. Therefore, for sufficient phase margin, we will often design the crossover frequency at 1/10–1/6 of the switching frequency f_sw, as shown in Equation (3).

$$f_c\le \left(\frac{1}{10}~\frac{1}{6}\right)·f_{SW}$$

(3)

4.3. Compensator Design

A(s) is the most critical for loop compensation design, which determines the cross-frequency, DC gain, phase, and gain margin of the voltage loop. To describe the loop gain, Figure 12 is simplified to Figure 13. In Figure 13, the converter loop gain T(s) can be expressed in Equation (4). In this paper, a type II compensation network is used at the output end of the operational amplifier, which is composed of resistance $R_t$, and capacitance $C_t$ and $C_p$ in parallel. The compensation network combined with an operational amplifier can be expressed as the compensator gain A(s), as shown in Figure 14. The transfer function A(s) is given by Equation (5). In the compensator design procedure, the zero $w_z$ is set to cancel the output pole of the peak current-mode buck topology, expressed as Equation (6). The compensation pole $w_{p2}$ is set at the lower frequency between the output capacitor ESR zero and 1/2 of the operating frequency. $w_{p1}$ is extrapolated to make the feedback system more stable.

$$\mathrm{T}\left(\mathrm{s}\right)=G_P\left(s\right)·A\left(s\right)·k$$

(4)

$$\mathrm{A}\left(\mathrm{s}\right)=\frac{v_{CMP}\left(s\right)}{v_{FB}\left(s\right)}=g_m·R_{tho}·\frac{\left(1+\frac{s}{w_z}\right)}{\left(1+\frac{s}{w_{p1}}\right)·\left(1+\frac{s}{w_{p2}}\right)}$$

(5)

where $w_z=\frac{1}{R_t·C_t}$, $w_{p1}=\frac{1}{R_{tho}·C_t}$, $w_{p2}=\frac{1}{R_t·C_p}$.

Set the $w_z$ of the compensator to cancel the output pole as follows:

$$w_z=\frac{1}{R_{LOAD}·C_{out}}, f_z=\frac{w_z}{2\pi }$$

(6)

Set the $w_{p2}$ of the compensator at about 1/2 of the switching frequency, as shown in Equation (7).

$$w_{p2}\approx \frac{1}{2}·w_s=\frac{1}{2}·(2\pi f_{sw})$$

(7)

4.4. Stability Analysis

Step1: Substitute

Table 1. Simulation condition.

Component	Value	Unit
RLOAD	3.6	Ω
Co	10	μF
L	4.7	μH
RESR	5	mΩ

value into Equation (2), then enter the equation into MathCAD and the Bode plot of the $G_p\left(s\right)$ can be drawn in Figure 15, where set R_i = 2, T_on = 0.7 μs. In Figure 15, $w_{pout}\approx \frac{1}{R_{LOAD}·C_o} \mathrm{i}.\mathrm{e}., f_{pout}=4.4 \mathrm{k}\mathrm{H}\mathrm{z}$.

Step2: As expressed in Equation (6), set the zero of the compensator $f_z=f_{pout}=4.4 \mathrm{k}\mathrm{H}\mathrm{z}$. From (7), set $f_{p2}\approx 3 \mathrm{M}\mathrm{H}\mathrm{z}$. By Equation (5), suppose $C_t=200 \mathrm{p}\mathrm{F},\mathrm{then} R_t=180 \mathrm{k}\Omega , C_p=200 \mathrm{f}\mathrm{F}$ can be obtained. The compensator gain is set at 60 dB, which can be adjusted according to the entire loop response. Suppose $R_{tho}=1 \mathrm{M}$Ω, then g_m = 1 mA/V, and $f_{p1}\approx 800$ Hz. Finally, substitute all the above numbers into Equation (5), then enter the equation into MathCAD, and the Bode plot of the compensator is drawn in Figure 16 and Figure 17.

Step3: Enter Equation (4) into MathCAD and substitute k with 0.5. The Bode plot of the loop response T(s) is drawn in Figure 16 and Figure 17. It can be seen that the T(s) phase margin is about 25 degrees, DC gain is about 61 dB, and the crossover frequency f_c is about 500 kHz.

5. Simulation Results

5.1. CM-AOT SIMPLIS Schematic Building

In this section, the SIMPLIS tool was used to simulate the proposed CM-AOT scheme. The SIMPLIS schematic is displayed in Figure 18.

5.2. Schematic Stability Analysis

The stability analysis of the proposed scheme was simulated by the SIMPLIS tool, and the results are shown in Figure 19, in which legend label names follow the previous section definition. It can be seen from Figure 19 that the crossover frequency of loop response is about 523 kHz, the phase margin is about 46 degrees, and the DC gain is about 62 dB.

In the previous section, we used MathCAD to draw the Bode plot of the transfer function by numerical approach. However, in this section, we used SIMPLIS to build the circuit architecture and confirm the stability with the Bode plot. In order to find the difference between them, the waveforms in Figure 16, Figure 17, and Figure 19 are redrawn in Figure 20 and Figure 21. From Figure 20 and Figure 21, we found that the results of MathCAD and SIMPLIS have some differences. There are two possible reasons for these differences: 1. Equation (2) has been simplified; 2. the proposed VIC cannot be replaced only by the current gain Ri in Equation (2). Nevertheless, Equation (2) is very close to the real behavior of the system.

From the perspective of stability, A(s) almost determines whether the system is stable or not. As the switching converter contains analog parts and digital parts, the AC stability analysis is not easy. In many cases, non-convergence may occur in AC simulation. To solve the non-convergence issue, the most common method is to run the transient simulation first, then replace the DC point in AC simulation with the DC operation point from transient simulation. At present, many computer-aided design (CAD) software programs, such as LTspice, LTpowerCAD, can help the designers to design the compensator for stability issues. In general, the crossover frequency is higher, and the phase margin is worse. The designer can reduce the loop gain to obtain a good phase margin. However, the loop gain reduction would sacrifice the DC regulation accuracy. The rule of thumb is to recommend the loop gain of 60 dB.

It should be noted that the type selection of compensation network depends on the control mode. In general, the voltage-mode control scheme needs to adopt the type III compensation network, which is fairly complicated. Fortunately, the current-mode control scheme only requires the type II compensation network. Thus, the stability issue would be relieved.

5.3. Transient Performance

Figure 22 shows the load transient waveforms. For the step-up and step-down load current steps between 0.1 A and 0.5 A, the output recovers to within 1% of the expected level 1.8 V in 1.98 μs and 1.6 μs, respectively. In addition, the overshoot and undershoot voltages can also be controlled within 26 mV.

Under 0.5 A load current, the acceptable input range of the proposed converter is 3.0–3.6 V, and the voltage output range is 1.0–2.5 V. The input/output characteristics are shown in Figure 23. Figure 23 shows that the maximum ripple voltage of the converter is 2.5 mV when Vin = 3.6 V and Vo = 2.5 V.

To ensure system reliability, the transient performance of the proposed converter was simulated with the variations of passive/active devices. First, the inductor was simulated with ±5% of variations. The results showed the recovery time would vary from 1.5 μs to 2.0 μs with 4.465 μH to 4.935 μH of the inductance, respectively. Secondly, the recovery time changed from 1.87 μs to 1.3 μs with the gm of the operational amplifier from 0.9 mA/V to 1.1 mA/V, respectively. Thirdly, the time would vary from 1.5 μs to 1.7 μs with −10% to +10% variations of DC gain. These simulation results show that the proposed system is insensitive to the device variations. Therefore, the reliability of the system is expected.

5.4. Load Regulation/Line Regulation

Load regulation is to measure the performance of a power supply. It is the capability to maintain a constant voltage (or current) level on the output despite changes in the load. We expect that a load change causes a small change in output, usually from 3% to 5%. In this paper, under the condition of 1.8 V output voltage with the load current switching from 0.5 A to 0.1 A, the load regulation was calculated by Equation (8). The simulation waveform is shown in Figure 24, and the calculation result is −0.05%.

$$\mathrm{Load}\mathrm{Regulation}=\frac{\Delta V_o}{V_{o@IL=0.5A}}·100\%$$

(8)

Line regulation is the ability of a power supply to maintain a constant output voltage despite changes to the input voltage, as shown in Equation (9). The calculation result is close to 0. As this is a system-level simulation, the simulation results of line regulation are meaningless and cannot reflect the real conditions.

$$\mathrm{Line}\mathrm{Regulation}=\frac{\Delta V_o}{\Delta V_{in}}·100\%$$

(9)

5.5. Performance List

Table 2. Performance summary.

Input voltage		3.0–3.6 V
Output voltage		1.0–2.5 V
Max. output ripple (@Vin = 3.6 V, Vo = 2.5 V)		2.51 mV
Max. load current		0.5 A
Inductor/DCR *		4.7 μH/30 mΩ
Output capacitor/ESR		10 μF/5 mΩ
Transient response @ Vo = 1.8 V	100 mA to 500 mA	1.98 μs
	500 mA to 100 mA	1.6 μs
Transient voltage @ Vo = 1.8 V	Overshoot	23 mV
	Undershoot	26 mV

* DCR: the DC resistance of inductor.

presents the performance of the current-mode adaptive on-time control buck converter. The input voltage range is 3.0–3.6 V. When the output voltage is 1.8 V, and the load current steps between 100 mA and 500 mA, the recovery time is smaller than 2 μs. The performance comparisons with reported converters are listed in

Table 3. Performance comparisons with reported converters.

References	2018 [15]	2020 [41]	2021 [27]	This work
Results	simulation	simulation	measurement	simulation
Control scheme	AOT	AOT	Hysteretic PLL	AOT
Process (μm)	0.35	0.18	0.35	0.35 **
Input voltage (V)	12	3.3–5.0	3.3–3.6	3.0–3.6
Output voltage (V)	1.2	1.8	0.9–2.5	1.0–2.5
Inductor (μH)	1	1.5	4.7	4.7
Output capacitor (μF)	47	20	10	10
Max. load current (mA)	5000	2000	600	500
Load current step (mA)	4000	800	400	400
Undershoot/overshoot (mV)	20/26	13/14	30/60	23/26
Recovery time (μs) (rise/fall)	<3	6/2	2.6/2.2	1.98/1.6

** This work is a system-level simulation with SIMPLIS.

.

6. Conclusions

In this study, an adaptive on-time control buck converter with a novel virtual inductor current circuit was proposed. The modeling approach was derived and sketched by MathCAD and SIMPLIS. This paper describes the design parameters and design procedure in detail. Moreover, a system-level circuit topology was build and verified by SIMPLIS. This study proposed the implementation of the VIC circuit that is compatible with the existing AOT architecture. The sensing point of VIC is more stable than that of ACS in [27]. Hence, the overall performance would be better than [27]. The proposed buck converter can be implemented with TSMC 0.35 μm 2P4M CMOS processes further.