A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS
Abstract
:1. Introduction
2. Proposed ADC Architecture
2.1. Input Network
2.2. Two-Step Flash ADC
3. Circuit Implementation
3.1. Comparator Design for CADC
3.2. Gain-Boosted VTC for FADC
3.3. High-Speed Multi-Phase Clock Generation
3.3.1. Clock Initial Logic
3.3.2. Main Clock Generation
3.3.3. Digitally-Controlled Delay Line
3.3.4. Sub-Clock Generation
4. Measurement Results
5. Conclusions
Funding
Conflicts of Interest
Abbreviations
ADC | Analog-to-Digital Converter |
TI | Time-Interleaved |
SAR | Successive Approximation Register |
S/H | Sample-and-Hold |
C-DAC | Capacitive Digital-to-Analog Converter |
R-DAC | Resistive Digital-to-Analog Converter |
R-string | Resistive string |
THA | Track-and-Hold Amplifier |
CADC | Coarse ADC |
VTC | Voltage-to-Time Converter |
FADC | Fine ADC |
DFF | D-type Flip Flop |
DCDL | Digitally-Controlled Delay Line |
SF | Source Follower |
LVDS | Low Voltage Differential Signaling |
CG | Clock Generator |
DM | Delay Matching |
T/H | Track-and-Hold |
MSB | Most Significant Bit |
LSB | Least Significant Bit |
TDI | Time-Domain Interpolator |
TSPC | True Single Phase Clock |
DNL | Differential Non-Linearity |
INL | Integral Non-Linearity |
SNR | Signal-to-Noise Ratio |
SFDR | Spurious-Free Dynamic Range |
SNDR | Signal-to-Noise and Distortion Ratio |
ERBW | Effective Resolution Bandwidth |
FoM | Figure of Merit |
ENOB | Effective Number of Bits |
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BS [5:4] | B1 [3:0] | B2 [3:0] | B3 [3:0] | B4 [3:0] |
---|---|---|---|---|
00 | BS [3:0] | 0000 | 0000 | 0000 |
01 | 1111 | BS [3:0] | 0000 | 0000 |
10 | 1111 | 1111 | BS [3:0] | 0000 |
11 | 1111 | 1111 | 1111 | BS [3:0] |
This Work | JSSC14 V. Chen [8] | JSSC17 S. Cai [20] | VLSI16 Y. Frans [2] | JSSC17 B. Xu [30] | VLSI19 D. Pfaff [3] | SSCL20 S-J Kim [31] | VLSI21 M. Zhang [32] | |
---|---|---|---|---|---|---|---|---|
Technology (nm) | 40 | 32 SOI | 65 | 16 FinFET | 28 | 7 FinFET | 16 FinFET | 65 |
Architecture | TI Two-Step Flash | TI Flash | TI Multi-bit Search | TI SAR | TI SAR-TDC | TI SAR | TI Flash-TDC | TI Time-domain |
# of channels | 16 | 8 | 8 | 32 | 16 | 32 | 16 | 8 |
Supply (V) | 0.9 | 0.9 | 1.0 | 0.9/1.2/1.8 | 0.85/0.95 | - | 0.9 | 1.0/1.2 |
Resolution (bit) | 6 | 6 | 6 | 8 | 6 | 8 | 8 | 8 |
FS (GS/s) | 20 | 20 | 25 | 28 | 24 | 28 | 20 | 20 |
VIN (mVdiff) | 400 | 300 | 500 | 1200 2 | ~240 | - | 500 | 450 |
DNL/INLMAX (LSB) | 0.45/0.38 | 0.47/0.42 | 0.64/0.60 | - | 0.25/0.22 | - | 0.95/2.39 | - |
SNDR@Nyq. (dB) | 30.1 | 30.7 | 29.7 | 31.5 | 28.9 | 29.4 | 35.4 | 38.8 |
SFDR@Nyq. (dB) | 40.2 | 39.4 | 42 | 39.1 | 41 | 39.1 | - | 52.5 |
ENOB@Nyq. (bit) | 4.71 | 4.81 | 4.62 | 4.9 | 4.51 | 4.6 | 5.6 | 6.15 |
Power (mW) | 56.2 | 69.5 | 88 | 280 | 23 | 150 | 175 | 129.9 |
Active area (mm2) | 0.1 | 0.25 | 0.24 | 2.8 3 | 0.03 | 0.09 4 | 0.1 | 0.22 |
Walden FOM 1 (fJ/conv.-step) | 107.4 | 124.1 | 143 | 325.7 | 42 | 221 | 180 | 91.3 |
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Oh, D.-R. A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS. Electronics 2022, 11, 3052. https://doi.org/10.3390/electronics11193052
Oh D-R. A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS. Electronics. 2022; 11(19):3052. https://doi.org/10.3390/electronics11193052
Chicago/Turabian StyleOh, Dong-Ryeol. 2022. "A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS" Electronics 11, no. 19: 3052. https://doi.org/10.3390/electronics11193052
APA StyleOh, D. -R. (2022). A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS. Electronics, 11(19), 3052. https://doi.org/10.3390/electronics11193052