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Peer-Review Record

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

Electronics 2022, 11(19), 3052; https://doi.org/10.3390/electronics11193052
by Dong-Ryeol Oh
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Reviewer 3: Anonymous
Electronics 2022, 11(19), 3052; https://doi.org/10.3390/electronics11193052
Submission received: 2 September 2022 / Revised: 20 September 2022 / Accepted: 21 September 2022 / Published: 25 September 2022
(This article belongs to the Section Circuit and Signal Processing)

Round 1

Reviewer 1 Report

1Can the skew calibration module of this circuit calibrate the time skew error when inputting multi-frequency signals? How is the effect?

2How effective is the calibration capability of the pseudo-differential comparator in this paper? Please add specific simulation results?

3Please describe in detail how the gain-boosted VTC achieves a more linear gain? And supplement the corresponding formula derivation process?Please add relevant simulation results?

4There is not much description in the text about the shared sample and hold circuit in this design, so how does the author improve the input bandwidth, area and power efficiency of the single-channel ADC? Please add relevant details in detail?

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

This work presented a 6-bit 20GS/s 16ch Time interleaved ADC based on a two-step flash ADC structure. With proposed S/H sharing and reference-embedding techniques, the bandwidth requirement can be met with minimized power consumption. Measured results are clearly presented to demonstrate the overall performance.

 

Although most of the techniques were proposed and covered in the author's previous work in Ref 22. This work added design consideration for a higher sampling speed, with modified S/H and VTC circuits. The overall work is solid and contains extensive consideration and discussion for the reader in the relevant field. Therefore, I recommend publication.

Author Response

I deeply appreciate your positive comments.

Author Response File: Author Response.pdf

Reviewer 3 Report

The paper presents a high speed TI ADC for wireline applications. The paper is well structured and good details are provided.

Below are my comments:

- Please use Frequency rather than # of points as the x-axis in your FFT plot figures 15, 16, etc.

- Fig. 15a. It seems the SNR or the noise floor is worse w/o offset cal. Offset mismatches should cause tones at fixed locations, but here it seems the noise floor has gone up. Any possible explanation for this? Please comment.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

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