Parasitic-Based Model for Characterizing False Turn-On and Switching-Based Voltage Oscillation in Hybrid T-Type Converter

Abstract

High frequency and high voltage switching converters utilizing wide bandgap semiconductors are gaining popularity thanks to their compactness and improved efficiency. However, the faster switching requirements gives rise to new challenges. A key issue is the increased oscillation of the drain–source voltage caused by the switching action of the complementary switch in the same phase or change of state of the other phase switches. The voltage stress caused by these oscillations can damage the switch. Furthermore, the high dv/dt during turning-on of one switch might result in false turn-on of the complementary switch due to the miller effect. In this paper, these issues are investigated in a T-type converter through analytical and experimental analysis. Based on the proposed analytical approach, simple and cost-wise solutions utilizing an optimum design of gate driver circuits and circuit layout modifications can be developed to cope with the aforementioned issues. A comprehensive analytical model of the converter with consideration of parasitic capacitances and inductances is developed. By performing sensitivity analysis on the model, the effect of the parasitic parameters on the drain–source voltage oscillation and gate–source voltage amplitude in case of false turn-on is studied. The validity of the model is then assessed through numerical simulations and experimental results.

1. Introduction

Silicon carbide (SiC) semiconductors favor faster switching, lower switching loss and lower turn-on voltage compared with the traditional silicon technology [1,2,3]. The fast-switching capability of the SiC switches provide the opportunity for developing power electronic converters with high switching frequency and high voltage ratings. Through boosting the switching frequency, the passive components of the converters can be shrunk, hence offering compact and high power density converter design [4,5]. Thanks to the high switching capability of SiC, they can be used in resonant converters, which are widely employed in various applications like electric vehicle battery chargers [6], drive systems [7], and V2X power converters [8]. Furthermore, SiC semiconductors are able to maintain higher junction temperature, which makes them suitable candidates for the compact power electronic converters in integrated motor drive applications [9]. Electro-thermal modeling of SiC-based converters for different power range has been studied in the literature [10,11,12] in order to improve the thermal performance of such converters.

Despite the aforementioned superior characteristics, the application of SiC semiconductors in high voltage/high frequency converters creates new issues [13]. On the one hand, the voltage overshoot across the switch’s drain–source terminals is higher due to the ultrafast switching (high dV/dt) [14]. The voltage overshoot stresses the switch and can damage the switch if it exceeds the switch voltage rating. On the other hand, unintentional voltage oscillations across the gate–source of a switch during turning-on of another switch might give rise to false turn-on [15,16]. SiC switches are more prone to such false turn-on due to the lower turn-on threshold voltage [17]. False turn-on contributes to cross conduction across two switches in a leg, which increases the losses and might even result in switch failure due to overcurrent [18]. Both drain–source voltage overshoot and false turn-on issues are dependent on the parasitic capacitances and inductances in the circuit layout.

In addition to the abovementioned issues, another challenge is associated with three-phase compact converters which are used in high-power, high-frequency application [19]. In this case, a change in the switching state of switches in one phase gives rise to drain–source voltage oscillations in the switches of the other phases [20,21]. This may have a negative impact on the switch voltage blocking and load current quality. This issue elevates in the case of three-phase PMs, which increase the power density through compact design [22]. In such a compact design, the mutual inductance/capacitance between each two phases of the three-phase converter are intensified, hence elevating the cross-phase voltage oscillations [23]. These oscillations can be mitigated using an active/passive snubber circuit [24,25].

The former issue, false turn-on, can be mitigated using an active Miller clamp technique in the gate driver [26,27]. However, this solution requires a gate driver design specific to the switch characteristics, which increases the cost [28]. Additionally, the reliability of this approach may be compromised depending on the circuit layout [29,30]. An extra isolated voltage source can be connected to the gate–source capacitor during the switch turn-off to maintain the gate–source voltage at less than the turn-on threshold [31]. Despite the improved reliability, the mentioned protection circuit is not cost effective [31]. The drain–source voltage overshoot can be limited within the safe range using a snubber circuit [32,33,34]. However, the conventional snubber configurations cannot be used in high-frequency applications because of the limitation in power loss and switching speed [35,36,37]. In practice, the issues associated with the voltage overshoot may be resolved slightly in the converter design stage by employing suitable SiC switches as well as a low parasitic power module (PM) and a PCB layout design [38,39].

Prior to introducing costly solutions such as snubbers, modified gate driver designs, and special circuit layouts, it is important to clarify the necessity of such solutions. A compact electrothermal model has been presented in [40] to characterize the SiC switch, where the whole circuit parasitic effects was not fully considered. Experimental characterization of the SiC switch and its body diode is also presented in [12] using a double pulse test setup, as well as a temperature-dependent physical thermal model in [41]. Although, the mentioned approaches are usable to precisely switch characteristic detection, proposing a general circuit model to determine the impact of the non-optimal layout parameters on the voltage stress and oscillation across the pre-characterized SiC switch is of interest. This paper proposes an analytical study of the mentioned issues to help quantify the drain–source voltage overshoot and gate–source voltage oscillations. The analytical results provide a baseline for assessment of the safe converter operation despite the presence of the drain–source voltage overshoot and the possibility of false turn-on. Based on the proposed analytical approach, simple and cost-wise solutions utilizing an optimum design of gate driver circuits and circuit layout modifications can be developed. This way, the cost of the converter can be reduced without compromising the performance.

The specific contributions of the paper are as follows.

• A general switching model of three-phase hybrid T-Type converter, consisting of SiC MOSFETs and Si IGBTs, is developed, which has not been studied before. This type of front-end converter is chosen due to the comparison results yielded from [42]. All possible effective parasitic components, which are modeled as stray inductances and switch intrinsic capacitors, are considered in the model. This makes a comprehensive model to be applied to other power electronic converter types.
• Unlike the conventional analytical model of the converter, sensitivity analysis is carried out here to investigate the impact of parasitic capacitances and inductances on the damping and natural oscillation frequency of the switch drain–source and gate–source voltages, simultaneously. This way, the most critical parasitic parameters affecting voltage overshoot and false turn-on are determined using the same analytical model.
• Regarding the proposed built compact converter, a new issue has been raised which is affecting the voltage oscillation characteristics across the switch. Accordingly, the effect of the switching in one phase on the drain–source voltage of the switches in the other phases is investigated in detail by simulating the equivalent circuit model, which was not completely focused in the literature.
• Simulation and experimental results have been carried out to verify the analytical model.

The rest of the paper is organized as follows. The possibility of false turn-on and drain–source voltage oscillation in a T-type converter with consideration of different modulation scenarios is investigated in Section 2. In Section 3, a detailed analytical model of one of the phases of the T-type converter is derived. In Section 4, the analytical model is analyzed to identify the sensitivity of damping and natural oscillation frequency on the parasitic parameters. In Section 5, the single-phase model is extended to three phases to analyze the impact of switching in one phase on the performance of the other phases. Experimental results based on a hybrid T-type converter are presented in Section 6 to validate the analytical and numerical results. Section 7 concludes the paper.

2. Topology-Based Miller Plateau Analysis

To illustrate the mechanism of false turn-on, an active T-type rectifier is considered in this study. The reason for choosing this converter topology is its acceptability in the industry as it has the best compromise between high power density and efficiency, as well as the possibility of reaching the pure sinusoidal supply current with a smaller input filter [36]. The topology of a single-phase active T-Type converter is shown in Figure 1. Switches Q₁ and Q₂ should maintain a high breakdown voltage that is equal to the DC link voltage (2V_DC) while the breakdown voltage cuts in half (V_DC) for the zero-level switches of Q₃ and Q₄. Therefore, SiC MOSFETs are used for Q₁ and Q₂ switches, while Q₃ and Q₄ are Si IGBT.

The zero-voltage level is provided using two back-to-back IGBTs with the same source and different command gate signals. The T-type converter is generally composed of two half-bridges (see Figure 1). The upper side half-bridge loop (red color) includes complimentary switches Q₁ and Q₃ while the lower side half-bridge (blue color) includes Q₂ and Q₄ as the complimentary set of switches. The modulation algorithm depicted in Figure 2 shows that in the positive half cycle of the reference waveform (voltage or current depending on the application), the lower side switch of the leg (Q₂) is always off. Accordingly, during the switching of the upper half-bridge at the positive cycle, switch Q₄ is on. Thus, the current can be conducted in both directions through Q₄. The same situation is considered for the lower half-bridge. According to the control algorithm, switch Q₁ is off during the whole negative half cycle of the reference waveform. Hence, the Q₃ is always on at this period and can conduct the bi-directional current through itself. Also, the dead time is defined at switching state changes.

As mentioned, to protect both half-bridges from shoot-through issues, the dead time is necessary to be considered for switching transient between Q₁ and Q₃, as well as switching states for Q₂ and Q₄. Nevertheless, each switch suffers from false turn-on occurrence after turning-on of the complimentary switch, which also causes unwanted shoot-through. In this paper, the Miller effect is investigated in three cases presented below:

(1)

For the upper side half-bridge, where turning-on of SiC MOSFET (Q₁) affects false turn-on of Si IGBT (Q₃);

(2)

For the lower side half-bridge, where turning-on of Si IGBT (Q₄) affects false turn-on of SiC MOSFET (Q₂);

(3)

For leg switches, where turning-on of SiC MOSFET (Q₁) affects false turn-on of SiC MOSFET (Q₂).

Accordingly, for cases 1 and 2, the gate–source voltage oscillations of switches Q₃ and Q₂ are investigated during the transient turning-on of switches Q₁ and Q₄, respectively. In addition, for case 3, the gate–source voltage oscillations of switch Q₂ should be monitored during the transient turning-on of switch Q₁. During the transient, in all cases, the drain voltage variation of the target switch equals 0.5 V_dc. This is found by referring to the switching modulation of the T-type converter. Although the electric model and circuit equations of case 3 are the same as the others, this case is the most extreme one. The reason is that case 3 has fewer switches in the loop, which results in less loop resistance and a lower damping ratio. This means the oscillation amplitude and the possibility of false turning-on magnifies in case 3. In addition, the turn-on threshold voltage of SiC MOSFET is lower than IGBT, which leads case 3 to be more susceptible to a false turn-on. Therefore, as the worst one, case 3 was chosen to be investigated in this paper.

Switch Q₂ is supposed to be off in theory in the transient time of Q₁ turning on. However, the following analysis shows that the induced voltage across the gate–source capacitor of Switch Q₂ may even exceed the turn-on threshold voltage, which results in cross conduction. Repeating the problem in thousands of cycles will damage and even burn the switches. For demonstrative purposes, the parasitic capacitances of switches Q₂, Q₃, and Q₄ are illustrated in Figure 3. Just before a false turn-on occurs, Q₂ is in its off state while V_drv,2 is considered to be grounded. When Q₁ turns on, the drain terminal of Q₂ faces a high dv/dt, while the source of Q₂ is directly connected to the ground through a leakage inductance. High dv/dt at drain terminal of Q₂ leads to a current passing through gate–drain capacitance (C_gd2). The reason is that before Q₁ turns on, Q₃ and Q₄ conducted the current. Accordingly, the drain voltage was V_dc when Q₃ and Q₄ were conducting. After turning on Q₁, the drain voltage jumps to 2V_dc, which results in current flow through Q₂ gate resistance, shown as R_G2 in Figure 3. Exceeding gate resistance voltage from the turn-on threshold voltage of Q₂, this switch is pushed to cross conducting, mistakenly causing a significant switching loss. More detailed analysis of false turn-on in T-type converters is still challenging in order to improve the reliable performance of the next generation ultra-high frequency converters which will use WBG switches.

3. Developed Model-Based Study

This paper aims to reveal the effective switch’s parameters or PCB layout leakages on false turn-on and voltage oscillation characteristics across the drain–source of the switch. Here, this is carried out by assessing the dependency of the natural frequency, ω_n, and damping ratio, ζ, on the switch’s intrinsic parameters (C_ds, C_gs, C_gd) and circuit leakage inductances. The simple and developed models considering all parasitics are analyzed mathematically in the following.

3.1. Simple Circuit Model

Based on the abovementioned, an abrupt turn-on of Q₁ results in high positive voltage derivative at the drain terminal of Q₂. Q₁ turn-on time depends on the turn-on gate resistance the switch’s intrinsic capacitances. In addition, the gate–source voltage of Q₂ during turning-on of Q₁ is affected by the gate resistance and C_gd dv/dt, which is considered as induced current. The well-known first-order circuit at this transient time (Q₁ turn-on) is illustrated in Figure 4, to study parasitic negative effects on induced gate–source voltage amplitude. The transfer function of the mentioned model using the Laplace form is as follows:

$$\frac{V_{gs2}\left(s\right)}{V_{ds2}\left(s\right)}=\frac{s{R}_{G2}{C}_{gd2}}{1+s{R}_{G2}\left(C_{gd2}+C_{gs2}\right)}$$

(1)

V_ds2(s) and V_gs2(s) are the drain–source voltage and gate–source voltage of switch Q₂, respectively. Variable s in Equation (1) can be replaced by jω to achieve the frequency response function as:

$$\frac{V_{gs2}\left(j\omega \right)}{V_{ds2}\left(j\omega \right)}=\frac{j\omega R_{G2}{C}_{gd2}}{1+j\omega R_{G2}\left(C_{gd2}+C_{gs2}\right)}.$$

(2)

In order to decrease false turn-on possibility, the absolute gain value of Equation (2) needs to be as low as possible. This guarantees V_gs2 to be less than the turn-on threshold voltage of Q₂. Referring to Equation (2), it is obvious that false turn-on possibility may decrease by lower gate–drain capacitor, C_gd2 while it increases by low gate–source capacitor (C_gs2) values. The experimental and analytical results in next sections will verify the findings here.

It should be mentioned that the model illustrated in Figure 4 is not complete due to lack of drain–source capacitor, C_ds2, and also the circuit leakage inductances. The latter has a considerable effect on V_ds oscillation in some circuit topologies [43]. The following developed model is investigated in the circuit using SiC switches to comprehensively evaluate which condition is more prone to the occurrence of the false turn-on and voltage oscillation.

3.2. Higher Order False Turn-On Model Considering Parasitic Parameters

The C_gd dV/dt circuit shown in Figure 5 is used to analytically and experimentally investigation of SiC MOSFET’s false turn-on in one leg. In theory and simulation, the ON and OFF states of Q₁ are modeled by a pulsating voltage source series to ON resistance whose value can be extracted from the switch datasheet document, in practice. The value of R₁ is adjusted during the analysis such that the in-mind dv/dt is applied to the drain terminal of Q₂. The gate terminal of the Q₂ is connected to the ground through a gate resistor, R_G2. The induced gate–source voltage (V_gs2) of Q₂ is studied by changing dv/dt at the drain terminal of Q₂. Using this technique, the maximum eligible dv/dt across the switch can be obtained in which the switch is still free of cross conduction.

The circuit shown in Figure 5a is the complete model of the structure illustrated in Figure 3, which includes all the parasitic capacitors of the switch as a result of using DOL technology for the die switch planting process, as well as the parasitic inductance because of the single layer conducting track. Figure 5b illustrates a rearrangement of the elements in Figure 5a in which Q₂ is off. Now, the step responses of both V_gs2 and V_ds2 in terms of the input step voltage are derived. By applying KCL to nodes, the following equations can be extracted:

$$\frac{V_p-V_{D2}}{s{L}_{total}+R_{total}}=s{V}_{ds2}{C}_{ds2}+s{V}_{gd2}{C}_{gd2},$$

(3)

$$s{V}_{gd2}{C}_{gd2}=V_{gs2}s{C}_{gs2}+\frac{V_{G2}}{s{L}_{G2}+R_{G2}},$$

(4)

$$\frac{V_{S2}}{s{L}_{l-}+R_{l-}}=s{V}_{ds2}{C}_{ds2}+s{V}_{gs2}{C}_{gs2},$$

(5)

$$\frac{V_{G2}-V_{GS,tran.}}{S{L}_{G2}}=\frac{V_{GS,tran.}}{R_{G2}},$$

(6)

$$L_{total}=L_{l+}+L_{mid}+L_{+}+L_{-},$$

(7)

$$R_{total}=R_{l+}+R_{mid}+R_{+}+R_{-},$$

(8)

where $L_{l\pm }$, $L_{mid}$, and $L_{\pm }$ are the leakage inductances of the upper and lower side of the leg, leakage inductance at the middle of the leg between two switches and stray inductance of the conductor from DC link to the leg, respectively. The same index is also used for the parasitic resistances. The whole system parameters which are modeled in the simulations and used in analysis are depicted in

Table 1. System parameters of the system model.

Parameter	Definition	Value	Parameter	Definition	Value
L+	Upper side conductor leakage inductance	12.5 nH	L−	Lower side conductor inductance	12.5 nH
Rleak+	Upper side conductor leakage resistance	12.5 mΩ	Rleak.−	Lower side conductor resistance	12.5 mΩ
Lmid	Leg inductance between the switches	5 nH	Rmid	Leg resistance between the switches	5 mΩ
Ll+	Leg inductance on top of the upper switch	5 nH	Ll−	Leg inductance under the lower switch	5 nH
Rl+	Leg resistance on top of the upper switch	5 mΩ	Rl−	Leg resistance under the lower switch	5 mΩ
LG2	Gate on/off stray inductance	0.5 nH	RG2,on	Gate ON-resistance	15.6 Ω
Cgd2	Gate–Drain capacitor for SiC	10 pF	Cgs2	Gate–Source capacitor for SiC	1300 pF
Cds2	Drain–Source capacitor for SiC	50 pF	Ron,Q1	SiC MOSFET on resistance	75 mΩ

.

The values of parasitic capacitances are extracted from the datasheet of switches that are used in the experimental setup. Furthermore, the data regarding the leakage inductances is obtained through simulations of the entire PM using Ansys Q3D, employing the same size and material parameters, as depicted in Figure 6. This PM contains die switches for both T-Type converter and inverter.

Because of using Kelvin connection at source point of each die switch, the value of Ll− is considered near zero in analysis. Based on Equations (3)–(6) and by considering V_p as the input step function, the step response of V_ds2 and V_gs2 is calculated. Then, the results are plotted as shown in Figure 7a,b. It is noteworthy that the initial value of the step voltage is 400 V as IGBTs Q₃ and Q₄ conduct. In addition, the final value of Q₂ drain voltage (V_D2) is 800 V instantaneously after Q₁ turns on. Shown in Figure 7a, V_ds oscillates about 175 ns and then it reaches 800 V in steady state. Also, V_gs in Figure 7b jumps to approximately 2.5 V at transient time of false turn-on. Once after reaching the peak amplitude, V_gs falls below the threshold voltage for turn-on (v_th = 2.5 V). The results of Figure 7 are in a good agreement with the experimental results obtained in Section 6. The proposed model is also discussed with more details in the following section.

4. Model Discussion

4.1. Sensitivity Analysis of ω_n and ζ

The general transfer function of V_ds, based on the proposed model and its corresponding Equations (3)–(8), can be obtained as follows

$${\mathrm{V}}_{\mathrm{ds}}\left(\mathrm{s}\right)=\frac{\left(\mathrm{s}+{\mathrm{z}}_1\right)\left(\mathrm{s}+{\mathrm{z}}_2\right)\left({\mathrm{s}}^2+2\mathsf{\alpha }\mathrm{s}+\mathsf{\beta }\right)}{\mathrm{s}\left(\mathrm{s}+{\mathrm{p}}_1\right)\left(\mathrm{s}+{\mathrm{p}}_2\right)\left({\mathrm{s}}^2+2{\mathsf{\zeta }\mathsf{\omega }}_{\mathrm{n}}\mathrm{s}+{\mathsf{\omega }}_{\mathrm{n}}^2\right)}$$

(9)

where z₁, z₂ and p₁, p₂ are the zeros and poles, respectively, and α and β are two constants in the transfer function. Also, in Equation (9), ω_n and ζ are the natural frequency and damping ratio, respectively, which determine the frequency of oscillations as well as the convergence speed of the system response. These two parameters are affected by the SiC MOSFET’s parasitic components. To study the sensitivity of the natural frequency and damping ratio on the parasitic inductances and capacitances of the device, variation of each parasitic element is examined on Equation (9).

Figure 8 depicts the impact of the switch’s parasitic capacitances on the damping ratio. Due to the sensitivity analysis, more focus has been carried out on the curve slope rather than its amplitude. Parameters of switch Q₂ have been considered in this study. In Figure 8, the slopes for C_ds2 and C_gd2 are negative up to certain values and will be increasingly positive beyond them. This means that increasing C_gd2 and C_ds2 first increases and then decreases the V_ds2 oscillations. However, the slope for C_gs2 is relatively constant, which shows that C_gs2 has no considerable impact on damping ratio. To ensure the same curve trend for C_gs2 due to the possibility of bifurcation, more values above the nominal C_gs2 (1.3 nF) are considered in the plot. Nevertheless, the same result has been concluded, which shows negligible impact of C_gs2 on damping ratio.

On the other hand, referring to Figure 9, C_ds2 and C_gd2 have a sensible impact on the natural frequency. Among them, C_gd2 is more effective. The negative slope in these two curves shows that the oscillation frequency of V_ds2 across Q₂ will be reduced by increasing C_ds2 and C_gd2. However, C_gs2 has a little impact on the oscillation’s frequency.

The result in Figure 10 clarifies these findings. In this figure, V_ds2 is plotted for C_gd2 = 2 nF which is higher than the one in nominal C_gd2 (Figure 7a), as mentioned in Table 1. Comparing Figure 10 to Figure 7a, it can be seen that the settling time is less in Figure 10. This means bigger C_gd2 leads to higher damping ratio with less oscillatory frequency. In addition, the peak–peak voltage oscillation (V_p-p) decreases to 250 V in Figure 10, while the value is 400 V in Figure 7a. Since the overshoot amplitude has an inverse relation with the damping ratio, this finding in Figure 10 is in good agreement with the findings extracted from Figure 8 and Figure 9, which show that increasing C_gd2 will result in an increment of the damping ratio and a decrement of the natural frequency.

The dependencies of the natural frequency and the damping ratio of V_ds on the parasitic inductors are presented in Figure 11 and Figure 12, respectively. Figure 11 shows a decrease in the damping ratio when the major loop inductance, L_total, is increased. On the other hand, the increment of the source inductance, L_l−, is followed by a damping ratio increase. Based on this finding, source inductance may have a positive effect against false turn-on of switch in some cases. In return, the effect of gate inductance, L_G, on the damping ratio of V_ds can be neglected. Regarding Figure 12, it is obvious that the natural frequency of V_ds decreases by increasing L_total and L_l−. On the other hand, L_G has no significant effect on the natural frequency. Comparison of Figure 8 and Figure 9 with Figure 11 and Figure 12 demonstrates both natural frequency and damping ratio are more influenced by the parasitic capacitances, as the slope variations are bigger in Figure 8 and Figure 9.

4.2. Dependency of False Turn-On on Parasitics

In this part, the dependency of false turn-on due to the induced V_gs on the parasitic capacitances is analyzed. Both simulation and theoretical results are illustrated in Figure 13 in the form of the gate–source peak amplitude. As seen, there exists an appropriate agreement among them. In addition, Figure 13 verifies that during false turn-on, C_gd has a prominent impact on the induced gate–source voltage. In addition, during false turn-on, a roughly piecewise linear relationship exists between C_gd and the gate–source voltage. This observation agrees with the studies previously presented in Section 3. It should be mentioned that 10 pF is the nominal value of C_gd. Therefore, in this analysis, the nominal value is considered by extrapolation which is impractical for SiC. This analysis tries to provide the insight of how substantial the effect of C_gd could be even with a decreased value. Further analysis of Figure 13 determines the increased value of C_gs is followed by a decrement of the magnitude of the induced gate–source voltage during false turn-on. This observation again is in appropriate compliance with the studies previously presented in Section 3.

V_gs waveform is analytically-drawn for the increased C_gs to 13 nF as shown in Figure 14. Comparing with Figure 7b, it is found that the peak value of V_gs is roughly 0.5 V, which is only 20% of peak voltage at nominal C_gs (1.3 nF). This finding can also be verified by referring to Figure 13c.

In a similar way, Figure 15 demonstrates the impact of C_ds2 on V_gs for the increased C_ds2 to 5 nF compared to nominal C_ds2, which is mentioned in Table 1. Figure 15 shows that increasing C_ds2 will result in the decrement of the induced gate–source voltage. This could not manifest based on the response function of the simple model presented in Equation (2). The effect of C_ds for false turn-on is not as prominent as C_gs, but it is still required to be considered. It is considerable that increasing capacitance generally results in an increment of switching losses during the switches turn-off/on. Therefore, in high dv/dt circuits, the values of C_gs and C_ds are required to be optimized to minimizing the total switching losses. Accordingly, their beneficial aspects during false turn-on are not completely offset by their parasitic effects during intended turn-off and turn-on. Experimental studies are presented in the next section to validate the reported analytical results.

5. Model Extension to Three-Phase T-Type Converter

The single-phase converter had been investigated in previous sections. The same challenges are assumable for each phase of three-phases system which is shown in Figure 16. In addition, in inverter mode, the voltage of each phase (V_phX = V_phx − V_M) will be affected by the switching of two other phases. This issue is reflected in form of voltage oscillation across V_phX. At each time, the low-frequency reference voltage (V_ref) applying to one phase (leg 1, 2, or 3) is in opposite polarity to the others depending on the phase angle.

Table 2. Polarity of reference voltage for each phase.

Vref for:
Phase 1/Sign		Phase 2/Sign		Phase 3/Sign
θ1 = 0–60°	+	120°–180°	+	240°–300°	-
θ1 = 60°–120°	+	180°–240°	-	300°–360°	-
θ1 = 120°–180°	+	240°–300°	-	0–60°	+

shows the sign of reference voltages of the three phases over the positive half cycle of phase 1. The same situation will occur for the negative half cycle.

For 0° to 60° degrees of V_ref in phase 1 (V_ref,1), the effect of switching in legs 2 and 3 on V_ph1 is investigated as a scenario. For simplification, ON and OFF state of the switch can be modeled by R_on and charged capacitor of C_ds, respectively. Accordingly, the circuit schematics before and after changes in the switching state of both legs 2 and 3 are shown in Figure 17. R_on, C_ds, R_on’, and C_ds’ illustrate MOSFET and IGBT ON and OFF state, respectively. Regarding Table 2, SiC MOSFET Q₂₁ turns off and Si IGBT Q₂₃ turns on for leg 2 only. In similar way, SiC MOSFET Q₃₂ turns off while Si IGBT Q₃₄ turns on in leg 3 only.

Like the circuit analysis in Section 3, Figure 5, a simplified circuit schematic by equating the switching state changes to pulse voltage across V_ph2,3 and midpoint (M) is shown in Figure 18 for θ₁ = 0°. Here, the effect of switching state changes of leg 1 on V_ph1 is not considered. The resulted voltage oscillation in this situation is obvious due to the leakage inductance of the route.

Table 3. Parameters of the system presented in Figure 18.

Parameter	Definition	Value	Parameter	Definition	Value
L+	Upper side conductor leakage inductance	40 nH	L−	Conductor leakage inductance	40 nH
Ron,11	SiC MOSFET ON-resistance	75 mΩ	R’on,14	Si IGBT ON-resistance	75 mΩ
Cds31, Cds22, Cds12	SiC MOSFET drain–source capacity	550 pF	C’ds13	Si IGBT drain–source capacity	55 pF

shows the amount of the parasitic components in Figure 18 and switches’ parameters including C_ds and ON-resistance, which are employed for model simulation. It is noteworthy that the duty cycles of V_P,ph2 and V_P,ph3 depend on the exact phase degree of the related reference voltages, V_ref,2 and V_ref,3, which are 120° different in phase. As an example, for θ₁ = 0°, 30° and 60°, the corresponding duty cycles of V_P,ph2 and V_P,ph3 are 0.86, 0.5, 0 and 0.86, 1, 0.86, respectively.

Figure 19 depicts the voltage oscillation of V_ph1 with respect to switching state changes for two other phases (ph₂ and ph₃) when θ₁ = 0°, 30°, and 60°. Based on the superposition principle, V_ph1 contains both oscillations of each V_ph2 and V_ph3 which occur in different moments depending on θ₁. For better demonstration, the amount of θ₁ is kept constant for 6 high frequency cycles (6T_s). This is acceptable due to the slow changes of θ₁ comparing the switching speed.

For each amount of θ₁, the equivalent pulse voltage of phases 2 and 3 is illustrated, as well as the oscillation across phase 1 voltage (V_ph1) resulting by switching state changes in two other phases. The total results are also shown in black color which is the integration of two distinct oscillation. There is an appropriate agreement with the superposition principle which can be applied for such simplified linear circuit. It is obvious that by any change in the switching state of phases 2 and 3, V_ph1 oscillates around V_DC. Without using a suitable filter at the output, this oscillation may be transferred to the load in stand-alone inverter mode, which is undesirable. Thus, this matter is taken into consideration in filter design for three-phase applications.

6. Experimental Evaluation

6.1. Double Pulse Setup Test

To authenticate the analytical and simulation-based investigations, the circuit depicted in Figure 5 underwent experimental scrutiny. This examination employed a SiC MOSFET for the legs and back-to-back Si IGBTs to attain a zero-voltage level, as illustrated in Figure 20. The three-phase T-Type converter utilized in this configuration served as the rectifier section of the entire Front-End converter, renowned for its high power density.

For characterization, the Tektronix AFG 31000 double pulse generator (Tektronix company, Portland, OR, USA) was employed to generate two pulses with adjustable duty cycles based on the switch current rate. This facilitated the characterization of both the gate driving circuit and the under-test switch. The current behavior of inductor L during the double pulse test (DPT) is depicted in Figure 21, where the inductance current exhibited a ramp-like increase upon switch activation and decreased slightly during the off time due to the voltage drop across the freewheeling diode. Subsequently, detailed investigation of the obtained V_gs in DPT was conducted to verify the theoretical findings.

Figure 22 considers all potential scenarios for false turn-on in the experimental testing circuits, with theoretical analysis and simulations focusing on case 3, regarded as the most critical scenario, wherein the false turn-on of switch Q₂ is investigated during the activation of switch Q₁.

6.2. False Turn-On Evaluation

To address all three potential scenarios outlined previously, identical circuits were subjected to experimental testing. Figure 23 presents the experimental outcomes of the test system, featuring V_DC = 400 V and DPT inductance L = 220 uH. This figure depicts the gate–source voltage of the two switches with the highest likelihood of activation, alongside the gate–source and drain–source voltages of the switch undergoing the double pulse application. The results encompass all three previously introduced cases in Section 2. Consequently, switches Q₁ and Q₂ were observed in case 1, where switch Q₃ underwent DPT testing. Additionally, switches Q₁ and Q₄ were monitored in case 2, where the double pulse was applied to switch Q₂. Similarly, switches Q₁ and Q₃ were scrutinized in case 3, involving the application of the double pulse to the gate–source of switch Q₁.

Across all three cases within the experimental setup (Figure 23a–c) and in case 3 of the analysis (Figure 7b), the peak value of the gate–source voltage was approximately 2.5 V. To facilitate better comparison, subsequent analysis exclusively concentrated on the experimental result of case 3.

Figure 24 provides a magnified perspective of the V_gs in Figure 23c, highlighting two turning-on transients (number 1: first turn-on; number 2: second turn-on) for clarity. Comparing the analytical/simulation model with experimental results reveals reasonable agreement. The peak value of the gate–source voltage in both experimental and analytical/simulation results is approximately 2.4 V. Notably, in the analytical model, the gate–source voltage reaches its first minimum value at 100 ns, whereas experimentally, this occurs slightly later, suggesting a slower experimental result attributed to larger circuit parasitics due to the new layout design. Nonetheless, the trends and shapes of the experimental waveforms reasonably align with the analytical/simulation results. It is worth noting that false turn-on during the falling edge of the applied gate–source pulses is less significant due to the deadtime between switching state changes, making monitoring of the rising edge of the pulses (indicated by dash loops) essential. In practical settings, induced gate–source voltage amplitude and voltage oscillation across switches are halved compared to DPT tests, as no inductance is placed in parallel to the switch, thus eliminating current conduction through the corresponding freewheeling diode during turning-off of the complementary switch. Consequently, the sensed step voltage across the switch in case 3 in real operation was V_DC (400 V) rather than 2V_DC (800 V), as depicted in Figure 7a.

In all cases, it was observed that the damping ratio of the drain–source voltage was higher during the second turn-on. This phenomenon occurs because before the second turn-on, the freewheeling diode of the switch, operating in parallel with inductance L, conducts the circulating current. Consequently, this diode effectively clamps the phase voltage to 2V_DC in case 1, V_DC in case 2, and 0 V in case 3. Prior to the first turn-on, as no current flows through the freewheeling diode, the drain–source voltage cannot be clamped by it.

6.3. Voltage Stress Evaluation

In this subsection, we focus on cases 2 and 3, examining the corresponding circuits depicted in Figure 22b,c, respectively. Theoretical analysis is conducted specifically for case 3, investigating the drain–source voltage (V_ds) of SiC switch Q₂ during the activation of Q₁. To assess the impact of intrinsic capacitors, as depicted in Figure 8 and Figure 9, another switch with different capacitances—C_ds, C_gs, and C_gd—compared to Q₂, requires investigation. Hence, case 2 was explored alongside case 3 to gather experimental results for Si switch Q₄, facilitating a comparison with the results of SiC switch Q₂. Notably, the differences in drain–source characteristics between Q₂ and Q₄ are primarily attributed to the intrinsic capacitors, as both switches received identical gating pulses with matching turn-on/off times and dv/dt rates. Subsequent analysis compared the results with analytical findings, focusing on C_ds as the sole varying parameter. Figure 25 illustrates the V_gs and V_ds of switches Q₂ and Q₄ in case 2, along with switches Q₁ and Q₂ in case 3, highlighting the V_ds at two rising edges of the gate–source pulses (indicated by dash loops) in Figure 26. Notably, V_ds overshoot for Q₂ in case 3 was 16% and 8% during the first and second rising edges, respectively, while these figures stood at 28% and 17% for Q₄ in case 2. This indicates a higher damping ratio of V_ds for Q₂, attributed to its smaller C_ds compared to Q₄. Such observations align well with analytical results, as showcased in Figure 8a, where an increase in C_ds up to 1.5 nF results in a decrease in damping ratio. Additionally, the natural frequency of V_ds oscillations remains similar for both switches, owing to the closely matched values of C_gd, which significantly influences ω_n. This correlation between experimental and analytical findings underscores the higher voltage overshoot during the first turn-on in both cases due to the absence of voltage clamping, a feature provided before the second turn-on by the switch’s body diode in parallel to the inductance, L. Overall, the observed overshoot amplitude and natural frequency in practice are generally lower than those predicted by theory, primarily due to anticipated parasitic effects associated with the PM layout and technology.

The analytical model exhibits a higher overshoot in the drain–source voltage compared to the experimental measurements, with the time needed to reach a steady state slightly prolonged in the experimental scenario. This suggests that the damping ratio in the experimental data surpasses that of the analytical model, while the natural frequency in the experiment was lower than predicted by the analytical model. This discrepancy is likely attributed to unaccounted-for experimental circuit parasitics in the analytical model.

6.4. Effects of dv/dt

Examining the effect of dv/dt involves altering the turn-on time of the switch, which is directly influenced by the turn-on gate resistance (R_G,on). By reducing R_G,on, an increase in dv/dt can be achieved. While previous plots were based on R_G,on = 15.6 Ω, Figure 27 presents V_ds oscillation overshoot for varying R_G,on values. Specifically, the V_ds2 waveform for a new R_G,on = 11.5 Ω was compared with R_G,on = 15.6 Ω during the first and second Q₁ turn-on transients in case 3. It is evident that lower R_G,on values result in higher voltage overshoot across the switch, indicating a correlation with increased dv/dt. Additionally, the overshoot amplitude is lower during the second turn-on transient for both turn-on gate resistance values due to this effect. Figure 28 illustrates the gate–source induced voltage for switch Q₂ in case 3 for R_G,on = 15.6 Ω and R_G,on = 11.5 Ω. Notably, decreasing turn-on gate resistance leads to an increase in induced V_gs, thereby escalating the risk of false turn-on with a higher voltage change rate. Consequently, the peak value of V_gs is 2.4 V for R_G,on = 15.6 Ω, whereas it rises to 3.2 V for R_G,on = 11.5 Ω, exceeding the safe range. This experiment aims to determine the maximum allowable dv/dt considering the induced voltage that might trigger false turn-on, ensuring it remains below the switch’s turn-on threshold voltage. Finally, Figure 29 showcases the DPT test waveform in a comprehensive double pulse testing scenario with R_G,on = 11.5 Ω.

7. Conclusions

An analytical methodology for evaluating drain–source voltage oscillation and false turn-on issue in T-Type converter with hybrid structure (SiC MOSFET, Si IGBT) has been presented. In this method, the equivalent circuit of the converter with consideration of parasitic capacitances and inductances is used to derive a mathematical model of the converter. The voltage stress and the possibility of false turn-on depend on the overshoot and duration of oscillations, which are a function of the damping ratio and natural frequency. Sensitivity analysis based on the developed model is carried out to investigate the impact of parasitic parameters on the drain–source and gate–source voltages’ damping ratio and natural frequency. The sensitivity analysis results show that the impact of parasitic capacitances on the voltage oscillations across both gate–source and drain–source is greater than the parasitic inductances. Furthermore, the most critical parameter affecting the possibility of false turn-on is the gain drain capacitance of the switch. The analytical results have been validated quantitatively with the simulation and experimental data. Experimental results show that the voltage overshoot across the switch reduces with decreasing of the drain–source capacitance. Also, increasing dv/dt by using a smaller gate turn-on resistor leads to higher induced gate–source voltage, which increases the possibility of false turn-on. The presented method can be beneficial in designing further high-voltage power converters to operate in the safe region using wide band gap switches which are suitable in high-frequency applications.