Simple and Effective Control System for Active AC Ripple Filtering Circuits

Abstract

In systems where dc and ac subsystems are interacting, dc capacitors are used to balance (filter or decouple) the ac power pulsations. The required capacitance often poses a limitation in terms of physical footprint, cost, and/or reliability. Active ripple filtering circuits are widely studied in the literature for reducing the size of the capacitor needed by using power electronic switches, passive circuit components, and a control system. The passive circuit components include a substantially smaller dc capacitor at a reasonably higher or lower voltage, and an inductor for filtering the switching ripples. The control systems presented in the literature for such systems are complex and need multiple sensors and are hardly plug-and-play and universal. This paper proposes a simple yet effective control system which uses only one voltage sensor. The circuit accurately emulates a large capacitor within a wide frequency bandwidth in a plug-and-play manner. The paper explains the details of the proposed control system and presents simulation and experimental results to illustrate its properties.

1. Introduction

A capacitor is a key circuit element for various electrical engineering applications. One important application is in grid-connected power converters, such as photovoltaic (PV) and wind generators, battery chargers, motor drives, electrified railways, rectifiers, and light-emitting diode (LED) drives. In such applications, a dc capacitor is commonly used to decouple ac double-frequency power ripples, and to provide control stability support against system disturbances that originate from either side of the converter [1,2,3,4,5,6,7,8,9]. The required dc capacitance for a given power level application demands the adoption of technologies, e.g., electrolytic, due to higher capacitance density. However, such capacitors suffer from high failure rates, especially in outdoor conditions. About 30% of the failures in power converters are attributed to their dc capacitors [10]. Film technology offers higher voltage, higher reliability, and longer life compared to the electrolytic technology. However, for all existing technologies, as the voltage level and the required capacitance increase, they quickly become bulky, heavy, and expensive [11].

Assuming that filtering of the ac power ripples, which are mainly double-frequency (2f) ripples, is the determining factor for the required size of the capacitor, a number of approaches to reduce the size of this capacitor are proposed in the literature. Some of the solutions are based purely on improving the control system of the main converter without adding any hardware, e.g., [6], to reduce adverse impacts of ripples on the control system responses. In this way, larger voltage ripples can be allowed across the intermediary dc-link capacitor, which means a smaller capacitance. Another category of solutions is based on adding an auxiliary circuit (comprising power electronics and small passive components) and controlling it properly to “emulate” a large capacitor. The focal idea is to relocate the ripples to a smaller capacitor, at a higher (or lower) voltage with magnified ripples, as long as it does not interfere with other system functions. Among this category, there are those which require modifications to the hardware and/or control of a host converter, e.g., [12,13], while others are autonomous in the sense that they do not require any modification to the hardware or control of a host converter, e.g., [14,15,16,17,18,19,20,21,22].

Among the autonomous solutions, i.e., those that do not require a change in the host converter hardware or control, the following appear to be the major existing proposals: the electronic capacitor (EC) of [14,23,24,25,26,27], the virtual infinite capacitor (VIC) of [15,28,29], the two-terminal active capacitor (TTAC) of [16,30,31,32], the active ripple energy storage (ARES) of [17], the active power decoupling (APD) method of [18], the active low-frequency ripple control device (ALFRCD) of [19], the active power decoupling circuit (APDC) of [20], the active dc bus conditioner of [21], and the ripple-current compensator (RCC) of [22]. The EC of [14,23,24,25,26,27] comprises a dc/dc converter, a small capacitor, and a control system. However, the extended and complex control systems are not mathematically and rigorously shown to demonstrate the desired capacitance. Moreover, the methods require multiple sensors, which adds costs and complexity. The idea of the VIC of [15,28,29] is to operate a power electronic converter (PEC) in conjunction with a capacitor such that an infinite capacitor is achieved at the output terminal. The VIC suffers from multiple issues, such as the requirement of at least three sensors and associated filtering circuits, complex control loops that are hard to design and operate, and limited bandwidth even with a very high switching frequency. In TTAC [16,30,31,32], a large capacitor is replaced with a small capacitor in series with an auxiliary circuit that comprises a full bridge bidirectional converter, two other small capacitors, and an inductor. However, the existing literature does not clearly prove nor does it demonstrate how well the proposed control system can achieve the objective. The frequency response shows that TTAC has hardly been able to emulate a large capacitor with any extended frequency range. Additionally, it suffers from practical issues, such as responses during disturbance and starting problems. The ARES of [17] comprises two switches, an inductor, and a capacitor where the switches are controlled in discontinuous current mode (DCM) to store the ripple energy in the capacitor. The ARES also requires two voltage sensors, a current sensor, and a complex control structure. The ALFRCD [19] has a relatively simple control structure. However, the presentation in [19] does not demonstrate that ALFRCD can have a robust and stable performance while offering a decently large capacitance gain. Moreover, it needs measurement of the external current that limits its operation in a plug-and-play fashion. The methods proposed in [18,20,21,22,33] suffer from one or more of the following issues: (i) a complex control system which leads to design difficulties and stability issues, (ii) the need for multiple signal measurements, (iii) limited bandwidth of the emulation capability, (iv) not a substantial gain in reducing the capacitance, and (v) lack of clarity and rigorous proof of the system functions. A series voltage compensator circuit and control is proposed in [34,35] that significantly reduces the flexibility in several applications. Therefore, the existing solutions have not been able to offer a substantially competitive solution (in terms of cost, performance, reliability, flexibility, and overall power efficiency) to replace a large dc capacitor.

This paper proposes an alternative solution, called a smart dc capacitor (SdcCap), for active power decoupling method in power converters. The proposed SdcCap consists of a power electronic converter, a small capacitor, and a controller. It amplifies and relocates the voltage ripples of a dc bus to a small capacitor to have the same effect of a larger capacitor. The substantial reduction in the capacitance requirement enables migration from low-reliable capacitor technologies to high-reliable capacitors, and also meets the capacitance needs and physical size.

The novelty and contribution of the paper can be summarized as below:

• A novel controller is proposed which is very simple, yet is robust with an all-stable internal feedback loop. The controller guarantees that it accurately emulates a larger capacitor within a wide bandwidth. The amount of capacitance amplification, as well as the voltage rating, are conveniently adjusted inside the controller. In advanced applications, these values can be changed after installation and even remotely, yielding a variable and adjustable capacitance.
• The proposed SdcCap is autonomous and plug-and-play in the sense that it is directly connected to the two terminals of interest without requiring any measurements external to it.
• The design approach and details of SdcCap are outlined, covering the two versions of SdcCap (buck/boost topology), the filter circuit design, and the controller design.
• The stability and robustness of the SdcCap have been analyzed. The SdcCap has high bandwidth, and it does not have stability and robustness issues.
• The detailed simulations and a sample of laboratory experimental results are presented that help to illustrate the performance of SdcCap in some exemplary applications.

2. Proposed Active Power Decoupling Controller

2.1. General Active AC Ripple Decoupling Circuits

The general topology of an active ac ripple decoupling circuit is shown in Figure 1a, with the output terminals A and B. It comprises a capacitor C, a power electronic converter (PEC), and either or both of Filter 1 and Filter 2. The filters are constructed using passive circuit components. The structure of Figure 1a is in the general form. Two possible specific forms, studied in this paper, are shown in Figure 1b,c, corresponding to a buck and a boost topology, respectively. In the buck topology, $v_c$ is larger than v, and in the boost topology, v is larger than $v_c$. The buck topology, Figure 1b, does not have Filter 1. Moreover, Filter 2 is an LC branch with inductance $L_f$ and capacitance $C_f$. In the boost topology, Figure 1c, Filter 1 is an inductance $L_f$, and Filter 2 is a capacitance $C_f$. The power electronic converter (PEC) is a standard half-bridge bidirectional voltage source converter (VSC) topology that uses standard pulse width modulating (PWM) switching. The switches $Q1$ and $Q2$ (Figure 1b,c) are turned ON and OFF opposite to each other. In the buck topology (Figure 1b), when $Q1$ is turned ON and $Q2$ is OFF, the voltage across the inductor filter $L_{\mathrm{f}}$ is $(v_{\mathrm{c}}-v)$, which causes the inductor filter current to increase (assuming the current flow towards terminal A as positive). When $Q1$ is OFF and $Q2$ is ON, the voltage across the inductor is v, which reduces the current in $L_{\mathrm{f}}$. Similarly, in the boost topology (Figure 1c), when $Q1$ is ON and $Q2$ is OFF, the voltage across the inductor $L_{\mathrm{f}}$ is $(v-v_{\mathrm{c}}$ that decreases the inductor current (again assuming current flows towards the terminal A as positive). When $Q1$ is OFF and $Q2$ is ON, the voltage across the inductor is $v_{\mathrm{c}}$, which increases the current in $L_{\mathrm{f}}$.

2.2. Proposed Control Structure

The proposed control structure of this paper is shown in Figure 2a,b for buck and boost topologies, respectively. In the buck topology, the controller receives the voltage of the capacitor C, i.e., $v_c(t)$, as the input, while in the boost topology, the terminal voltage v is the input. The controller generates the modulation signal for the PEC switch $Q_1$, i.e., $m(t)$. Switch $Q_2$ is turned on and off opposite to switch $Q_1$. The symbols $V_n$ and $V_{c,n}$ represent the nominal dc values for the output voltage, i.e., $v(t)$, and the capacitor voltage, i.e., $v_c(t)$, respectively.

Based on the diagrams of Figure 2a,b, the governing equations of the controller for the buck and boost topologies are, respectively,

$$u(t)=m(t)v_c(t)=V_n+{\displaystyle \frac{1}{k}}[v_c(t)-V_{c,n}],$$

(1)

$$u(t)=m(t)v(t)=V_{c,n}+k[v(t)-V_n],$$

(2)

where $k>1$ and $u(t)$ represent the voltage across switch $Q_2$ shown in Figure 1b,c.

2.3. Analysis of Proposed Controller for Buck Topology

2.3.1. Principle of Operation

In order to understand the principle of operation of the proposed controller for the buck topology, we note that the purpose of the $L_f{C}_f$ filter is to reduce the switching noises. Its transfer function is ${\displaystyle \frac{V(s)}{U(s)}}={\displaystyle \frac{1}{L_f{C}_f{s}^2+1}}$ and has a very close to unity flat gain within the frequency bandwidth sufficiently below its resonance frequency of ${\omega }_r={(L_f{C}_f)}^{-{\displaystyle \frac{1}{2}}}$. Within this bandwidth, the voltage u closely follows v and the controller Equation (1) may be approximated by

$$v(t)\approx V_n+{\displaystyle \frac{1}{k}}[v_c(t)-V_{c,n}].$$

(3)

In the boost topology, since the filter inductance $L_f$ is small, the voltage u closely follows $v_c$. The controller Equation (2) may be approximated by

$$v_c(t)\approx V_{cn}+k[v(t)-V_n].$$

(4)

It is immediately observed that the two Equations (3) and (4) are equivalent. Defining $\Delta v(t)=v(t)-V_n$ and $\Delta v_c(t)=v_c(t)-V_{c,n}$, both (3) and (4) yield

$$\Delta v_c(t)=k\Delta v(t).$$

(5)

Equation (5) means that the deviation of the voltage $v_c(t)$ around its nominal point $V_{c,n}$ is k times the deviation of $v(t)$ around its nominal point $V_n$. Both buck and boost topologies with their corresponding proposed controllers establish (5).

The instantaneous power supplied by the capacitor C is

$$\begin{array}{c}{p}_c(t)=C{v}_c(t){\dot{v}}_c(t)=Ck{v}_c(t)\dot{v}(t)\approx Ck{V}_{c,n}\dot{v}(t)=Ck{\displaystyle \frac{V_{c,n}}{V_n}}{V}_n\dot{v}(t)\approx C(k{\displaystyle \frac{V_{c,n}}{V_n}})v(t)\dot{v}(t).\hfill \end{array}$$

(6)

Equation (6) indicates that the equivalent capacitance is

$$C_{eq}=(k{\displaystyle \frac{V_{c,n}}{V_n}})C=KC,K=k{\displaystyle \frac{V_{c,n}}{V_n}}.$$

(7)

The constant K is called the capacitance advantage factor (CAF) and it can be made quite large by proper selection of k and $V_{c,n}$. In the above derivation, two approximations $v(t)\approx V_n$ and $v_c(t)\approx V_{c,n}$ are used to derive a simplified expression for CAF. The actual CAF is variable and is given by

$$K(t)={\displaystyle \frac{v_c(t){\dot{v}}_c(t)}{v(t)\dot{v}(t)}}=k{\displaystyle \frac{v_c(t)}{v(t)}}.$$

(8)

2.3.2. Discussion on Stability

The proposed feedback loops shown in Figure 2a,b do not engage any dynamic transfer function that could introduce dynamics into its operation. In other words, its ability to emulate a larger capacitor is instantaneous and natural. This allows the emulation to take place within a wide bandwidth. Furthermore, due to the same reason, it will not have any inherent stability issues. Regarding the resonance phenomenon of the $LC$ filter, it must be noted that since the filter is not in the path of the control loop (that is no measurement pertaining to this filter is used in the feedback loop of SdcCap), its stability will not be aggravated. Moreover, the filter components are appropriately selected such that the resonance frequency is sufficiently large, and no additional passive and/or active damping of that resonance mode is required. However, if need be, a small resistor can be added in series with $C_f$ to prevent possible ringings in very dynamic conditions.

2.3.3. Discussion on Robustness

The proposed controller has three circuit components (C, $C_f$, $L_f$), power electronic switches, and three control parameters k, $V_n$, and $V_{c,n}$. The parameter $V_n$ represents the nominal value of the terminal voltage $v(t)$ and is an external variable. If the actual value of this variable is different from the value used in the controller, it could cause problems.

To study this effect, note that (3) and (4) imply

$$v_c(t)=V_{c,n}+k[v(t)-V_n].$$

(9)

Assume that $v(t)=V+\tilde{v}(t)$, where V is the actual dc and $\tilde{v}(t)$ is the totality of the non-dc components of $v(t)$. We study what happens when V is not equal to $V_n$.

Equation (9) results in

$$v_c(t)=V_{c,n}+k(V-V_n)+k\tilde{v}(t)=V_c+{\tilde{v}}_c(t),$$

(10)

where $V_c=V_{c,n}+k(V-V_n)$ is the dc and ${\tilde{v}}_c(t)=k\tilde{v}(t)$ is the non-dc component of $v_c(t)$, respectively. This analysis results in two conclusions as explained below.

• The non-dc component of $v_c$ is k times the non-dc component of $v(t)$, i.e., ${\tilde{v}}_c(t)=k\tilde{v}(t)$. There is no robustness issue here because k is a known control parameter.
• The dc component of $v_c$, i.e., $V_c$, is off from the intended $V_{c,n}$ by as much as $k(V-V_n)$. For V smaller than $V_n$, $V_c$ will be smaller than $V_{c,n}$. Thus, $V_{c,n}$ must be sufficiently large to ensure that $v_c(t)$ remains larger than $v(t)$ in the buck topology and larger than zero in the boost topology to prevent the modulation index from going above unity in the buck topology and to remain in continuous conduction mode in the boost topology. For V larger than $V_n$, $V_c$ will be larger than $V_{c,n}$. Thus, $V_{c,n}$ must be sufficiently small to ensure that $v_c(t)$ remains below the acceptable voltage limit of capacitor C in the buck topology and below $v(t)$ in the boost topology.

To further illustrate this aspect, assume a scenario that $v(t)=V+\tilde{v}(t)=200+2sin(240\pi t)$. Also, let $k=8$, $V_n=200$ and $V_{c,n}=275$ for the buck and $V_{c,n}=125$ for the boost topology. Then, from (10), $v_c(t)=275+16sin(240t)$ for the buck and $v_c(t)=125+16sin(240t)$ for the boost topology. The average CAF is $K=k{\displaystyle \frac{V_{c,n}}{V_n}}$, which is 11 and 5 for the buck and boost topologies, respectively. As shown in Figure 3 and Figure 4 (for the buck and boost converters, respectively), during normal conditions, i.e., until $t=20$ ms, the CAF averages at 11 and 5.

When the bus voltage $v(t)$ experiences a drop of 4% or 8 V (i.e., to 192 V) between $t=20$ ms and $t=40$ ms, the voltage $V_{c,n}$ drops to $275-8k=211$ V for the buck and $125-8k=61$ V for the boost converter. For this voltage drop, $v_c(t)$ is still larger than $v(t)$ in the buck converter and is not over-modulated; and the boost converter is still in CCM. When the bus voltage $v(t)$ experiences a jump of 4% or 8 V (i.e., to 208 V) between $t=40$ ms and $t=60$ ms, the voltage $V_{c,n}$ rises to $275+8k=339$ V and the peak of $v_c(t)$ reaches as high as $339+8\times 2=355$ V in the buck converter; and $V_{c,n}$ rises to $125+8k=189$ V and the peak of $v_c(t)$ reaches as high as $189+8\times 2=205$ V in the buck converter which still remains in the linear region.

It is possible to improve the proposed controllers to address this robustness issue. One scenario is shown in Figure 5 where the proposed controller for the boost converter is improved by adding a simple low-pass filter (LPF) with the transfer function $G_{\mathrm{LPF}}(s)={\displaystyle \frac{1}{{\tau }_{\mathrm{lpf}}s+1}}$. The output of this block estimates the average (offset) of $v(t)$. Subsequently, this voltage is multiplied into a constant $\beta <1$ to generate the offset of $v_c$.

2.3.4. Selection of $L_f$ and $C_f$

The selection of $L_f$ and $C_f$ is made based on the following considerations: (1) The inductance $L_f$ must be large enough to adequately limit the level of switching ripples of the current flowing into the switches, yet it must be small enough such that the voltage drop across is negligible. (2) The capacitor $C_f$ must be large enough to adequately limit the level of switching ripples of the voltage across it. Yet, it must be small enough to allow a sufficiently large resonance frequency ${\omega }_r={\displaystyle \frac{1}{\sqrt{L_f{C}_f}}}$. A larger resonance frequency requires a lower level of damping and it is better if naturally damped. Specific designs are presented in the context of different examples in the rest of this paper.

3. Simulation Results

3.1. Single-Phase Rectifier Application

A single-phase passive rectifier application of the proposed SdcCap is discussed and studied in this section. The diagram of a single-phase rectifier application is shown in Figure 6. The setup consists of an ac source, a full-bridge diode rectifier circuit, a dc capacitor–$C_{\mathrm{dc}}$, and a load. The parameters of the circuit are given in

Table 1. Rectifier parameters.

Parameter	Symbol	Value
Grid voltage and freq.	$V_{\mathrm{g}}$ & f	120 V (rms) & 60 Hz
Rectifier output dc voltage	$v_o^{*}$	167 V
Rectifier power rating	$P_{\mathrm{rate}}$	1 kW
Rectifier capacitor	$C_{\mathrm{dc}}$	10 mF
Output voltage ripples	$V_{\mathrm{ripple}}$	6 V (pp)

. A dc capacitor is used at the dc terminals (A–B in Figure 6) to filter the voltage ripples caused by the ac input and a large capacitance is required to reduce these voltage ripples within allowable limits. In this section, such a large dc capacitor is replaced by the proposed SdcCap that uses a significantly smaller capacitor. Both the buck and boost topology of the proposed SdcCap are discussed.

3.1.1. Buck Topology

The parameters of the proposed buck-based capacitor are summarized in

Table 2. Proposed buck control parameters.

Parameter	Symbol	Value
Small capacitor	C	0.795 mF
Filter inductance	$L_f$	20 $\mathsf{\mu }$H
Filter capacitance	$C_f$	20 $\mathsf{\mu }$F
Switching frequency	$f_{\mathrm{sw}}$	80 kHz
Control gain	k	7
Nominal output voltage	$V_n$	167 V
Nominal capacitor voltage	$V_{c,n}$	300 V
Average CAF	K	12.58

. For a switching frequency of 80 kHz, the values of $L_f$ and $C_f$ are selected at 20 $\mathsf{\mu }$H and 20 $\mathsf{\mu }$F, respectively. This will limit the peak-to-peak switching ripples of current in $L_f$ and the switching ripples in voltage across $C_f$ within reasonably low values. The resonance frequency of the LC filter is about one-tenth of the switching frequency, i.e., about 8 kHz. With the selection of $V_n=167$, $V_{c,n}=300$, and $k=7.0$, the CAF will be $K=k{\displaystyle \frac{V_{c,n}}{V_n}}=12.58$. This means that the small capacitor is $C={\displaystyle \frac{10000}{12.58}}=795\mathsf{\mu }$F down from the original required value of 10 mF.

A sample of simulation results is shown in Figure 7, which summarizes the responses of the actual large capacitor and the proposed capacitor. Two load-changes are applied at $t=50$ ms and $t=100$ ms, and a $\pm 10$% change in the input ac voltage is applied at $t=150$ ms and $t=200$ ms. The responses of the proposed capacitor closely match those of the rectifier with the large capacitor. In other words, the proposed SdcCap that uses a 795 $\mathsf{\mu }$F capacitor can replace a large capacitor of 10 mF without compromising the quality of the dc voltage.

3.1.2. Boost Topology

The parameters of the proposed boost-based capacitor are summarized in

Table 3. Proposed boost control parameters.

Parameter	Symbol	Value
Small capacitor	C	1.7 mF
Filter inductance	$L_f$	20 $\mathsf{\mu }$H
Filter capacitance	$C_f$	1.7 mF
Switching frequency	$f_{\mathrm{sw}}$	80 kHz
Control gain	k	7
Nominal output voltage	$V_n$	167 V
Nominal capacitor voltage	$V_{c,n}$	143 V
Average CAF	K	6

. With the selection of $V_n=167$, $V_{c,n}=143$, and $k=7.0$, the CAF will be $K=k{\displaystyle \frac{V_{c,n}}{V_n}}=6$. This means that the small capacitor is $C={\displaystyle \frac{10000}{6}}\approx 1.7$mF down from the original required value of 10 mF. A sample of simulation results is shown in Figure 8, which summarize the responses of the actual large capacitor and the proposed capacitor. Two load-changes are applied at $t=50$ ms and $t=100$ ms, and $\pm 5$% change in the input ac voltage are applied at $t=150$ ms and $t=200$ ms. The responses of the proposed capacitor closely match those of the rectifier with the large capacitor. However, during the ac voltage changes, the voltages as expected start to shift apart. As explained, this problem can be significantly remedied by using the modified boost converter of Figure 5, as discussed in Section 3.1.3.

3.1.3. Boost Topology with Modified Control

The parameters of the proposed modified boost-based capacitor, Figure 5, are summarized as $\tau =5$ ms (time-constant of a first-order LPF), $\beta =0.85$, and $k=7$. With this selection, the nominal CAF will remain around 6. This means that the small capacitor is $C={\displaystyle \frac{10000}{6}}\approx 1.7$mF down from the original required value of 10 mF.

A sample of simulation results is shown in Figure 9, which summarizes the responses of the actual large capacitor and proposed capacitor. Comparison with Figure 8 shows that the proposed capacitor responses now closely match those of the actual large capacitor, even during the ac voltage uncertainties and changes. This circuit (i.e., the modified version) would allow increasing k (to further decrease the capacitor) while accommodating larger uncertainties in the ac voltage. In another simulation, shown in Figure 10, k is increased to 10 which means a CAF of around 8.6, i.e., a small capacitor of about 1.2 mF. The ac voltage disturbance is also increased to $\pm 10$%. Desired responses are observed.

3.2. Dc-Link Application in Two-Stage Single-Phase Inverter

This section describes the application of the proposed capacitor as a dc-link capacitor in a two-stage single-phase inverter application. A typical two-stage converter topology that interfaces a PV system to a single-phase ac system is shown in Figure 11. In this topology, the first stage dc/dc converter extracts power from the PV and steps up the voltage to a level needed for the second stage. The second stage converter is a single-phase inverter that (1) feeds power to the grid at an acceptable level of power quality, and (2) enables reactive power exchange. The inverter is also responsible for dc-link voltage control. A dc-link capacitor ($C_{\mathrm{dc}}$) of rather a large size is required to decouple the ac component of the power from the PV terminals. The proposed capacitor can replace such a large capacitor to have a similar level of performance. The proposed capacitor amplifies and relocates the voltage ripples of the dc-link to a smaller capacitor to have the same effect as that of a large capacitor. In this study, the proposed buck-based capacitor is used.

In Figure 11, the ‘dc converter control’ consists of an MPPT algorithm that provides a reference PV terminal voltage $V_{\mathrm{pv}}^{*}$, and the inner proportional integral (PI)-based voltage control ($P{I}_{\mathrm{v}}$) generates the reference current $I_{\mathrm{pvo}}^{*}$. The innermost current controller ($P{I}_{\mathrm{c}}$) generates a modulating signal for the dc/dc boost converter. This way, the terminal voltage of the PV is regulated at $V_{\mathrm{pv}}^{*}$ to extract maximum power from the PV system. The ‘inverter control’ has a dc-voltage reference $V_{\mathrm{dc}}^{*}$ and reference reactive power $Q^{\mathrm{ref}}$ as inputs. A PI-based voltage control ($P{I}_{\mathrm{v}}$) generates an active component of the reference current $I_{\mathrm{d}}$ while a reactive component $I_{\mathrm{q}}$ is calculated from $Q^{\mathrm{ref}}$. The active and reactive current references are combined with the phase components to generate a reference sinusoid current $i_{\mathrm{inv}}^{*}$ for the inverter. A single phase-enhanced phase-locked loop (ePLL) is used in this application to extract the phase components. A proportional resonant controller ($P{R}_{\mathrm{c}}$) then regulates the output current of the inverter at $i_{\mathrm{inv}}^{*}$. This way, the inverter feeds power to the ac grid and also controls the dc-link voltage.

The parameters of the converter system and proposed capacitor in Figure 11 are summarized in

Table 4. Two-stage single-phase converter and control parameters.

Parameter	Symbol	Value
Grid voltage and freq.	$V_{\mathrm{g}}$ & f	120 V (rms) & 60 Hz
PV voltage	$v_{pv}$	145 V
PV power	$P_{pv}$	2.5 kW
Dc-link nominal voltage	$v_{\mathrm{dc}}$	400 V
Inverter power rating	$S_{\mathrm{inv}}$	3.53 kVA
Dc-link capacitor	$C_{\mathrm{dc}}$	750 $\mathsf{\mu }$F
Small capacitor in SdcCap	C	37.5 $\mathsf{\mu }$F
SdcCap filter inductance	$L_f$	50 $\mathsf{\mu }$H
SdcCap filter capacitance	$C_f$	25 $\mathsf{\mu }$F
SdcCap switching frequency	$f_{\mathrm{sw}}$	80 kHz
SdcCap control gain	k	10
Nominal SdcCap output voltage	$V_n$	400 V
Nominal SdcCap capacitor voltage	$V_{c,n}$	800 V
Average CAF	K	20

. The system interfaces a 2.5 kW PV system at 145 V to a single-phase ac system of 120 V (rms). The first-stage boost converter extracts maximum power from the PV and boosts the voltage level to 400 V. The second stage inverter then feeds active and reactive powers to the grid. The inverter is rated at 3.53 kVA to enable simultaneous supply of 2.5 kW active power from the PV system and exchange 2.5 kVAr of reactive power with the grid. For the nominal dc link voltage of 400 V, a dc-link capacitor of 750 $\mathsf{\mu }$F is selected to reduce the dc-link voltage ripples to 5% (20 V) and a peak voltage fluctuation of 10% (40 V) during power jumps. The dc-link voltage control and the inverter control are designed using the standard methods discussed in [5,6]. The dc/dc converter is a standard boost converter and its nested control loop gains are designed using a linear quadratic regulator (LQR) approach.

For the proposed capacitor, a switching frequency of 80 kHz is used. The values of $L_f$ and $C_f$ are selected as $50\mathsf{\mu }$H and $25\mathsf{\mu }$F, respectively, which results in a resonance frequency of 4.5 kHz. In the SdcCap, $V_n=400$, $V_{c,n}=2V_n=800$, and $k=10$ are selected to achieve a CAF of $K=k{\displaystyle \frac{V_{c,n}}{V_n}}=20$. Thus, a capacitor of $C=37.5\mathsf{\mu }$F is used in the SdcCap.

Figure 12 shows the results from the simulation of a two-stage single-phase system with a large dc-link capacitor of $750\mathsf{\mu }$F, and the SdcCap that uses $37.5\mathsf{\mu }$F. The active and reactive powers of the inverter, the dc-link voltage, the inverter current, and the voltage across the small capacitor in the proposed SdcCap are shown. Several active and reactive power disturbances are applied to compare the performance of SdcCap with the actual capacitor. The inverter feeds 2.5 kW between $0\le t\le 0.1$ s. At $t=0.1$ s, the active power is reduced to 1.25 kW, and it is increased to 2.5 kW at $t=0.2$ s. The active power disturbances are applied by changing the irradiance of the PV system. The inverter feeds a reactive power of 1.5 kVAr between $0.3\le t\le 0.4$ s, and absorbs a reactive power of 1.0 kVAr between $0.4\le t\le 0.5$ s. The results of Figure 12 clearly show that the power levels, inverter currents, and the dc link voltage follow similar transients and have similar performance when using either the proposed SdcCap or a large capacitor. The SdcCap has switching ripples in the dc-link voltage that, if needed, can be reduced by increasing the switching frequency and/or the filter capacitance. These high-frequency switching ripples on the dc-link voltage do not impact the operation and performance of the inverter.

3.3. Dc-Link Application in One-Stage Single-Phase Inverter

Figure 13 shows a schematic diagram of a one-stage single-phase inverter topology in PV application. Similar to the two-stage topology, the inverter controls the dc voltage and feeds power to the ac system. The inherent nature of the ac power output of the inverter creates double-frequency voltage ripples across the dc link, the same as in the two-stage topology. Since the PV terminals are directly connected across the dc link, the voltage ripples on the dc-link directly affect the power extraction from the PV. Therefore, the voltage ripple in the one-stage converter topology is more critical than for the two-stage converter in PV applications. This means a significantly large dc link capacitor is required to reduce the voltage ripples and, hence, achieve smooth PV power extraction. In such a converter topology, the SdcCap that uses a significantly smaller capacitor can be utilized to produce a similar level of performance to a large capacitor.

In Figure 13, the inverter control has a similar structure as the ‘two-stage topology’. The MPPT algorithm generates the voltage reference $V_{\mathrm{pv}}^{*}$ for the PI-based voltage control ($P{I}_{\mathrm{v}}$) that generates an active component of the reference current $I_{\mathrm{d}}$. The reactive component $I_{\mathrm{q}}$ is calculated from the reference reactive power, $Q^{\mathrm{ref}}$. These reference currents are combined using phase components to generate a reference sinusoid current, $i_{\mathrm{inv}}^{*}$ for the inverter. Similar to the two-stage topology, a single-phase ePLL is used. A PR-based controller ($P{R}_{\mathrm{c}}$) then regulates the output current of the inverter at $i_{\mathrm{inv}}^{*}$. This way, the inverter feeds power to the ac grid and also controls the dc voltage to extract maximum power from the PV system.

The one-stage single-phase converter topology, shown in Figure 13, is studied for two capacitors—a directly connected large dc capacitor and the SdcCap in the buck topology. The power rating of the inverter is 8.5 kVA. The parameters of the inverter and the SdcCap are summarized in

Table 5. One-stage single-phase inverter and control parameters.

Parameter	Symbol	Value
Grid voltage and freq.	$V_{\mathrm{g}}$ & f	120 V (rms) & 60 Hz
PV voltage	$v_{pv}$	400 V
PV power	$P_{pv}$	6.0 kW
Dc-link nominal voltage	$v_{\mathrm{dc}}$	400 V
Inverter power rating	$S_{\mathrm{inv}}$	8.5 kVA
Dc-link capacitor	$C_{\mathrm{dc}}$	1500 $\mathsf{\mu }$F
Small capacitor in SdcCap	C	75 $\mathsf{\mu }$F
SdcCap filter inductance	$L_f$	50 $\mathsf{\mu }$H
SdcCap filter capacitance	$C_f$	50 $\mathsf{\mu }$F
SdcCap switching frequency	$f_{\mathrm{sw}}$	80 kHz
SdcCap control gain	k	10
Nominal SdcCap output voltage	$V_n$	400 V
Nominal SdcCap capacitor voltage	$V_{c,n}$	800 V
Average CAF	K	20

. The nominal voltage at the dc-link is 400 V. For a dc capacitor of 1500 $\mathsf{\mu }$F, the double-frequency voltage ripple in the dc link is 28 V peak-to-peak when the inverter active and reactive powers are 6.1 kW and 0 kVAr, respectively. An SdcCap is designed to mimic the large capacitor of size 1500 $\mathsf{\mu }$F. The switching frequencies ($f_{sw}$), $L_f$, and $C_f$ in SdcCap are 80 kHz, 50 $\mathsf{\mu }$H, and $50\mathsf{\mu }$F, respectively. In the SdcCap, $V_n=400$, $V_{c,n}=2V_n=800$, and $k=10$ are selected to achieve a CAF of $K=k{\displaystyle \frac{V_{c,n}}{V_n}}=20$, that results in a capacitor $C=75\mathsf{\mu }$F.

Figure 14 shows the responses of the inverter with a large capacitor and one with the SdcCap. The active and reactive power disturbances are applied. The active power disturbance is applied by changing the solar irradiance level. The solar irradiance is 1000 $\mathrm{W}/{\mathrm{m}}^2$ and the PV power is at 6.1 kW between $0\le t\le 0.1$ s. At $t=0.1$ s, the solar irradiance is changed to 500 $\mathrm{W}/{\mathrm{m}}^2$, which reduces the PV power to 3.2 kW. Again at $t=0.2$ s, the solar irradiance is increased to 1000 $\mathrm{W}/{\mathrm{m}}^2$, which increases the PV power to 6.1 kW. The inverter feeds reactive power of 4.0 kVAr between $0.3\le t\le 0.4$ s, and absorbs reactive power of 4.0 kVAr between $0.4\le t\le 0.5$ s. With a directly connected large capacitor of 1500 $\mathsf{\mu }$F, the dc link voltage ripples are small, and the PV power has a lower level of fluctuations. The SdcCap that uses 75 $\mathsf{\mu }$F exhibits a similar level of performance to the 1500 $\mathsf{\mu }$F capacitor in terms of the inverter currents, dc link voltage, and PV power.

3.4. Output Capacitor in Flyback Converter Applications

This section describes the application of the proposed SdcCap in a flyback converter for an LED drive application. The comparison results with a conventional approach are also presented. A schematic circuit diagram of the studied system is shown in Figure 15, which consists of a diode full-bridge rectifier, a flyback converter, and an output capacitor. In this section, three cases are studied where the output capacitor is (1) an actual large capacitor, (2) a small capacitor with an active circuit introduced in [7,8], (3) the SdcCap of this paper.

The diagram of the method of [8] is shown in Figure 16. With regard to the hardware, it is exactly identical to the SdcCap: a half-bridge converter, a dc capacitor, and an LC filter. It, however, needs two additional current sensors for measuring $I_s$ and $i_b$. Its control circuit is quite extensive and comprises (1) a band-pass filter (BPF) at double frequency to generate the reference current $i_b^{*}$, (2) a 90-degree phase-shift block that is implemented using a first-order all-pass filter, (3) two PI compensators, (4) an inversion block, and (5) a square-root calculation. The constant $k_1$ is equal to ${\displaystyle \frac{1}{C\omega V_o^{*}}}$.

The parameters of the power circuit and control systems of this study are given in

Table 6. Flyback converter application parameters.

Parameter	Symbol	Value
Grid voltage and freq.	$v_{\mathrm{s}}$ & f	100 V (peak) & 60 Hz
Rated output voltage	$V_o^{*}$	10 V
Rated power	$P_o$	10 W
Output capacitor	$C_{\mathrm{dc}}$	2000 $\mathsf{\mu }$F
Small capacitor in SdcCap/[8]	C	200 $\mathsf{\mu }$F
SdcCap filter inductance	$L_f$	20 $\mathsf{\mu }$H
SdcCap filter capacitance	$C_f$	20 $\mathsf{\mu }$F
SdcCap switching frequency	$f_{\mathrm{sw}}$	100 kHz
SdcCap control gain	k	5
Nominal SdcCap output voltage	$V_n$	10 V
Nominal SdcCap capacitor voltage	$V_{c,n}$	20 V
Average CAF	K	10
Voltage compensator in [8]	PIv	$0.02+0.1$ ${\mathrm{s}}^{-1}$
Current compensator in [8]	PIi	$1+10000$ ${\mathrm{s}}^{-1}$
Flyback compensator	PIf	$0.01+$ ${\mathrm{s}}^{-1}$

. The flyback switch is controlled via a PI controller, shown in Figure 15.

The simulation scenario is as follows: The converter starts from complete rest at $t=0$ s while half the rated load is connected; then, at $t=0.1$ s and $t=0.2$ s, the load is increased to full load and one-and-half full load, respectively. The output voltages of the three systems (large capacitor, SdcCap, and conventional) are shown in Figure 17. It is observed that all three systems regulate the output voltage to 10 V properly. The waveform traces of the SdcCap are more similar to the large capacitor.

Figure 18 shows the voltage across the small capacitor of SdcCap and conventional method. As expected, this voltage is centered around 20 V, and its range of ripples is around five times larger than those of the output voltage. The conventional approach tends to give a more robust voltage. The modulation indices of the SdcCap and conventional converters are shown in Figure 19. It is observed that the SdcCap has a smoother index without high-frequency noises.

Since the BPF and phase-shift, as well as the gain $k_1$, in the conventional method are functions of the input ac frequency, this means that it cannot operate for a wide range of input frequency changes unless those gains are adaptively adjusted. Figure 20 shows the results of the simulation when the input ac frequency is changed to 50 Hz without adjusting the controller blocks and gains. It is observed that the SdcCap continues to operate without any visible change while the conventional approach experiences extremely large and unacceptable oscillations at its output voltage. The results clearly show that the applications of the conventional method are limited, especially where the frequency of the ac voltage may change, for example, in variable frequency drives (VFDs), while the proposed SdcCap operates like an actual capacitor. Moreover, the conventional controller is extensive with a band-pass filter, phase-shift block, and PI compensators that introduce dynamics to the control loop, making the system vulnerable to stability issues.

The above simulation studies confirm that the proposed SdcCap can successfully reduce the capacitor size by anywhere between 10 to 20 times without compromising the system performance.

4. Experimental Results

A laboratory-scale prototype of SdcCap in buck topology was built and tested to show its performance in a rectifier application. Figure 21a shows a photograph of this setup. The setup consists of (1) an ac supply of 30 V (rms), (2) a passive full-bridge rectifier, (3) a resistive load ($R_{\mathrm{L}}$), and (4) a dc capacitor ($C_{\mathrm{dc}}$) at the dc terminals of the rectifier. This dc capacitor filters the double-frequency ripples on the dc voltage ($v_{\mathrm{L}}$). In this study, a $C_{\mathrm{dc}}$ of 500 $\mathsf{\mu }$F (the measured capacitance was 400 $\mathsf{\mu }$F) is used. The load is a resistive load of 50 $\mathsf{\Omega }$. This study evaluates the performance of the proposed SdcCap that uses 25 $\mathsf{\mu }$F against the large capacitor of 500 $\mathsf{\mu }$F in this passive rectifier application. The proposed SdcCap is highlighted in the blue box in the setup diagram of Figure 21a. The SdcCap has a small capacitor of 25 $\mathsf{\mu }$F, an H-bridge power electronic converter with IGBT switches (similar to buck topology), and an LC filter (200 $\mathsf{\mu }$H, 20 $\mathsf{\mu }$F). A corresponding schematic diagram of the test setup is shown in Figure 21b. The system and control parameters are given in

Table 7. Experimental test parameters.

Parameter	Symbol	Value
Ac voltage and freq.	$V_{\mathrm{g}}$ & f	30 V (rms) & 60 Hz
Rectifier output dc voltage	$v_o^{*}$	35 V
Rectifier load	$R_{\mathrm{L}}$	50 $\mathsf{\Omega }$
Rectifier capacitor	$C_{\mathrm{dc}}$	400 $\mathsf{\mu }$F
Small capacitor in SdcCap	C	25 $\mathsf{\mu }$F
SdcCap filter inductance	$L_f$	200 $\mathsf{\mu }$H
SdcCap filter capacitance	$C_f$	20 $\mathsf{\mu }$F
SdcCap switching frequency	$f_{\mathrm{sw}}$	20 kHz
SdcCap control gain	k	7.14
Nominal SdcCap output voltage	$V_n$	35 V
Nominal SdcCap capacitor voltage	$V_{c,n}$	80 V
Average CAF	K	16

.

The experimental results of a large capacitor and an SdcCap that uses 25 $\mathsf{\mu }$F in a passive rectifier circuit are shown in Figure 22. The test results show that using a large capacitor of 500 $\mathsf{\mu }$F (measured at 400 $\mathsf{\mu }$F), the average output voltage is 36 V with voltage ripples of 12 V peak-to-peak. With the proposed SdcCap that uses 25 $\mathsf{\mu }$F, the average output voltage is 35 V with voltage ripples of 12 V peak-to-peak. The voltage across the small capacitor in SdcCap ranges from 40 V to 120 V. From these results, it can be clearly observed that the SdcCap with 25 $\mathsf{\mu }$F can achieve a similar level of performance in ripple reduction as that of an actual 400 $\mathsf{\mu }$F capacitor. The SdcCap amplifies and relocates the voltage ripples to a small capacitor to achieve this higher capacitor gain. In the test results, SdcCap has a slight drop in the average load voltage that can be attributed to the voltage drop across the IGBT switches and the output filter during operation.

The simulation study is also carried out for the experimental setup to validate its performance against the simulation studies. Figure 23 shows the simulation results of the experimental setup of Figure 21. In the simulation study, 2 $\mathsf{\Omega }$ resistance is considered across the terminals of the ac source to account for the resistance of the wire leads. Moreover, an additional 0.75 $\mathsf{\Omega }$ is considered across the IGBTs and output filter to account for the voltage drop across them. The experimental results shown in Figure 22 are consistent with the simulated results shown in Figure 23. The large capacitor in the simulation study has an average output voltage of around 35 V with voltage ripples of roughly 10 V peak-to-peak. The SdcCap has a similar level of performance with an average output voltage of around 35 V and a voltage ripple of around 11 V peak-to-peak. The voltage across the small capacitor ranges from 40 V to 115 V in SdcCap. These results imply that the SdcCap that uses 25 $\mathsf{\mu }$F has a similar level of performance as that of a large capacitor of 400 $\mathsf{\mu }$F.

5. Conclusions

In dc/ac systems, dc capacitors are used to decouple double-frequency power ripples, and to provide control stability against system disturbances originated on either side of the power converter. The typical capacitance required for such applications is large to reduce the order of double-frequency ripples and achieve better performance during disturbances. However, large capacitance requirements often impose limitations in terms of physical size and reliability. An approach to replace a dc capacitor with another one at a substantially smaller size is presented and discussed in this paper. The proposed solution, called a smart dc capacitor or SdcCap, amplifies the relocation of the voltage ripples of the dc bus to a small capacitor to achieve a similar effect to a large capacitor. The control approach proposed in this paper is new and novel. It has a very simple and robust structure without any dynamic feedback loops. This gives a wide bandwidth and instantaneous response to the proposed capacitor. Analytical derivations, computer simulations, and laboratory-scale experimental results are presented to illustrate the performances of the proposed SdcCap concept in several applications. A potential direction for future work could involve exploring this SdcCap concept across a range of applications through experimental research while also refining the design with a focus on commercial viability.