A Comparative Study of Incremental ΔΣ Analog-to-Digital Converter Architectures with Extended Order and Resolution

Abstract

Incremental Delta-Sigma (I-DS) analog-to-digital converters (ADCs) are one of the best candidates for integrated sensor interface systems when it comes to high resolution and power efficiency. Advanced architectures such as Multistage noise shaping (MASH) or extended counting (EC) I-DS ADCs can be used to achieve a high resolution and fast conversion times and avoid stability issues. Different architectures have been proposed in the state of the art (SoA), but there exists no extensive quantitative or qualitative comparison between them. This manuscript fills this gap by providing a detailed system-level comparison between MASH, EC, and other architectural options in I-DS ADCs, where different performances between these architectures are realized depending on the employed oversampling ratio (OSR) and the chosen number of quantizer bits. Also, for specific MASH designs, the appropriate choice of the digital filter improves the SQNR. The advantages, disadvantages, and limitations of the different architectures are presented including non-idealities such as coefficient mismatch showing that 2-1 MASH-LI is less sensitive to mismatch and provides a high maximum stable amplitude (MSA) relative to the simulated architectures. Furthermore, the 2-1 EC achieves good results and comes with the advantage of a lower noise penalty factor compared to the MASH architectures. This work is intended to assist designers in selecting the most appropriate enhanced I-DS MASH architecture for their specific requirements and applications.

1. Introduction

Delta-Sigma modulators (DSMs) achieve good efficiencies for high-resolution converters due to their oversampling and noise-shaping properties. Disadvantageously, the same properties prevent DSMs from being used in applications where true Nyquist operation is required, including multiplexed, single-shot conversion, or true cycle-cycle operation. I-DS ADCs offer an alternative, while inheriting the basic oversampling and noise-shaping properties of a conventional DSM. In the incremental Delta-Sigma modulator (I-DSM), the analog loop filter and the digital reconstruction filter are reset before the start of each conversion. The I-DS ADC converts sample-by-sample without memory of prior samples, and it can thus be considered as a true Nyquist-rate converter [1,2]. Compared to a conventional DSM, I-DSMs usually have a less complex decimation filter, allow multiplexing, and offer low latency. Furthermore, I-DSMs are also less subject to idle tones due to the periodic reset [3,4,5]. As a result, it is a more suitable candidate in sensor fusion SoCs and neural recording systems [5].

However, I-DS ADCs are less efficient in terms of noise-shaping and resolution: a first-order I-DSM needs $2^N$ oversampling clock periods to achieve N-bit accuracy, requiring a relatively high OSR. Higher-order I-DSM can be used to reduce OSR and achieve shorter conversion times or higher signal-to-quantization-noise ratio (SQNR) [6]. However, single-loop high-order modulators are more prone to instability, require reduced loop gain to maintain stable operation, and generally lead to reduced MSA.

MASH DSM have been proposed to realize high-order noise-shaping by cascading low-order individual stages, thereby mitigating the stability issues of single-loop architectures [7], a concept that can be transferred to as I-DSM [8]. MASH ADCs pass the quantization error of the first stage to the subsequent stages for further quantization. Thereby, two different methods have been used in the SoA to extract the quantization error of the first stage. Either the quantizer output is subtracted from the quantizer input to build a quantization error, which is then passed to the higher stages [9,10]. Alternatively, the last integrator output of the I-DSM [5,8,11] is used to pass the quantization error to the next stage.

An alternative to extended I-DSM order by multi-stage architectures is motivated by the fact that the remaining quantization error after I-DSM operation can be found in the analog domain at the last integrator output at the end of each Nyquist conversion. Since this analog quantization error can be sampled and re-quantized in a second operation phase, it can be subtracted from the digital output of the I-DS ADC to further improve the overall resolution. This technique is known as EC or extended range (ER) in the SoA [12,13,14,15]. While EC and ER were used as terminology for first- or higher-order I-DSM using the same principle, for the sake of simplicity, we name this technique EC in the remainder of this work irrespective of I-DSM order.

These architectures of extended order or resolution have been introduced in the SoA and illustrated in Figure 1a, emphasizing the three methods to extract and requantize the quantization error from the first stage, where $e_1$ is the quantization error of the first stage, emphasizing the method MASH-quantization error (QE). $e_2$ corresponds to the quantization error of the first stage emphasizing the method MASH-last integrator (LI). $e_3$ corresponds to the quantization error of the first stage after down-sampling by M cycles and emphasizes the method of extended counting (EC). $X\left[n\right]$ is the input, $H\left(z\right)$ is the loop filter, and $y_1\left[n\right]$ is the output of the first stage. The three methods are explained in detail in the following section. The timing diagram in Figure 1b shows that in the case that the second stage is realized as the MASH architecture, it runs simultaneously with the first stage and is reset at the same time. In the case that the second stage is extended, its counting only starts running after the first stage is finished. In the case that the second stage is implemented using another I-DS ADC, it runs with the oversampling $M_2$, which does not necessarily have to be the same as the oversampling of the first stage M. To the knowledge of the authors, there exists no work in the state of the art comparing them, including non-idealities and achievable performances, but still, all three variants are independently used in recent publications [5,10,14]. A comparative study has been presented for two types of extended range architectures, and a single-stage I-DS ADC [16]. Ref. [3] provides an extensive overview of oversampling ADCs and discusses previous SoA, and [4,17] discuss extended counting and multi-step architectures analytically. However, none of the available papers provide an extensive comparison of EC and MASH architectures under varying parameters such as different numbers of quantizer bits, inter-stage gain, and non-idealities. Therefore, we aim to focus on different variants of quantization error extraction specifically for incremental DSM and to close a gap in the SoA by revising, analyzing, and comparing them on a system level. The comparison shows the limitations of MASH-QE, the maximum stable architecture while using inter-stage gain, the appropriate choice of OSR for MASH-LI and EC, the limitations of using a single-bit quantizer for MASH-QE and EC, the possibility of two different designs for the digital filters for MASH-LI and the benefit of using the appropriate choice of the digital filters for MASH-LI. Since there exists no closed equation to precisely predict the SQNR of I-DS ADCs, especially including non-idealities [18], the comparison of the different architectures is based on simulations using MATLAB/SIMULINK. The paper is organized as follows. In Section 2, several incremental MASH architectures are compared with one another on the system level. In Section 3, the performance of the architectures is investigated. In Section 4, non-idealities are included in the simulations of the architecture comparison. Section 5 provides a discussion and a summary of the reported simulation results. Section 6 concludes the paper.

2. Incremental Multi-Stage/Step Architectures

Six exemplary incremental MASH and EC architectures will be discussed and compared on the system level. Figure 2a shows two of the exemplary MASH architectures, and the differences between the two architectures are drawn in light shading, and dashed to indicate that either the light red or the light blue method can be used. $b_1$, $c_1$, $c_2$, $a_1$, $a_2$ and $b_3$ are the coefficients of the first-stage I-DSM. $H_1\left(z\right)$ and $H_2\left(z\right)$ are the digital filters for the error cancellation logic, and $H_{rec}\left(z\right)$ is the reconstruction filter. $x\left[n\right]$ is the input signal and $y\left[n\right]$ is the final output of the MASH.

2.1. MASH-QE

Figure 2a shows an exemplary 2-1 MASH with a second-order first-stage I-DSM and a first-order second-stage I-DSM. The illustrated 2-1 MASH can also be modified to be a 2-0 MASH architecture when the second-stage, first-order I-DSM is replaced by a quantizer. Including the red inter-stage connection, a 2-1 MASH-QE is realized, where the input to the second stage is the subtraction of the quantizer output from the quantizer input, i.e., the actual error of the first stage quantizer. This MASH-QE requires an additional digital-to-analog converter (DAC) in the extraction path. The inter-stage gain (g) can be used to further improve performance and will be discussed in Section 3. Figure 2b shows the timing diagram for two conversions for the first and second stages, where the two stages are running simultaneously. A more detailed explanation of the operation of MASH architectures can be found in [17].

2.2. MASH-LI

It can be shown that the output of the last integrator in an I-DSM is the quantization error between the (constantly assumed) analog input and the reconstructed digital output after the chain of integrators (CoI) reconstruction filter. As this is not only true after a complete conversion of M clock cycles but at any operating step $k=1\dots M$, the quantization error can be requantized from there at any time. This is the principle of the second variant of a MASH I-DSM and illustrated with the blue inter-stage connection in Figure 2a. The resulting MASH-LI passes the quantization error from the output of the last integrator to the second stage for re-quantization. No additional DAC is required. An equivalent 2-0 MASH-LI is obtained by replacing the first-order second stage with a quantizer. All MASH architectures require a digital cancellation logic (cf. $H_1/H_2$ in Figure 2a) and use a CoI filter as a reconstruction filter. The 2-1 MASHs use a CoI3 and the 2-0 MASHs a CoI2. Depending on the architecture and loop-filter coefficients used it is also possible in some cases to combine the error cancellation logic (ECL) with the reconstruction filters [19] to save area and power in the digital domain.

2.3. Extended Counting EC

Figure 3a shows an EC architecture. The first stage is a second-order I-DSM that operates for M clock cycles. The last output of the last integrator of the first stage is given as input to the second stage, indicated by a decimation by M in Figure 3a. In an EC architecture, this analog quantization error is re-quantized by a second stage. This can be any ADC. Figure 3a indicates a first-order I-DSM in the second stage for this operation, and we refer to it as 2-1 EC I-DSM. The I-DSM of the second stage does not necessarily have the same oversampling as in the first stage but can rather have its own oversampling $M_2$, cf. Figure 3a. Replacing the second stage with a quantizer, we refer to it as 2-0 EC I-DSM. In contrast to the MASH architectures, the second stage in Figure 3a starts operating after the first stage is finished. The differences between the MASH and EC architectures are emphasized by light green blocks. Figure 3b shows the timing diagram for the operation of EC, where the second stage operates after the first stage is finished. M is the oversampling of the first stage and $M_2$ is the oversampling of the second stage [17].

In practice, the SoA introduced different methods of implementing the second operation phase of the EC architecture. Since the second stage starts working after the first stage is finished, the second stage could be a separate circuit, as illustrated in Figure 3a [20]. In this case, it is also possible to pipeline the operation of the first and second stages. Another possibility is to reuse part of the first stage for requantization [21,22]. In this context, it should be noted that the EC architecture comes with a higher latency. This is because the overall output is only available when the second stage is finished, as indicated by a delay in the first-stage output.

Also, the required digital reconstruction filters are different in the EC I-DSM. The reconstruction filter of the first stage must resemble the analog modulator. Therefore, it can be calculated using the modulator transfer function from the quantizer output to the output of the last integrator. In the case of a second-order I-DSM as in Figure 3a, it would be a CoI2 filter together with a gain factor consisting of $c_1·c_2$ indicated by the symbol $H_{rec}\left(z\right)$ [20,23]. If the second stage is implemented as a first-order I-DS ADC as in Figure 3a, it needs a separate the CoI1 reconstruction filter indicated by the symbol $H_{rec2}\left(z\right)$. If the second stage is implemented as a simple quantizer, there is obviously no reconstruction filter required. In contrast to Figure 2a, no digital recombination filters $H_{1/2}$ are needed, as the digital recombination is effectively incorporated into the reconstruction filter as a gain factor. Before subtracting the output of the second stage from the output of the first stage reconstruction filter, it must be divided by the gain of the first stage reconstruction filter. In case of the CoI2 filter operating for M cycles, this is $1/M(M-1)$.

2.4. Reconstruction Filters and Noise Penalty

It is well known that I-DS ADC have a so-called noise penalty factor (NPF) [24]. Input referred thermal noise is weighted over the operational cycles $k=1\dots M$ by the digital reconstruction filter. While the weighting is uniform for a first-order CoI reconstruction filter, it is different for higher-order filters. This leads to an increase in noise. The NPF is then defined as the achieved noise for higher-order CoI vs. the minimum noise achieved by a first-order CoI. The MASH I-DSM require the order of the CoI reconstruction filter to be of the same order as that of the combined MASH stages, i.e., CoI3 for 2-1 MASH and CoI2 for a 2-0 MASH. The EC I-DSM requires only a reconstruction filter of the order of the first stage, i.e., CoI2 for both 2-1 and 2-0 EC. This leads to an advantage of EC as, e.g., the NPF of the 2-1 MASH is that of a third-order CoI, NPF ≈ 1.85, while the EC architecture only requires a second-order CoI filter leading to a NPF ≈ 1.35.

3. Ideal Performance of MASH and EC IDSM

In order to further elaborate on the differences between these architectures, they are realized using multi-bit and single-bit quantizers and different values of OSR, and the achievable performance is compared. We use the exemplary 2-1 and 2-0 architectures presented in Section 2. The analysis for MASH-QE can be derived from the time domain analysis of a single-stage IADC. Thereby, the order of the single stage is the summation of the order of the two stages, the quantization error of the first stage is canceled, and instead, the quantization error of the second stage is considered. Furthermore, it has the noise shaping of the second stage multiplied by the noise shaping in $H_2$. Using the MB coefficients in

Table 1. Coefficient values for the first stage for different out-of-band gain (OBG) values.

	OBG	${\mathit{c}}_1$	${\mathit{c}}_2$	${\mathit{a}}_1$	${\mathit{a}}_2$	${\mathit{b}}_1$	${\mathit{b}}_3$
MB	4	1	1	2	1	1	1
SB	1.5	0.7	0.46	1.1	0.67	0.7	1

, the quantization error E and the maximum SQNR can be expressed as [17]:

$$E\approx {\displaystyle \frac{N!}{M^N}}·{\displaystyle \frac{V_{FS}}{L_2-1}}$$

(1)

$$SQNR\approx N·20log\left(M\right)+20log(L_2-1)-20log(N!)$$

(2)

$L_2$ refers to the quantizer levels of the second stage, $V_{FS}$ is the full-scale voltage, M is the oversampling ratio, and N is the total order of noise shaping of the MASH architecture.

3.1. Multi-Bit Quantization in MASH-QE, MASH-LI, and EC

All the architectures are simulated using an OSR = 60 and three-bit quantizer in the first stage. Table 1 shows the multi-bit (MB) scaling coefficients used in the second-order first stage. The inter-stage gain g is 1 for all the architectures. The design parameters are chosen to achieve an SQNR of around 110 dB at an input amplitude of a −6 dBFS sinusoidal signal. The second stage employs an eight-bit quantizer in the case of a zero-order second stage and a four-bit quantizer in the case of a first-order IDSM in the second stage. In the case of the 2-1 EC architecture, the second stage runs the same $M=M_2=60$ clock cycles to have comparable effort as in the 2-1 MASHs. Inserting the simulation parameters in Equation (2) leads to

$$SQNR\approx 2·20log\left(60\right)+20log(256-1)-20log\left(2\right)\approx 113.24\mathrm{dB}$$

(3)

for the 2-0 MASH-QE and to

$$SQNR\approx 3·20log\left(60\right)+20log(16-1)-20log\left(6\right)\approx 114.65\mathrm{dB}$$

(4)

for the 2-1 MASH-QE. Both architectures give similar SQNR values. Figure 4 shows the simulated SQNR. All architectures can achieve the same SQNR as intended. Furthermore, it can be observed that the MASH-LI and the 2-0 EC have slightly lower SQNR values than the MASH-QE. The reason can be found in the delayed passing of the quantization error of the first to the second stage and is also reflected in the SQNR equation for the MASH-LI:

$$SQNR\approx N·20log(M-N_1)+20log(L_2-1)-20log(N!)$$

(5)

$N_1$ is the order of the first stage of the I-DSM. Inserting the simulation parameters leads to

$$SQNR\approx 3·20log(60-2)+20log(16-1)-20log\left(6\right)\approx 113.76\mathrm{dB}$$

(6)

for the 2-1 MASH-LI. Interestingly, the 2-1 EC behaves differently with 10 dB higher SQNR. The reason is that we use the same number of operating cycles $M_2=60$ for the first-order second stage in the 2-1 EC architecture as for all first stages. A first-order I-DS ADC with 4-bit quantization and $M_2=60$ achieves almost 10-bit resolution, whereas the zeroth-order second stage is simulated with only 8-bit resolution. This yields the significantly better SQNR of the 2-1 EC. The 2-1 MASH architectures, on the other hand, behave like a third-order I-DS ADC with a four-bit quantizer in the second stage and therefore cannot achieve the same high resolution as the 2-1 EC, which basically adds the resolution of the second stage to the resolution of the first stage. This fact can be shown analytically by looking at the SQNR equation of the EC architecture:

$$\begin{array}{c}\hfill SQNR\approx N_1·20log\left(M\right)+N_2·20log(M-N_1)\\ \hfill +20log(L_2-1)-20log(N_1!)-20log(N_2!)\end{array}$$

(7)

From this, it can be concluded that the difference between 2-1 MASH and 2-1 EC is independent of the number of cycles in the second stage if the same number of cycles is used as in MASH, but the difference is rather a constant number that comes from the reconstruction filters; the difference in SQNR is

$$SQN{R}_{diff}\approx 20log(N!)-20log(N_1!)-20log(N_2!),$$

(8)

which leads to a difference in SQNR of

$$SQN{R}_{diff}\approx 20log(3!)-20log(2!)\approx 9.54\mathrm{dB}$$

(9)

as can be seen in Figure 4.

3.1.1. Including Swing Limitation

Using the same simulation conditions as in Figure 4, the simulation is repeated after adding limitation to swings at all nodes, where the quantization error of the first stage is extracted and passed to the second stage, i.e., the input of the quantizer and the last integrator output.

The simulated SQNR is shown in Figure 5. Unlike the ideal simulation in Figure 4, the MSA of the MASH-QE drops significantly. Close to the MSA, the quantizer input experiences the largest signal, slowly starting to overload the quantizer. While in a single-stage I-DSM, this usually yields a smooth reduction in SQNR and finally instability by overload, this is different in a multi-stage design. The adder preceding the quantizer experiences the largest output swing and will clip the large swings as the input signals increase. The MASH-LI and the EC architectures extract the first stage quantization error in the analog domain from the output of the last integrator, while the QE architecture relies on an exact extraction of the quantization error by a subtraction of the quantizer input (adder output) from the quantizer output. For illustration, Figure 6 shows the histogram of the adder output at an input signal of −6 dBFS and −3 dBFS, respectively. In comparison, the histogram of the last integrator output (relevant for MASH-LI) and the histogram of the last sample of the last integrator output (relevant for EC) are shown in Figure 7. While the adder output is still within a full-scale range (normalized to $\pm 1$) for the low input, the output of the adder increases above the full-scale range and will be chopped off by the limiter. Accordingly, the subtraction between the quantizer input and the quantizer output does not extract the correct quantization error for high inputs and leads to the performance degradation seen in Figure 5. In contrast, the output of the last integrator is limited to $\pm V_{LSB}/2$, defined by the employed three-bit quantizer in the first stage, which does not experience clipping. Thus correct requantization can be achieved for the MASH-LI and the EC architectures at large input signals.

3.1.2. Inter-Stage Gain

The idea of inter-stage gain g in multi-stage architectures as in Figure 2a and Figure 3a is to increase the extracted quantization error of the first stage to the full-scale range of the requantizing second stage. Since the inter-stage gain g is subsequently undone in the digital domain, cf. Figure 2a and Figure 3a, this decreases the added quantization error of the second stage, effectively increasing its resolution [1]. With the exemplary three-bit quantization in the first stage, the quantization error is limited between $\pm V_{LSB}/2=FS/2^3$. In practice, the inter-stage gain cannot be at its maximum, $g_{max}=2^3$, but remains slightly below to not overload the second stage quantization.

Figure 8 shows the simulated SQNR using the prior simulation conditions of Figure 5, but including an inter-stage gain $g=6$. For lower input amplitudes, the SQNR of all employed architectures increases by $g=6$. Only at large input amplitudes, we see differences, the reason for which can be explained: as discussed, the quantization error must be correctly extracted, which is not the case for large input signals for the MASH-QE due to the clipping of the adder output (quantizer input). Moreover, large input signals will still also increase the quantization error if extracted at the output of the last integrator. Thus, the inter-stage gain will start to slowly overload the second stage. Both EC variants and the 2-0 MASH-LI slightly lose MSA, as every overload of the second stage will heavily decrease the accuracy of the requantization and its subtraction from the overall output. Interestingly, the 2-1 MASH-LI loses the least performance. This is because even if the second stage first-order I-DSM is slightly overloaded, it still maintains a reasonably high SQNR.

3.1.3. Simulation over OSR

The six architectures, including inter-stage gain $g=6$ and swing limitation are simulated across different OSR values, from 8 to 60 in Figure 9. The first stage uses a 3-bit quantizer and the second stage uses an 8-bit quantizer in the case of (2-0) and a 4-bit quantizer in the case of (2-1). The input amplitude is a −6 dBFS sinusoidal signal. Obviously, the architectures relying on noise-shaping in the second stage (2-1) drop faster in performance for decreasing OSR than the architectures that rely on the intrinsically higher resolution of the second-stage quantizer (2-0).

Another difference becomes visible at low OSR, which was also visible in the earlier simulations: the MASH-QE achieves slightly better performance than the MASH-LI, which becomes more prominent for low OSR. This is explained as follows: deriving the analysis of the analog quantization error appearing at the output of the last integrator in an I-DSM [25], the analog quantization error is delayed against the actual quantization error by the loop filter, and its delay depends on the number of delaying integrators. This delay is accounted for in the digital recombination filters in Figure 2a, and for a constant number of operational cycles, it causes two cycles of the first stage to be omitted. This reduces signal power, which becomes more prominent for low OSR and thus a larger ratio of omitted cycles vs OSR.

A similar effect appears in the EC architecture. There, the second stage requantizes the last integrator output (quantization error) of the last operation cycle M of the first stage. But this corresponds to the quantization error of two cycles before, which, if subtracted from the digital output of the first stage, would result in erroneous output. Thus, also in the case of EC, the two-clock cycle delay has to be accounted for. These result match with Equations (5), (7) and (8).

3.2. Single-Bit Quantization in MASH-QE, MASH-LI, and EC

MB quantization in DSM requires an MB DAC in the feedback, which not only needs the resolution of the internal quantizer but also needs the linearity performance of the overall Delta-Sigma (DS) ADC [1], which is very challenging. For this reason, many multi-stage and multi-step architectures employ single-bit (SB) quantization in the first stage [20]. The SB coefficients in Table 1 are used together with a single-bit quantizer in the first stage of all the exemplary IDSM shown in Section 2 with an OSR = 100. The second stage employs an eight-bit quantizer for 2-0 MASH/EC, and a four-bit quantizer for 2-1 MASH/EC. The coefficients are scaled to allow a full-scale input to the second stage in order to have a fair comparison. In the case of the 2-1 EC architecture, the second stage runs the same $M_2=M=100$ clock cycles to have comparable effort as in the 2-1 MASHs. The inter-stage gain is 1 for all the architectures and cannot be increased anymore without losing MSA.

Figure 10 shows the simulated SQNR, and similar to Figure 5, all swings are limited. A few new findings can be summarized: The MASH-QE still suffers from reduced MSA at high input signals. More interestingly, MASH-QE has an overall smaller SQNR than the MASH-LI in opposition to the MB case, cf Figure 5. Also, the SQNR of the 2-1 EC was largely better than that of 2-1 MASH in Figure 5, which is not the case anymore. Moreover, the 2-0 EC shows no longer identical performance as the 2-0 MASH-LI, as in the case of the MB simulation in Figure 5, and the 2-0 EC is lower by 7 dB. The reasons for these findings will be explained in the following paragraphs.

3.2.1. Similarities and Differences Between EC and MASH-LI

To explain this behavior, we should have a look at the digital filter $H_{1,2}$ in Figure 2a. The digital filter for MASH-QE are easily derived to be $H_1=ST{F}_2$ and $H_2=NT{F}_1$ [1,10,26]. This is not only different for MASH-LI, but one can even derive two alternative versions for its digital recombination logic $H_{1,2}$ in Figure 2a. Let $H_{\mathrm{int}}\left(z\right)$ be the transfer function from the quantizer output to the output of the last integrator. Then, the first version of the recombination logic for MASH-LI is

$$\begin{array}{cc}\hfill H_1\left(z\right)& =NT{F}_1\left(z\right)·ST{F}_2\left(z\right)·H_{\mathrm{int}}\left(z\right)\hfill \\ \hfill H_2\left(z\right)& =NT{F}_1\left(z\right),\hfill \end{array}$$

(10)

which is called error cancellation logic ECL_LI,1 in the remainder of the work. This is the version that was chosen for all the simulations of MASH-LI so far. The second version of the recombination logic can be derived as

$$\begin{array}{cc}\hfill H_1\left(z\right)& =ST{F}_2\left(z\right)\hfill \\ \hfill H_2\left(z\right)& =1/H_{\mathrm{int}}\left(z\right).\hfill \end{array}$$

(11)

This version of error cancellation logic is referred to as ECL_LI,2. From this, we can explain why in the multi-bit case, 2-0 MASH-LI behaved identically to 2-0 EC, but not in the single-bit case. One can derive that using ECL_LI,2, this makes a 2-0 MASH-LI mathematically identical to 2-0 EC. In the multi-bit case, due to the used scaling coefficients shown in Table 1, $H_{int}\left(z\right)=1/NT{F}_1\left(z\right)$, which makes the two versions of the digital filters identical, ECL_LI,1 = ECL_LI,2. Thus, 2-0 MASH-LI and 2-0 EC are identical architectures in the multi-bit case, but not in the single-bit case. Consequently, in order to explain the worse performance of the 2-0 EC compared to the 2-0 MASH-LI in the single-bit case, we look at the differences between the MASH-LI using ECL_LI,1 or ECL_LI,2. For this, it is helpful to have a look at their overall noise transfer functions (NTFs) [27], which are shown in Figure 11. The solid lines use a single-bit quantizer in the first stage and OSR = 100. The dashed lines use a three-bit quantizer in the first stage and OSR = 60. The second stage is an eight-bit quantizer for the two cases. Depending on loop-filter scaling, a significant difference can be seen in the higher-frequency range. While for the multi-bit scaling with OBG = 4, no difference between the NTFs is visible (cf. dashed lines in Figure 11), a less aggressive scaling yields a significantly higher quantization noise suppression in case of the ECL_LI,1 (solid blue).

To obtain a more intuitive explanation of the resulting SQNR difference in the single-bit case, it is helpful to have a look at the filter weights in Figure 12. There, it is shown how the output of the second stage is weighted by the digital filters $H_2\left(z\right)·H_{\mathrm{rec}}(z)$ for the two LI versions using either ECL_LI,1 in Figure 12a or ECL_LI,2 in Figure 12b. In this example, the first stage is scaled with the single-bit coefficients of Table 1 at an OSR of 100. A second-order CoI filter is used as a reconstruction filter. In both cases, it can be seen that most of the samples are weighted with zero and only the last few samples have an influence on the overall performance of the MASH-LI. The performance difference results from the fact that ECL_LI,1 uses approximately the last ten samples for the quantization noise suppression, while ECL_LI,2 only uses the last output sample of the second stage in the overall I-DS ADC output; the latter again emphasizing its identical behavior to a 2-0 EC. The amount of samples influencing the output of ECL_LI,1 depends on the scaling of the modulator. While in the single-bit case shown, approximately the last 10 samples have significant weight, re-simulating Figure 12a for the multi-bit case (OBG = 4) would yield that only the last sample is used and all other samples are weighted at zero. This is why, in the multi-bit case, no performance difference can be seen between the two LI architectures or between 2-0 MASH-LI and 2-0 EC.

3.2.2. Differences Between MASH-QE and MASH-LI

While in the multi-bit case, the MASH-QE showed a slightly higher resolution than the MASH-LI, cf. Figure 5, in the single-bit case, this behavior changed, cf. Figure 10. Thereby, both MASH versions (QE and LI) were scaled in a way that the second stage receives full-scale inputs close to the MSA to achieve a fair comparison. The reason behind this changed behavior is the quantizer gain, which is not unity anymore if a single-bit quantizer is used. To account for the quantizer gain in the MASH-QE, two new coefficients should be introduced before the subtraction around the quantizer of the first stage [28]. If these coefficients are added and scaled to account for the quantizer gain and the digital filters are adapted accordingly, the resolution advantage of the MASH-QE compared to the MASH-LI can be restored. The quantizer gain of I-DSM can be extracted following [29].

4. Non-Idealities: Mismatch and DC Gain

It is well known that multi-stage DSM architectures are sensitive against analog loop-filter variations due to the arising mismatch between the digital recombination filters and the analog loop filter. The same is true in multi-step ADCs because the fine quantization needs to match the scale of the coarse quantization. Consequently, the six exemplary architectures are compared in terms of their robustness against non-idealities. In detail, we investigate loop-filter coefficient variation and finite DC gain in the integrators.

4.1. Loop-Filter Coefficient Mismatch

First, analog vs. digital coefficient mismatch is investigated. Thereby, all coefficients of the first I-DSM stage are varied. Furthermore, the inter-stage gain, the feedback path in the second stage, and—in the QE case—the paths in front of the adder are also subject to a coefficient variation. The architectures are simulated as in Figure 8.

4.1.1. 2-0 MASH/EC

Figure 13 shows the simulated SQNR for the 2-0 architectures using OSR = 60, a three-bit quantizer in the first stage, and an eight-bit quantizer in the second stage. The inter-stage gain is set to 6. The simulations shown represent the average of 25 Monte Carlo runs of a Gaussian distribution around the nominal MB analog loop-filter scaling with a standard deviation of ${\sigma }_c$ as a percentage at an input amplitude of −6 dBFS sinusoidal signal. Additionally, the error bars depict the standard deviation $\sigma$ of the resulting SQNR values. The 2-0 MASH-QE is the most sensitive, while the 2-0 MASH-LI (and the 2-0 EC, which is mathematically identical to the 2-0 LI) are more robust.

This is because, in the case of 2-0 MASH-LI and 2-0 EC, the input to the second stage is not only the delayed version of the quantization error $E_1\left(z\right)$ but rather the delayed shaped quantization error [30] since the last integrator output

$$V\left(z\right)=E_1\left(z\right)·NT{F}_1\left(z\right)·H_{\mathrm{int}}\left(z\right),$$

(12)

is passed to the second stage. Thus, the mismatch has a smaller impact.

4.1.2. 2-1 MASH/EC

Figure 14 shows the simulated SQNR for the 2-1 architectures using OSR = 60, the three-bit quantizer in the first stage, and the four-bit quantizer in the second stage. An inter-stage gain of 6 is used. The shown simulations represent the average of 25 Monte Carlo runs of a Gaussian distribution around the nominal loop-filter scaling with a standard deviation of ${\sigma }_c$ as a percentage at an input amplitude of −6 dBFS sinusoidal signal. The error bars depict the standard deviation $\sigma$ of the resulting SQNR values. The 2-1 EC shows a similar sensitivity to coefficient variation as the 2-0 EC. This makes sense as in EC the second stage needs a certain resolution to requantize the quantization error from the first stage, and in 2-0, this resolution is achieved by quantizer resolution, and in 2-1 EC, it is achieved by a first-order I-DSM. Thus, the dominant non-ideality is the coefficient variation in the first stage and the incorrectly scaled quantization error it passes on to the second stage, which is basically identical in both cases. Interestingly, the 2-1 MASH architectures not only outperform the 2-1 EC, but also the 2-0 MASH architectures. At the time of writing, it has not been possible to determine where this improved performance comes from. The cause of this changed behavior will be the subject of further research.

4.2. Integrator Finite-DC Gain

It is well known [1,26] that the finite integrator DC gain is a dominant source of noise leakage in MASH DSM, causing the analog transfer function to deviate from its ideal value and produce a mismatch between analog and digital filters. Accordingly, the SQNR of all considered architectures is finally simulated with respect to the finite integrator DC gain. The results are shown in Figure 15 at an OSR of 60, an inter-stage gain of 6, and at an input amplitude of −6 dBFS sinusoidal signal. The first stage uses a three-bit quantizer and the second stage uses an eight-bit quantizer in the case of (2-0) and a four-bit quantizer in the case of (2-1). As expected, all the architectures degrade at low DC gain. While the 2-0 MASH architectures operate with second-order noise shaping and increase their resolution by higher quantizer resolution in the second stage, their performance drop against finite DC gain is lower compared to the 2-1 MASH architectures, which aim to achieve ideal higher-order noise-shaping and are thus more affected by finite integrator DC gain. Interestingly, the 2-1 EC architecture performs similarly to the 2-0 MASH ones at a low integrator DC gain. This can also be explained by the fact that it is only a second-order I-DSM, while its second stage is an independent (Nyquist-rate) ADC, either achieving its resolution by higher quantizer resolution or by a first-order noise shaping. Therefore, facing finite DC gain, it behaves more like a 2-0 MASH than a 2-1 MASH.

5. Discussion

Table 2. Comparison table of different architectures. SQNR values are at an input amplitude of −6 dBFS for (MB) and at −8 dBFS for (SB). The latency represents the number of clock cycles for one Nyquist conversion. Green indicates the highest-achieved values, while red indicates the lowest-achieved values.

Design Parameters	Tradeoffs	2-0 MASH-QE	2-1 MASH-QE	2-0 MASH-LI	2-1 MASH-LI	2-0 EC	2-1 EC
Multi-bit	SQNR [dB]	90.71	76.2	85.78	69.86	85.65	78.38
$M=8$	MSA [dBFS]	−3.88	−3.88	−2.05	−1.11	−2.05	−2.05
$g=6$	Latency	8	8	8	8	9	16
Multi-bit	SQNR [dB]	124.68	126.58	124.14	125.4	123.9	134.89
$M=60$	MSA [dBFS]	−3.88	−3.88	−2.05	−1.11	−2.05	−2.05
$g=6$	Latency	60	60	60	60	61	120
Single-bit	SQNR [dB]	109.45	114.15	112.47	117.68	105.16	121
$M=100$	MSA [dBFS]	−6.75	−6.38	−1.11	−1.21	−1.11	−1.11
$g=1$	Latency	100	100	100	100	101	200

provides a summary of the results presented in the manuscript. The reported SQNR values are obtained at an input amplitude of −6 dBFS for the multi-bit quantizer (MB) case and −8 dBFS for the single-bit (SB) case. The latency is given in clock cycles and corresponds to the number of operating cycles of the I-DSM (M) plus additional delay through digital filters or by additional cycles required for requantization in the second stage.

As was shown in Figure 9, at low OSR, there are more differences in SQNR between the architectures, specifically for MASH-LI and EC, due to the delayed quantization error accounted for in the digital recombination filters. In this case, 2-0 MASH-QE gives the highest SQNR but has the disadvantage of low MSA. At higher OSRs, the architectures provide similar SQNR values, with the exception of 2-1 EC, which significantly provides the highest SQNR with a reasonable MSA but at the cost of higher latency and greater sensitivity to coefficient mismatch. However, the 2-1 EC has another advantage over 2-1 MASH architectures, which is the lower noise penalty factor. The 2-0 MASH-LI and 2-0 EC have a higher MSA compared to MASH-QE and also have better mismatch behavior compared to 2-0 MASH-QE, as discussed in Section 4. The 2-1 MASH-LI has the highest SQNR in terms of mismatch and the highest MSA, making it another good architectural choice alongside the 2-1 EC. In the case of a single-bit quantizer, MASH-QEs drop even more in MSA. The 2-0 EC has the lowest SQNR and 2-1 EC has a comparable SQNR with higher latency, but again with the advantage of a lower noise penalty factor. The 2-1 MASH-LI achieves a good SQNR. Therefore, the 2-1 MASH-LI and 2-1 EC are good candidates for an efficient multi-step/stage incremental delta-sigma ADC.

6. Conclusions

This paper gives an overview of multi-stage/-step incremental DSM architectures. The different architectures were compared using system-level simulations, and the advantages and disadvantages of the different architectures were highlighted. It has been demonstrated that the QE architectures are prone to a reduction in MSA and the necessity for an additional DAC. Furthermore, it was elucidated that the 2-1 EC exhibits a reduced noise penalty factor, thereby demonstrating superior thermal noise behavior. Non-idealities such as coefficient variation and finite DC gain were also included in the comparison, and the results are summarized in Table 2 and discussed. For future research, it would be interesting to compare these architectures in prototypes and to provide analysis and equations to precisely predict the SQNR of I-DS ADCs for MASH, including non-idealities.