A 13–33 GHz Wideband Low-Noise Amplifier in 150-nm GaAs Based on Simultaneous Noise- and Input-Matched Gain-Core with R-L-C Shunt Feedback Network

Abstract

This work reports the concept of a shunt negative feedback technique for implementing a millimeter-wave wideband low-noise amplifier. The proposed shunt negative feedback network consists of a resistor–capacitor–inductor configuration. The proposed feedback network can achieve simultaneous noise and input matching (SNIM) over a wide frequency range by adjusting the values of the resistor–capacitor–inductor configuration based on numerical analysis. By adopting the SNIM-based gain core as the first stage of the amplifier, the simulation results of the three-stage low-noise amplifier in a 150-nm GaAs pHEMT process achieve a gain of 15.6–18.6 dB and a noise figure of 1.05–2.8 dB in the frequency range of 13–33 GHz, respectively, while dissipating 99 mW.

1. Introduction

Recently, the Ku (12–18 GHz), K (18–26.5 GHz), and Ka (26.5–40 GHz) bands have become essential for advanced communication, radar, and sensing technologies, as each band provides distinct benefits that enable a wide range of applications [1].

A radio transceiver is a crucial component in the applications mentioned above. For the transceiver link budget, the sensitivity of the receiver is a key performance metric. This sensitivity is highly dependent on the performance of the low-noise amplifier (LNA), particularly its gain and noise figure (NF).

The gallium arsenide (GaAs) process offers several advantages over CMOS technology, particularly for implementing LNAs in high-frequency applications. The GaAs process has inherently higher electron mobility, which enables GaAs-based LNAs to achieve superior gain and bandwidth performance [2]. Another advantage of the GaAs process is its low-noise characteristics. Compared to silicon-based devices, GaAs has higher electron mobility, which can effectively reduce resistive losses and thermal noise. In addition, due to its structural characteristics, it has low resistive noise, which enables it to maintain excellent signal quality even in the high frequency band. In particular, GaAs-based HEMTs provide excellent low-noise amplification characteristics in the high-frequency band by forming high-speed electron transport channels [3,4]. Therefore, GaAs-based LNAs are preferred for high-frequency, high-sensitivity applications, as they provide high gain and a low noise figure over a wide frequency range.

Much previous work on GaAs-based low-noise amplifiers (LNAs) has been reported, covering a wide range of frequency bands, including 1–12.5 GHz [5], 10–20 GHz [6], 24.25–33 GHz [7], and 40–51 GHz [8]. These studies primarily focus on broadband designs to meet the demands of various applications. The primary objective of LNA design is to achieve maximum gain while minimizing the noise figure (NF) within the target frequency band. However, previous work exhibits a major limitation in that simultaneous noise and input matching (SNIM) is restricted to a narrow range relative to the target frequency band [5,9,10].

To overcome the aforementioned limitations, this article proposes a wideband simultaneous noise- and input-matched gain core design technique that leverages the advantages of an R-L-C shunt feedback network. By adopting the proposed gain core as the first stage of a three-stage low-noise amplifier, it achieves high gain and a low NF within the targeted frequency range.

The rest of this article is organized as follows. Section 2 introduces the limitations of conventional SNIM techniques. Next, Section 3 describes the proposed R-L-C shunt feedback network along with precise design methodology and implementation details. Subsequently, Section 4 presents the simulation results of the proposed three-stage low-noise amplifier adopting the R-L-C shunt feedback network. Finally, Section 5 concludes this article.

2. Limitations of Conventional SNIM Techniques

The simultaneous noise and input matching (SNIM) technique is widely adopted in millimeter-wave LNA design to achieve both optimal noise and gain matching simultaneously [11]. While the SNIM technique offers significant benefits for achieving both optimal noise and gain performance at the input node of a transistor, it also has several limitations that impact its overall usefulness.

In a conventional common-source (CS) topology without a source degeneration inductor, the input impedance ($Z_{in}$) is entirely imaginary, with no real part [12]. However, the optimum noise impedance ($Z_{opt}$) has both real and imaginary parts. Therefore, achieving SNIM that satisfies $Z_{in}^{*}=Z_{opt}$ is not possible by adding an input matching network to a CS topology without inductive source degeneration [12]. By adopting a source degeneration inductor ($L_s$) at the source terminal of the input transistor, $Z_{in}$ can be derived as [13]

$$\begin{array}{c}\hfill Z_{in}=s{L}_s+{\displaystyle \frac{1}{s{C}_{gs}}}+{\displaystyle \frac{g_m{L}_s}{C_{gs}}}\end{array}$$

(1)

where $C_{gs}$ is the gate-source capacitance of the transistor, and $g_m$ is the transconductance of the transistor. As shown in (1), the real part of the impedance ($g_m{L}_s/C_{gs}$) can be generated by adopting Ls [13], which can be utilized to achieve SNIM.

Figure 1 shows the schematics of conventional CS topologies for achieving simultaneous noise and input matching. In Figure 1a, the CS topology incorporates $L_s$ and an input matching network with a series inductor ($L_g$) at the gate node. The condition for satisfying SNIM ($Z_{in}^{*}=Z_{opt}$) can be achieved by adjusting the values of $L_s$ and $L_g$.

However, inductive source degeneration has certain limitations. When small-sized transistors are used, the real part of $Z_{opt}$ increases significantly, which requires a larger value of $L_s$ to achieve SNIM [12]. The implementation of a required large value of $L_s$ results in a larger chip size and is also constrained by the design rules provided by the foundry. Furthermore, a large value of $L_s$ can significantly degrade $N{F}_{min}$ and the power gain of the transistor [14].

To overcome the aforementioned challenges in the SNIM technique with $L_s$ in Figure 1a, a power-constrained SNIM (PCSNIM) is proposed. In Figure 1b, the CS topology adopts $L_s$ and $L_g$ at the gate node, along with a capacitor ($C_{ex}$) added between the gate and source nodes. By incorporating $C_{ex}$ between the gate and source terminals, the required large value of $L_s$ can be reduced [12].

However, PCSNIM also has several limitations. A larger $C_{ex}$ facilitates achieving SNIM by reducing the required inductance ($L_s$) but results in a decrease in power gain [12]. In addition, a small transistor size increases the noise resistance ($R_n$), causing the NF of the LNA to rise sharply at frequencies away from the optimum frequency, resulting in narrow-band noise matching [12]. To address the mentioned issue, the proposed technique for achieving wideband SNIM using shunt R-L-C feedback is introduced in Section 3.

3. Proposed R-L-C Shunt Feedback Network

3.1. Choice of Transistor Size

To achieve high performance in a millimeter-wave LNA, the size of the transistors must be carefully selected. In this work, the target frequency range is set to 15 to 33 GHz. The overall noise factor (F) of the multi-stage amplifier is expressed as [15]

$$\begin{array}{c}\hfill F=F_1+{\displaystyle \frac{F_2-1}{G_1}}+{\displaystyle \frac{F_3-1}{G_1{G}_2}}+\cdots ,\end{array}$$

(2)

where $F_n$ and $G_n$ represent the noise factor and gain of the nth amplification stage, respectively. As in (2), in low-noise amplifier design, the gain and noise factor of the first stage of the amplifier dominate the overall noise performance.

Figure 2 shows the simulated maximum available gain ($G_{ma}$) and minimum noise figure ($N{F}_{min}$) for varying transistor widths with different numbers of fingers (NoF). While $G_{ma}$ tends to increase as the transistor width increases, the change is relatively small. Moreover, the change in $G_{ma}$ with respect to the number of fingers is negligible. In the design, more focus was placed on optimizing the overall noise performance of the circuit. As a result, the width and number of fingers (NoF) of the first-stage transistor were selected to achieve the lowest possible minimum noise figure ($N{F}_{min}$) within the target bandwidth. As shown in Figure 2d, a width of 40 μm and NoF of 6 are selected since they provide the lowest $N{F}_{min}$ within the target bandwidth of 15–33 GHz.

Figure 3 shows the variation of the gain matching points and the noise matching points of a transistor with a width of 40 μm and NoF of 6 as the frequency changes on a Smith chart. The transistor itself, in a common-source topology, cannot achieve the simultaneous noise and gain matching condition. To resolve this issue, a shunt R-L-C feedback network is proposed, and the design details are explained in Section 3.2.

3.2. R-L-C Feedback Network

Figure 4 shows the schematic of the gain core with the proposed shunt R-L-C feedback network and its equivalent small-signal model. The proposed shunt R-L-C feedback consists of a resistor ($R_F$), an inductor ($L_F$), and a capacitor ($C_F$); $C_F$ is used for DC blocking purposes. It is assumed to be a sufficiently large value and is ignored in the analysis in Figure 4b. In Figure 4b, $C_{gd}$ and $C_{gs}$ are the parasitic capacitances of the transistor.

In Figure 4, the voltage gains of the core circuit with ($A_F$) and without (A) the shunt feedback network are expressed as

$$A_F=-g_m\left[Z_L\left|\right|(R_F+s{L}_F)\left|\right|{\displaystyle \frac{1}{s{C}_{gd}}}\right]=-{\displaystyle \frac{g_m{Z}_L(R_F+s{L}_F)}{s^2{C}_{gd}{L}_F{Z}_L+s\left(C_{gd}{Z}_L{R}_F+L_F\right)+Z_L+R_F}}.$$

(3)

and

$$A=-g_m{Z}_L,$$

(4)

respectively. Compared to (4), (3) can be adjusted by varying the combinations of feedback components ($L_F$ and $R_F$). The ratio of $A_F$ to A (R) is expressed as [16]

$$R={\displaystyle \frac{A_F}{A}}={\displaystyle \frac{R_F+j\omega L_F}{j\omega \left(C_{gd}{Z}_L{R}_F+L_F\right)-{\omega }^2{C}_{gd}{L}_F{Z}_L+Z_L+R_F}}.$$

(5)

In (5), depending on the values of the feedback components ($L_F$ and $R_F$), the shunt feedback network can operate in either positive feedback ($R>1$) or negative feedback ($R<1$) mode. This variation in the feedback components can affect the gain, noise figure, bandwidth, and impedance matching condition of the amplifier. Therefore, for achieving wideband SNIM operation, the values of the feedback components should be carefully chosen.

3.3. Design of R-L-C Shunt Feedback Network

For wideband operation, the gain core is designed to operate with negative feedback. As mentioned in the previous section, $C_F$ is a DC decoupling capacitor. To simplify the analysis, $C_F$ is chosen to be a sufficiently large value to have a negligible effect on the frequency response ($\omega L_F\gg {\displaystyle \frac{1}{\omega C_F}}$). A value of 9 pF is chosen as a design point, which rarely affects the frequency response for all available $L_F$ values (0.12 nH to 12.65 nH) provided by the process used in the design.

The effectiveness of the conventional voltage gain analysis is limited at high frequencies due to parasitic effects. Therefore, power gain using numerical two-port network methods is more suitable for high-frequency circuit analysis.

Figure 5 shows the schematic of the gain core with the R-L-C shunt feedback and its Y-parameter-based equivalent model. The $G_{ma}$ is defined as [17]

$$G_{ma}={\displaystyle \frac{\left|S_{21}\right|}{\left|S_{12}\right|}}\left(k-\sqrt{k^2-1}\right),$$

(6)

where k represents the Rollet’s stability factor. Equation (6) can be re-expressed as

$$G_{ma}={\displaystyle \frac{\left|Y_{21}\right|}{\left|Y_{12}\right|}}\left(k-\sqrt{k^2-1}\right).$$

(7)

in terms of Y-parameters.

Assuming that the capacitance is sufficiently large and can be ignored, the admittance of the feedback network ($Y_F$) in Figure 5 is expressed as

$$Y_F=\left[\begin{array}{cc}{Y}_{11F}& Y_{12F}\\ Y_{21F}& Y_{22F}\end{array}\right]=\left[\begin{array}{cc}{\displaystyle \frac{1}{R_F+j\omega L_F}}& -{\displaystyle \frac{1}{R_F+j\omega L_F}}\\ -{\displaystyle \frac{1}{R_F+j\omega L_F}}& {\displaystyle \frac{1}{R_F+j\omega L_F}}\end{array}\right].$$

(8)

The admittance of the transistor ($Y_{M1}$) extracted through SPICE simulation is expressed as

$$Y_{M1}=\left[\begin{array}{cc}{Y}_{11M1}& Y_{12M1}\\ Y_{21M1}& Y_{22M1}\end{array}\right].$$

(9)

Therefore, the Y-parameter of the gain core ($Y_{eq}$), which consists of the parallel configuration of $Y_F$ and $Y_{M1}$, is given by

$$\begin{array}{cc}\hfill Y_{eq}=Y_F+Y_{M1}& =\left[\begin{array}{cc}{Y}_{11F}+Y_{11M1}& Y_{12F}+Y_{12M1}\\ Y_{21F}+Y_{21M1}& Y_{22F}+Y_{22M1}\end{array}\right]\hfill \\ \hfill & =\left[\begin{array}{cc}{\displaystyle \frac{1}{R_F+j\omega L_F}}+Y_{11M1}& -{\displaystyle \frac{1}{R_F+j\omega L_F}}+Y_{12M1}\\ -{\displaystyle \frac{1}{R_F+j\omega L_F}}+Y_{21M1}& {\displaystyle \frac{1}{R_F+j\omega L_F}}+Y_{22M1}\end{array}\right].\hfill \end{array}$$

(10)

By substituting (10) into (7), $G_{ma}$ of the gain core ($G_{ma,eq}$) can be expressed as

$$\begin{array}{cc}\hfill G_{ma,eq}& ={\displaystyle \frac{\left|Y_{21eq}\right|}{\left|Y_{12eq}\right|}}\left(k-\sqrt{k^2-1}\right)\hfill \\ \hfill & ={\displaystyle \frac{\left|-\frac{1}{R_F+j\omega L_F}+Y_{12M1}\right|}{\left|-\frac{1}{R_F+j\omega L_F}+Y_{21M1}\right|}}\left(k-\sqrt{k^2-1}\right).\hfill \end{array}$$

(11)

As in (11), the power gain can be adjusted by varying the values of $R_F$ and $L_F$.

Figure 6 shows the calculated $G_{ma,eq}$ in (11) for variations in $R_F$ and $L_F$ at 15 GHz, 24 GHz, and 33 GHz. The simulated inductor range (0.2–12 nH) was determined based on verified inductor values available in the PDK used for the design. For the simulated resistor range, a value between 0 and 1000 Ω was chosen to ensure practical implementation and to avoid excessively large resistor values that could negatively affect the design. This approach ensures that the analysis remains grounded in realistic component values, reflecting the constraints and capabilities of the design process. To enhance circuit stability and extend bandwidth, the feedback network configuration is selected to operate within the negative feedback region. The plane parallel to the $R_F$ and $L_F$-axis (shown in red) in the graph represents the intrinsic gain of the transistor ($G_{ma}$) without the feedback network. The area below this plane indicates that the feedback network operates with negative feedback, while the area above it indicates positive feedback. The area that operates with negative feedback at each frequency is highlighted with a black solid line for clearer visualization on the right side of Figure 6. The values of $R_F$ and $L_F$ are selected within this range. At 15 GHz, compared to 24 and 32 GHz, most of the region operates with positive feedback, whereas only a small portion within the target band exhibits negative feedback. To operate in the negative feedback mode within the target frequency band, the range of $R_F$ and $L_F$ values is approximately $R_F$ = 650 Ω to 1000 Ω and $L_F$ = 0.12 nH to 1.4 nH, as indicated by the dashed lines on the right side of Figure 6a. As shown in Figure 6a, the variation in $G_{ma,eq}$ is relatively minor with changes in the $R_F$ value, while changes in the $L_F$ value significantly impact $G_{ma,eq}$ within the negative feedback range. To prevent $G_{ma}$ from dropping excessively in this range, $L_F$ is set to 1.2 nH. The choice of the optimum value of $R_F$ will be explained in the next paragraph.

Figure 7 shows the variations in the noise matching points with the 0.2 dB noise circles and the gain matching points of the gain core with an R-L-C feedback network according to various $R_F$ values. As mentioned before, $L_F$ is fixed to 1.2 nH. As $R_F$ increases, the gain matching points and noise matching points gradually converge. When $R_F$ = 1000 Ω, the gain matching points fall almost entirely within the 0.2 dB noise circle across the target frequency range. Therefore, the final design values for $R_F$, $L_F$, and $C_F$ are 1000 Ω, 1.2 nH, and 9 pF, respectively, enabling wideband SNIM under these conditions.

4. Implementation and Simulation Results of a Three-Stage Low-Noise Amplifier

To demonstrate the feasibility of the proposed R-L-C shunt feedback network, a three-stage low-noise amplifier is designed using a 150 nm GaAs pHEMT process. Figure 8 shows the schematic of the proposed three-stage LNA. The proposed gain core with the R-L-C shunt feedback network is adopted as the first stage with a transistor dimension of 6 × 40 μm to achieve SNIM. The subsequent second and third stages adopt transistor dimensions of 6 × 50 μm and 6 × 60 μm, respectively, to enhance linearity.

Figure 9 shows a layout of the proposed three-stage LNA. The overall chip area of the designed amplifier is 2.2 × 1.5 mm² (3.3 mm²) including DC bias, input, and output pads. All stages are biased with VGS = −0.6 V and VDS = 2 V, resulting in a total current consumption of 49.3 mA and a DC power consumption of 99 mW. The bias line consists of a transmission line and an inductor in a series configuration, with a capacitor and resistor in a shunt configuration. Especially for gate biasing, small resistors are inserted in the series path to improve stability. It is noted that DC bias circuitries should be carefully designed for wideband operation since they also affect the matching conditions. The input and output matching networks adopt high-order matching networks to ensure wideband operation. All matching components are implemented using microstrip lines.

Figure 10 shows the simulated S-parameters versus frequency, noise figure versus frequency, k and $\left|\Delta \right|$ versus frequency, and $O{P}_{1dB}$ and PAE versus frequency of the proposed LNA. As shown in Figure 10a, the simulation results show a 3-dB bandwidth of 20 GHz (13–33 GHz), power gains ($S_{21}$) of 17.1 ± 1.5 dB, and relatively wideband input matching. In Figure 10b, the NF also shows a flat response within the targeted frequency range and remains below 2.1 dB. Considering the results of input matching and NF, the concept of the proposed wideband SNIM-based gain core with shunt R-L-C feedback is successfully demonstrated. In Figure 10c, the unconditional stability ($k>1$ and $\left|\Delta \right|=\left|S_{11}{S}_{22}-S_{12}{S}_{21}\right|<1$) of the amplifier is verified by simulation at all frequencies (DC to $f_{max}$) at the input and output terminals. The simulated peak output $P_{1dB}$ ($O{P}_{1dB}$) and power-added efficiency (PAE) at input $P_{1dB}$ are 12.8 dBm and 14.2 %, respectively.

Figure 11 and Figure 12 show the simulated S-parameters, (a) Rollett’s stability factor, and (b) noise figure from a Monte Carlo analysis using 2000 samples at a center frequency of 24 GHz to evaluate the impact of process, voltage, and temperature (PVT) variations. The histograms represent $S_{11}$, $S_{22}$, $S_{21}$, $S_{12}$, Rollett’s stability factor, and NF, respectively. As shown in Figure 11, the variations in the S-parameters are less than 1 dB. In Figure 12, the variations in the noise figure (NF) are less than 0.08 dB, and the designed amplifier shows the unconditional stability. Therefore, the Monte Carlo analysis with 2000 samples confirmed the robustness of the designed amplifier under process, voltage, and temperature (PVT) variations, highlighting the amplifier’s consistent performance and reliability.

Table 1. Performance summary in comparison with state-of-the-art GaAs-based amplifiers operating in the Ku (12–18 GHz), K (18–26.5 GHz), and Ka (26.5–40 GHz) bands.

	Process	Topology	Frequency (GHz)	Bandwidth * (GHz)	Gain ** (dB)	Noise Figure (dB)	${\mathit{P}}_{\mathit{DC}}$ (mW)	Area (mm2)	FOM ***
[19] (measured)	GaAs 100 nm	2-stage CS with R-L-C shunt feedback	18.7–36.5	17.8	15.9	1.5–2.1	66	0.96	4.08
[7] (simulated)	GaAs 150 nm	3-stage CS with R-L-C shunt feedback	24.25–33	8.75	19.8	2.2–2.8	-	1.24	-
[20] (measured)	GaAs 150 nm	3-stage CS with resistive feedback	15–25	10	30	1.25–2	212	1.87	4.47
[21] (measured)	GaAs 70 nm	2-stage CS with self-based network	26.5–31.5	5	18	1.3–1.7	115	3.6	0.99
[22] (simulated)	GaAs 100 nm	4-stage CS	23–29	6	33	1.4–2	118.2	5.94	5.96
[23] (simulated)	GaAs 100 nm	4-stage CS	26–36	10	33	1.5–1.8	-	3.64	-
This Work (simulated)	GaAs 150 nm	3-stage CS with R-L-C shunt feedback	13–33	20	18.6	1.05–2.1 (15–33 GHz) 1.05–2.8 (13–33 GHz)	99	3.3	6.29

* 3-dB bandwidth, ** Maximum gain in 3-dB bandwidth, *** FoM = (S₂₁ · bandwidth)/((NF − 1) · P_DC).

shows the performance summary in comparison with state-of-the-art GaAs-based amplifiers operating between 10 and 40 GHz. The proposed amplifier shows comparable performance in terms of NF, power dissipation, and bandwidth. The figure of merit (FOM) is provided to give an overview of the performance of a circuit and is defined as follows [18]:

$$FOM={\displaystyle \frac{S_{21}·Bandwidth}{(NF-1)·P_{DC}}},$$

(12)

where bandwidth, $S_{21}$, NF, and PDC represent 3-dB bandwidth, maximum gain, minimum noise figure within 3-dB bandwidth, and DC power consumption, respectively. As shown in the comparison table, the proposed design achieves the highest FOM.

5. Conclusions

In this paper, we presented the design and implementation of a wideband low-noise amplifier (LNA) employing an R-L-C shunt feedback network to achieve simultaneous noise and input matching (SNIM) over a broad frequency range. The proposed feedback network, consisting of resistor (R), inductor (L), and capacitor (C) components, enables precise control over impedance matching and noise figure, addressing limitations observed in conventional SNIM techniques. By utilizing this feedback network in the first stage of a three-stage LNA, the amplifier achieves significant improvements in gain, noise performance, and stability. The three-stage LNA, fabricated using a 150-nm GaAs pHEMT process, demonstrates a measured gain of 15.6–18.6 dB and a noise figure (NF) of 1.05–2.1 dB within the operating frequency range of 15–33 GHz. The amplifier maintains unconditional stability across the entire frequency band, with a total power dissipation of 99 mW. A Monte Carlo analysis with 2000 samples confirmed the robustness of the design under process, voltage, and temperature (PVT) variations, highlighting the amplifier’s consistent performance and reliability. Comparison with state-of-the-art GaAs-based LNAs operating within similar frequency ranges shows that the proposed design achieves competitive results in terms of bandwidth, noise figure, and gain. Notably, the amplifier attains the highest figure of merit (FOM), demonstrating the effectiveness of the R-L-C shunt feedback network in enhancing wideband performance. The design approach outlined in this work provides a pathway for developing high-performance LNAs suitable for advanced communication, radar, and sensing applications in the Ku, K, and Ka bands.