5GHz CMOS All-Pass Filter-Based True Time Delay Cell
Abstract
:1. Introduction
2. Proposed First-Order All-Pass Filter
3. Circuit Optimization and Tunability
Non-Ideality Analysis
4. Results
5. Discussion
Author Contributions
Funding
Conflicts of Interest
References
- Buckwalter, J.; Hajimiri, A. An active analog delay and the delay reference loop. In Proceedings of the IEEE Radio Frequency Integrated Circuits (RFIC) Systems, Fort Worth, TX, USA, 6–8 June 2004. [Google Scholar]
- Wang, Z. A Fully integrated W-band beamformer in 0.13 μm SiGe BiCMOS technology based on distributed true-time-delay architecture. In Proceedings of the IEEE International Nanoelectronics Conference (INEC), Chengdu, China, 9–11 May 2016. [Google Scholar]
- Perera, S.M.; Ariyarathna, V.; Udayanga, N.; Madanayake, A.; Wu, G.; Belostotski, L.; Wang, Y.; Mandal, S.; Cintra, R.J.; Rappaport, T.S. Wideband N-beam arrays using low-complexity algorithms and mixed-signal integrated circuits. IEEE J. Sel. Top. Signal Process. 2018, 12, 368–382. [Google Scholar] [CrossRef]
- Mailloux, R.J. Phased Array Antenna Handbook, 2nd ed.; Artech House: Norwood, MA, USA, 2005; ISBN 1-58053-689-1. [Google Scholar]
- Van Trees, H.L. Optimum Array Processing: Detection, Estimation, and Modulation Theory; Wiley: New York, NY, USA, 2002; ISBN 0-471-09390-4. [Google Scholar]
- Madanayake, A.; Ariyarathna, V.; Udayanga, N.; Belostotski, L.; Perera, S.K.; Cintra, R.J. Design of a low-complexity wideband analog true-time-delay 5 Beam array in 65 nm CMOS. In Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Boston, MA, USA, 6–9 August 2017. [Google Scholar]
- Schwartz, J.; Arnedo, I.; Laso, M.A.G.; Lopetegi, T.; Azana, J.; Plant, D. An electronic uwb continuously tunable time-delay system with nanosecond delays. IEEE Microw. Wirel. Compon. Lett. 2008, 18, 103–105. [Google Scholar] [CrossRef]
- Chu, T.; Roderick, J.; Hashemi, H. An integrated ultra-wideband timed array receiver in 0.13 μm cmos using a path-sharing true time delay architecture. IEEE J. Solid-State Circuits 2007, 42, 2834–2850. [Google Scholar] [CrossRef]
- Soer, M.; Klumperink, E.; Nauta, B.; van Vliet, F. A 1.5-to-5.0 GHz input-matched +2 dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65 nm CMOS. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 19–23 February 2012. [Google Scholar]
- Ghaffari, A.; Klumperink, E.; Soer, M.; Nauta, B. Tunable high-q n-path band-path filters: Modeling and verification. IEEE J. Solid-State Circuits 2011, 46, 998–1010. [Google Scholar] [CrossRef]
- Lien, Y.; Klumperink, E.; Tenbroek, B.; Strange, J.; Nauta, B. A high-linearity CMOS receiver achieving +44 dBm IIP3 and +13 dBm B1dB for SAW-Less LTE radio. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 5–9 February 2017. [Google Scholar]
- Li, W.; Wang, W.; Chen, Y. A 0.5–3 GHz true-time-delay phase shifter for multi-antenna systems. In Proceedings of the IEEE 2nd Advanced Information Technology, Electronic and Automation Control Conference (IAEAC), Chongqing, China, 25–26 March 2017. [Google Scholar]
- Elkind, J.; Goldberger, E.; Socher, E. 57–67 GHz highly compact bidirectional 3-bit phase shifter in 28 nm cmos. IEEE Microw. Wirel. Compon. Lett. 2018, 28, 1017–1019. [Google Scholar] [CrossRef]
- Zhang, Y.; Huang, F.; Li, T.; Tang, X.; Jiang, N. A 1 V 2.4–6 GHz 6 bit vector-sum phase shifter with very low rms phase error and gain error. Microw. Opt. Technol. Lett. 2018, 60, 2467–2471. [Google Scholar] [CrossRef]
- Garakoui, S.K.; Klumperink, E.; Nauta, B.; van Vliet, F. Compact cascadable gm-c all-pass true time delay cell with reduced delay variation over frequency. IEEE J. Solid-State Circuits 2015, 50, 693–703. [Google Scholar] [CrossRef]
- Mondal, I.; Krishnapura, N. A 2 GHz bandwidth, 0.25–1.7 ns true-time-delay element using a variable-order all-pass filter architecture in 0.13 μm cmos. IEEE J. Solid-State Circuits 2017, 52, 2180–2193. [Google Scholar] [CrossRef]
- Wijenayake, C.; Madanayake, A.; Belostotski, L.; Xu, Y.; Bruton, L. All-pass filter-based 2-D IIR filter-enhanced beamformers for AESA receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 2014, 61, 1331–1342. [Google Scholar] [CrossRef]
- Chen, Y.; Li, W. Campact and broadband variable true-time delay line with DLL-based delay-time control. Circuits Syst. Signal Process. 2018, 37, 1007–1027. [Google Scholar] [CrossRef]
- Ulusoy, A.; Schleicher, B.; Schumacher, H. A tunable differential all-pass filter for uwb true time delay and phase shift applications. IEEE Microw. Wirel. Compon. Lett. 2011, 21, 462–464. [Google Scholar] [CrossRef]
- Ahmadi, P.; Maundy, B.; Elwakil, A.S.; Belostotski, L.; Madanayake, A. A new 2nd-order all-pass filter in 130 nm cmos. IEEE Trans. Circuits Syst. II Express Br. 2016, 63, 249–253. [Google Scholar] [CrossRef]
- Wijenayake, C.; Xu, Y.; Madanayake, A.; Belostotski, L.; Bruton, L. RF analog beamforming fan filters using cmos all-pass time delay approximations. IEEE Trans. Circuits Syst. I Regul. Pap. 2012, 59, 1061–1073. [Google Scholar] [CrossRef]
- Ahmadi, P.; Taghavi, M.H.; Belostotski, L.; Madanayake, A. 6-GHz all-pass-filter-based delay-and-sum beamformer in 130 nm CMOS. In Proceedings of the IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), College Station, TX, USA, 3–6 August 2014. [Google Scholar]
- Maheshwari, S. Tuning approach for first-order filters and new current-mode circuit example. IET Circuits Devices Syst. 2018, 12, 478–485. [Google Scholar] [CrossRef]
- Bult, K.; Wallinga, H. A cmos analog continuous-time delay line with adaptive delay-time control. IEEE J. Solid-State Circuits 1988, 23, 759–766. [Google Scholar] [CrossRef]
- Ahmadi, P.; Belostotski, L.; Madanayake, A.; Haslett, J.W. 0.96-to-5.1 GHz 4-element spatially analog IIR-enhanced delay-and-sum beamformer. In Proceedings of the IEEE International Microwave Symposium (IMS), Honolulu, HI, USA, 4–9 June 2017. [Google Scholar]
- Chen, Y.; Li, W. An ultra-wideband pico-second true-time-delay circuit with differential tunable active inductor. Analog Integr. Circuits Signal Process. 2017, 91, 9–19. [Google Scholar] [CrossRef]
Reference | Technology | Mode | Order | Frequency (GHz) | Max. Delay (ps) | P1dB (dBm) | IIP3 (dBm) | Power (mW/V) |
---|---|---|---|---|---|---|---|---|
[15] | 140-nm CMOS | Voltage | 1st | 1–2.5 | 61 1 | N/A | N/A | 10 2/1.5 |
[19] | SiGe2RF HBT | Voltage | 2nd | 3–10 | 75 | −1 | N/A | 38.8/2.5 |
[20] | 130-nm CMOS | Voltage | 2nd | 6 | 55 | −5.5 | 2 | 18.5/1.5 |
[22] | 130-nm CMOS | Voltage | 1st | 9 | 49 3 | −2 | 8.5 | 20.4/1.5 |
[25] | 130-nm CMOS | Current | 1st | 0.3–5.1 | 82 | N/A | N/A | 6.15/1.5 |
[26] | 180-nm CMOS | Voltage | 2nd | 3–12 | 8.5 | 14.6 | 22.6 | 12/1.8 |
This work | 180-nm CMOS | Voltage | 1st | 5 | 59 4 | −1.9 | 16.6 | 10/1.8 |
© 2018 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
Share and Cite
Aghazadeh, S.R.; Martinez, H.; Saberkari, A. 5GHz CMOS All-Pass Filter-Based True Time Delay Cell. Electronics 2019, 8, 16. https://doi.org/10.3390/electronics8010016
Aghazadeh SR, Martinez H, Saberkari A. 5GHz CMOS All-Pass Filter-Based True Time Delay Cell. Electronics. 2019; 8(1):16. https://doi.org/10.3390/electronics8010016
Chicago/Turabian StyleAghazadeh, Seyed Rasoul, Herminio Martinez, and Alireza Saberkari. 2019. "5GHz CMOS All-Pass Filter-Based True Time Delay Cell" Electronics 8, no. 1: 16. https://doi.org/10.3390/electronics8010016
APA StyleAghazadeh, S. R., Martinez, H., & Saberkari, A. (2019). 5GHz CMOS All-Pass Filter-Based True Time Delay Cell. Electronics, 8(1), 16. https://doi.org/10.3390/electronics8010016