Abbaszadeh, A.; Iakymchuk, T.; Bataller-Mompeán, M.; Francés-Villora, J.V.; Rosado-Muñoz, A.
AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface. Electronics 2019, 8, 94.
https://doi.org/10.3390/electronics8010094
AMA Style
Abbaszadeh A, Iakymchuk T, Bataller-Mompeán M, Francés-Villora JV, Rosado-Muñoz A.
AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface. Electronics. 2019; 8(1):94.
https://doi.org/10.3390/electronics8010094
Chicago/Turabian Style
Abbaszadeh, Asgar, Taras Iakymchuk, Manuel Bataller-Mompeán, Jose V. Francés-Villora, and Alfredo Rosado-Muñoz.
2019. "AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface" Electronics 8, no. 1: 94.
https://doi.org/10.3390/electronics8010094
APA Style
Abbaszadeh, A., Iakymchuk, T., Bataller-Mompeán, M., Francés-Villora, J. V., & Rosado-Muñoz, A.
(2019). AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface. Electronics, 8(1), 94.
https://doi.org/10.3390/electronics8010094