A New Low-Voltage Low-Power Dual-Mode VCII-Based SIMO Universal Filter

Abstract

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 μm CMOS technology parameters at a supply voltage of ±0.9 V are provided to support the presented theory.

1. Introduction

Filters are among the most widely used circuits in different areas such as instrumentation, communication, control, and signal processing systems [1,2,3,4,5]. Traditionally, filters were designed in voltage mode using active devices such as operational amplifiers (Op-Amp). However, due to the reduced supply voltage in advanced CMOS technologies and the ever-increasing demand on low-power circuits, the design of high-performance Op-Amp-based filters has become very difficult. The inherent low-voltage nature of current-mode signal processing has motivated a wide investigation on current-mode filters with the aim of achieving better results under low supply voltage restrictions. Among the various types of current-mode filters, the multifunction or universal type which is able to produce several transfer functions simultaneously with the same circuit, is good solution for the ever-increasing demand of the market for low-power circuits. That is why, in recent years, numerous current-mode universal filters have appeared in literature [6,7,8,9,10,11,12].

In the universal filter category, second-order (biquadratic) filters play an important role in the field of analog signal processing such as the implementation of phase-locked loop (PLL), frequency modulation (FM), stereo demodulation, etc. [1,2,3,4,5]. They can be classified in single-input-multiple-output (SIMO), multiple-input-single-output (MISO), and multiple-input-multiple-output (MIMO) topologies. A deep investigation in the literature reveals that various current-mode active building blocks such as four-terminal floating nullor (FTFN) [6], differential voltage current conveyor (DVCC) [7], current-controlled current conveyor transconductance amplifier (CCCCTA) [7], current feedback operational amplifier (CFOA) [9], current differencing buffered amplifier (CDBA) [10,11], modified current-controlled current differencing transconductance amplifier (MCCCDTA) [12], operational transconductance amplifier (OTA) [13] LT1228 IC [14], fully differential second-generation current conveyor [15], current follower cascaded transconductance amplifier (CFCTA) [16], and voltage differencing differential difference amplifier [17] have been used in the design of multifunction filters. The common feature of the multifunction filters of [6,7,8,12] is that their output signal is in the form of a current. The reason is that the used current-mode active building blocks lack a low-impedance voltage output port. Therefore, for applications requiring voltage outputs, these circuits require additional voltage buffers resulting in higher power consumption and chip area. There are a few current-mode building blocks such as CDBA, CFOA, and FTFN that have low-impedance voltage output ports. However, the voltage output multifunction filters based on these active building blocks reported in [6,9,10,11] suffer from serious drawbacks, the most serious of them being their inability to provide low impedance at all voltage output ports and the consequent requirement of additional voltage buffers. For example, the voltage output multifunction FTFN-based filter of [6] requires an extra voltage buffer at its LP output. Similarly, the multifunction CFOA-based filter of [9] requires an extra voltage buffer for HP output. Although the CDBA-based multifunction filter of [9] provides low impedance for all voltage outputs, it has the load and other passive elements connected to output ports, so the output ports must be designed to have high current drive capability. These will result in a complicated internal circuit for the used CDBA. The filter circuits of [14,15,16,17,18] suffer from a high supply voltage requirement.

Recently a new active building block called the second-generation voltage conveyor (VCII) has attracted the attention of researchers [19,20]. It is the dual of well-known second-generation current conveyor (CCII) and, compared to other active building blocks, enjoys a simple internal structure and features more design flexibility. It is characterized by a low-impedance current input port, a high-impedance current output port and a low-impedance voltage output port. Using the low-impedance current input port, current summing/subtracting operations can be performed very easily. In addition, having a low-impedance voltage output port makes this building block highly suitable for voltage output applications. In other words, the low-impedance voltage output port makes the extra voltage buffer unnecessary. More interestingly, VCII internal structure is composed of a current buffer and a voltage buffer. This simple implementation results in low power consumption and low chip area.

Despite these attractive features, up to now, VCII is not used in the implementation of universal filters. Therefore, in this paper, we take the advantages offered by the VCII block to design a voltage output low-power second-order universal filter. The presented filter topology employs one inverting current buffer (I-CB), three double output VCIIs, five resistors, and three capacitors. I-CB is simply a current buffer with gain of −1. The proposed universal filter is designed in SIMO topology and provides all-pass (AP), band-pass (BP), band-stop (BS), low pass (LP), and high-pass (HP) functions. All the outputs are available in voltage form at the low-impedance voltage output ports of the VCII. Interestingly, the HP, BP, and BS outputs are also available in current form at the high-impedance port of the VCII. Moreover, the AP and BS outputs are provided in both the inverting and non-inverting types. The proposed circuit is in dual mode and, based on the application, the input signal can be either a current or a voltage.

The organization of this paper is as follows. In Section 2 the VCII block and its implementation are presented. In Section 3, the proposed filter topology is given. In Section 4, the non-ideal analysis is performed. The simulation results and a comparative table are presented in Section 5. Finally, Section 6 concludes the paper.

2. The VCII Internal Circuit Design

Figure 1a,b shows the schematic diagram and the symbolic representation of a dual-output VCII, respectively. It has a low-impedance current input Y port. Ideally, the impedance at the Y terminal is zero. The current applied to the Y port is transferred to the X₁ and X₂ ports with a current gain of A_I1 and A_I2, respectively. In the ideal case, the values of A_I1 and A_I2 are unity. X₁ and X₂ are high-impedance (ideally ∞) current output ports. The voltage produced at the X₁ and X₂ ports is conveyed to the Z₁ and Z₂ ports, respectively. The voltage gain between X₁–Z₁ and X₂–Z₂ is shown by A_V1 and A_V2, respectively, which are equal to unity in the ideal case. The Z₁ and Z₂ ports are low-impedance (ideally zero) voltage output ports. The relation between the port currents and voltages is:

$$v_Y=r_Y{i}_Y,i_{X1}=A_{I1}{i}_Y,i_{X2}=A_{I2}{i}_Y,V_{Z1}=A_{V1}{V}_{X1},V_{Z2}=A_{V2}{V}_{X1}.$$

(1)

As seen from Figure 1, a dual-output VCII is composed of a dual-output current buffer and two voltage buffers. Figure 2 shows the CMOS circuit implementation of the dual-output VCII, representing the dual-output version of the VCII circuit reported in [19]. The current buffers are composed by M₁–M₉, M₁₃ transistors together with current sources I_B1–I_B3, I_B5. The input current to the Y terminal is transferred to the X₁ terminal with a current gain of about −1 by an inverting current buffer (I-CB) made of M₁–M₉ transistors and I_B1–I_B3 current sources. The non-inverting current buffer made of M₁–M₆, M₁₃ and current sources I_B1–I_B2, I_B4 conveys the input current of the Y terminal to the X₂ terminal with a current gain of about +1. The voltage buffers are simply two flipped voltage followers (FVFs) [21] formed by M₁₀–M₁₁, M₁₄–M₁₅ transistors and current sources I_B4, I_B6. The used FVFs provide very low impedance at the Z terminals. The negative-feedback loop established by M₁–M₅ provides very low impedance at the Y terminal. The main feature of the proposed circuit is very low impedance at the Y terminal, which makes this node ideal for a current summing operation. In addition, very low impedance at the Y terminal ensures negligible voltage drop at this node.

3. The Proposed Universal Filter

The proposed VCII-based filter topology is shown in Figure 3. It is based on three dual-output VCIIs and one I-CB as active building blocks and three resistors and three capacitors as passive elements. There is only one floating capacitor. The input signal can be either current or voltage type. Input current is applied to the circuit directly as shown in Figure 3a, while, due to the very low impedance at the Y terminal which is ideally zero, voltage signals can only be applied through a resistor as shown in Figure 3b. The circuit is designed in single-input three-output topology and produces second-order HP, LP, and BP outputs simultaneously. The outputs are available as voltage signals at the low-impedance Z ports of VCII. The HP output can also be provided in the form of current at the high-impedance X₂ port of the VCII. The AP and BS outputs can be simply produced using an additional VCII block and three resistors as shown in Figure 4 in which, as it will be shown, V_in1, V_in2, and V_in3 are connected to HP, LP, and BP outputs, respectively. The transfer functions of Figure 3a and b are similar except that, for Figure 3b, the input signal should be replaced with V_in/R_in. For this similarity, in the following analysis, the transfer functions are only derived for the topology of Figure 3a.

Due to the very low impedance at the Y port of the VCII, which is ideally zero, we can assume this port at ground. Therefore, applying Kirchoff’s Current Law (KCL) analysis at node 2, gives I₃ as:

$$I_3=\frac{s{C}_1{R}_1}{1+s{C}_1{R}_1}{I}_2.$$

(2)

Using Equation (1), the relationship between I₁–I₂ and I₃–I₄ can be expressed as:

$$I_1\approx I_2; I_3\approx I_4$$

(3)

By assuming the Y port of VCII₂ at ground and performing a KCL analysis at node 3, I₅ is obtained as:

$$I_5=\frac{1}{1+s{C}_2{R}_2}{I}_4.$$

(4)

At the input node (node 1) we have:

$$i_{in}=I_1+I_5.$$

(5)

Using Equations (3) and (5), I₂ is found as:

$$I_2=\frac{\left(1+s{C}_1{R}_1\right)\left(1+s{C}_2{R}_2\right)}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(6)

For V_X1 (the voltage at node 3) we have:

$$V_{X1}=\frac{R_2}{1+s{C}_2{R}_2}{I}_4.$$

(7)

From Equations (2), (3), and (6), I₄ is obtained as:

$$I_4=\frac{s{C}_1{R}_1\left(1+s{C}_2{R}_2\right)}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(8)

Inserting Equation (8) into Equation (7), gives V_X1 as:

$$V_{X1}=V_{Z1}=V_{BP}=\frac{s{C}_1{R}_1{R}_2}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(9)

Equation (9) represents a second-order BP response. Due to the voltage buffer action between X₁ and Z₁ terminals, the BP response is available at the Z₁ port as a voltage signal.

From Equations (4) and (8), I₅ is found as:

$$I_5=\frac{s{C}_1{R}_1}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(10)

By subtracting I₄ (Equation (8)) from I₅ (Equation (10)) the HP output can be provided:

$$I_{HP}=I_5-I_4=-\frac{s^2{C}_1{R}_1{C}_2{R}_2}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(11)

As in Figure 3a, by connecting the current output X₂ ports of VCII₁ and VCII₃, a HP output in the form of current is produced at node 4. The HP output is also available in the form of voltage at Z₂ ports of VCII₁ and VCII₃ as:

$$V_{HP}=R_3{I}_{HP}=-\frac{s^2{C}_1{R}_1{C}_2{R}_2{R}_3}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(12)

Using Equation (10), the voltage at X₂ and Z₂ ports of VCII₃ have a LP transfer function as:

$$V_{X2}\approx V_{Z2}=-\frac{I_5}{s{C}_3}=V_{LP}=-\frac{\frac{C_1{R}_1}{C_3}}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{i}_{in}.$$

(13)

By assuming the Y terminal of VCII₄ at ground, the Io₁ and Io₂ outputs are achived as:

$$\left|I_{o1}|=|I_{o2}\right|=\frac{V_{in1}}{R_4}+\frac{V_{in2}}{R_5}+\frac{V_{in3}}{R_6}.$$

(14)

For the AP output, V_in1, V_in2, and V_in3 are connected to V_HP, V_BP, and V_LP outputs, respectively. Therefore, by inserting V_HP (Equation (12)), V_BP (Equation (9)), and V_LP (Equation (13)) into Equation (14), the AP transfer function is achieved as:

$$I_{AP}=I_{o1}=I_{o2}=-\frac{\frac{s^2{C}_1{R}_1{C}_2{R}_2{R}_3}{R_4}-\frac{s{C}_1{R}_1{R}_2}{R_5}+\frac{C_1{R}_1}{C_3{R}_6}}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{I}_{in}.$$

(15)

For the BS output, V_in2 is connected to ground while V_in1 and V_in3 are connected to V_HP and V_LP outputs respectively giving:

$$I_{BS}=I_{o1}=I_{o2}=-\frac{\frac{s^2{C}_1{R}_1{C}_2{R}_2{R}_3}{R_4}+\frac{C_1{R}_1}{C_3{R}_6}}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(2C_1{R}_1+C_2{R}_2\right)+1}{I}_{in}.$$

(16)

Therefore, the tAP and BS outputs are produced as current signals at the X₁ and X₂ terminals of VCII₄. In addition, as shown in Figure 4, both AP and BS outputs are available as voltage signals at the Z₁ and Z₂ terminals of VCII₄ in inverting and non-inverting forms, respectively.

From Equation (9) the quality factor Q and natural frequency ω₀ are determined using the following formulas:

$${\omega }_0=\sqrt{\frac{1}{C_1{C}_2{R}_1{R}_2}}.$$

(17)

$$Q=\frac{\sqrt{C_1{C}_2{R}_1{R}_2}}{2C_1{R}_1+C_2{R}_2}.$$

(18)

By assuming R₁ = R₂ = R and C₁ = C₂ = C in Equations (17) and (18), we have:

$${\omega }_0=\frac{1}{RC}.$$

(19)

$$Q=\frac{1}{3}.$$

(20)

Therefore, ω₀ can be set by R and C independent of Q.

The sensitivities of the proposed filter are calculated using the well-known definition of sensitivity in Equation (15) [22] as:

$$S_x^F=\frac{x}{F}\frac{\partial F}{\partial x}.$$

(21)

$$S_{R_1}^{{\omega }_0}=S_{R_2}^{{\omega }_0}=S_{C_1}^{{\omega }_0}=S_{C_2}^{{\omega }_0}=-\frac{1}{2}.$$

(22)

$$S_{C_1}^Q=S_{R_1}^Q=\left[\frac{1}{2}-\frac{2R_1{C}_1}{\left(2C_1{R}_1+C_2{R}_2\right)}\right].$$

(23)

$$S_{C_2}^Q=S_{R_2}^Q=\left[\frac{1}{2}-\frac{R_2{C}_2}{\left(2C_1{R}_1+C_2{R}_2\right)}\right].$$

(24)

For C₁ = C₂ = C, R₁ = R₂ = R, from Equations (23) and (24), we have:

$$S_{C_1}^Q=S_{R_1}^Q=\left[\frac{1}{2}-\frac{2}{3}\right]=-\frac{1}{6}.$$

(25)

$$S_{C_2}^Q=S_{R_2}^Q=\left[\frac{1}{2}-\frac{1}{3}\right]=\frac{1}{6}.$$

(26)

As seen from Equations (22), (25), and (26), the proposed filter exhibits reduced sensitivities to passive parameters.

4. Non-Ideal Analysis

The non-ideal analysis of the proposed universal filter can be performed by considering the non-ideal current and voltage gains of the used VCIIs. Using Equation (1), we have:

$$I_2=A_{IB}{I}_1; I_4=A_{I1}{I}_3$$

(27)

where A_IB and A_I1 are the gain of the current buffer and the current gain of VCII₁ at its X₁ terminal, respectively.

At the input node (node 1) we have:

$$i_{in}=I_1+A{\prime }_{I2}{I}_5,$$

(28)

where A’_I2 is the current gain of VCII₂ at its X₂ terminal.

Using Equations (27) and (28) and Equations (2) and (4), I₂ is found as:

$$I_2=\frac{A_{IB}\left(1+s{C}_1{R}_1\right)\left(1+s{C}_2{R}_2\right)}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(29)

From Equations (27) and (29), I₅ is obtained as:

$$I_5=\frac{A_{IB}{A}_{I1}s{C}_1{R}_1}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(30)

V_LP can be expressed as:

$$V_{LP}=V_{Z23}=A{{}^{″}}_{V2}{V}_{X23}=-A{{}^{″}}_{I2}A{{}^{″}}_{V2}\frac{1}{s{C}_3}{I}_5,$$

(31)

where V_Z23 and V_X23 are the voltages at the Z₂ and X₂ terminals of VCII₃, respectively. A”_V2 is the voltage gain at the Z₂ terminal of VCII₃. Inserting Equation (30) into Equation (31), V_LP is found as:

$$V_{LP}=-\frac{A{{}^{″}}_{I2}A{{}^{″}}_{V2}{A}_{IB}{A}_{I1}\raisebox{1ex}{$C_1{R}_1$}\!\left/ \!\raisebox{-1ex}{$C_3$}\right.}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(32)

From Equations (2) and (28), I₄ is found as:

$$I_4=\frac{A_{IB}{A}_{I1}s{C}_1{R}_1\left(1+s{C}_2{R}_2\right)}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(33)

Inserting Equations (30) and (33) into Equation (11) gives I_HP as:

$$I_{HP}=\frac{-A_{IB}{A}_{I1}{s}^2{C}_1{R}_1{C}_2{R}_2}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(34)

From Equation (34), V_HP1 and V_HP2 are found as:

$$V_{HP1}=\frac{-A_{IB}{A}_{I1}{A}_{V2}{s}^2{C}_1{R}_1{C}_2{R}_2{R}_3}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(35)

$$V_{HP2}=\frac{-A_{IB}{A}_{I1}A{{}^{″}}_{V2}{s}^2{C}_1{R}_1{C}_2{R}_2{R}_3}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in}.$$

(36)

Using Equations (33), (7), and (1), V_BP is found as:

$$V_{BP}=\frac{A_{IB}{A}_{I1}{A}_{V1}s{C}_1{R}_1}{s^2{C}_1{C}_2{R}_1{R}_2+s\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)+1}{i}_{in},$$

(37)

where A_v1 is the voltage gain at the X₁ terminal of VCII₁. From Equation (37), the quality factor Q and the natural frequency ω₀ are determined using the following formulas:

$${\omega }_0=\sqrt{\frac{1}{C_1{C}_2{R}_1{R}_2}}.$$

(38)

$$Q=\frac{\sqrt{C_1{C}_2{R}_1{R}_2}}{\left(C_1{R}_1\left\{1+{A^{\prime }}_{I2}{A}_{I1}{A}_{IB}\right\}+C_2{R}_2\right)}.$$

(39)

As seen from Equations (38) and (39), ω₀ is not affected by the non-ideal gains of VCIIs. In addition, as current and voltage gains of VCIIs are designed to be very close to unity, their effect on Q is also negligible. The relations for AP and BS outputs can be simply achieved by inserting Equation (32) and Equations (35)–(37) into Equation (14).

5. Simulation Results and Comparative Analysis

The proposed multifunction filter of Figure 3 has been simulated with PSpice and using 0.18 μm CMOS parameters under a supply voltage of ±0.9 V. The circuit of Figure 2 is used as a VCII. For I-CB, the current buffer section of Figure 2, consisting of transistors M₁–M₉ and current sources I_B1–I_B3, is used. The chosen transistor aspect ratios are shown in

Table 1. Transistor aspect ratios.

M1–M2	18/0.36	M8–M9	9/0.9
M3–M4	18/0.9	M13	18/0.9
M5	9/0.36	M10, M15	9/0.36
M6–M7	18/0.9	M11, M14	0.9/0.36

. The values of bias currents are I_B1 = 50 µA, I_B2 = I_B3 = I_B4 = I_B5 = I_B6 = 20 µA. The values of the passive components are: R₁ = R₂ = 10 KΩ, C₁ = C₂ = 10 pF. The values of R₃ and R_L are 5 KΩ.

Figure 5a shows the frequency performances of the BP, HP, and LP outputs. The value of ω₀ and Q is measured as 1.55 MHz and 0.33, respectively. From Equations (17) and (18), the values of ω₀ and Q are calculated as 1.6 MHz and 0.33, respectively. As seen, there is a good agreement between theory and simulation results. The transient response of the different outputs is evaluated by applying a sinusoidal input current with a peak-to-peak value of 10 μA and frequency of 1.5 MHz. The total harmonic distortion (THD) values are 3.7%, 2.6%, and 3.6%, for HP, BP, and LP outputs, respectively.

Figure 5b shows the BS output, which is achieved by setting R₄ = 12.5 KΩ, R₅ = 78 kΩ, and R₆ = 5 KΩ and connecting V_in1 = V_HP, V_in2 = 0 and V_in3 = V_LP. Figure 5c shows the gain and phase response of the AP output, which is achieved by connecting V_in1 = V_HP, V_in2 = V_BP and V_in3 = V_LP and using the same values for R₄–R₆.

The tunability of the proposed filter is investigated by varying the center frequency ω₀, through C₁ and C₂. As shown in Figure 6, ω₀ varies from 1 to 32 MHz for different values of capacitors without affecting Q.

The transient response of the different outputs is evaluated by applying a sinusoidal input current with a peak-to-peak value of 10 μA and a frequency of 1.5 MHz. The THD values are 2%, 1%, 6%, 1.4%, and 2% for the HP, BP, LP, AP, and BS outputs, respectively.

To investigate the circuit performance against transistor parameter tolerances, the circuit is simulated by applying 3% and 5% tolerance in V_TH and β (with usual meaning of symbols) of transistors. The result is shown in

Table 2. Filter parameters vs. transistor parameters variation.

Variation in VTH and β of Transistors	ω0	Q
3%	1.68 MHz	0.32
5%	1.7 MHz	0.328

, which acknowledges the negligible effect of tolerances in the circuit performance. The input impedance of the proposed filter is only 47 Ω and the output impedances for voltage outputs and current outputs are 93 Ω and 254 KΩ, respectively. The power consumption is also 1.47 µW.

A comparison between the proposed universal filter and some other previously reported works is drawn in

Table 3. Comparison between the proposed multifunction filter and other works.

		# of Floating Capacitors	Used Active Building Block	Vss-Vdd (V)	Pd (mW)	Outputs	Configuration	I–O Signals	ω0	Extra Voltage Buffer
[6]	1	0	FTFN, OTA	NA	NA	LP, BP, BS	SIMO	V–V	7.95 KHz	Yes
	2	2	FTFN, OTA	NA	NA	LP, HP	SIMO	I–I	7.95 KHz	-
[7]		0	DVCC	±0.9	0.462	BP, BS, HP	MIMO	I–I	3.18 MHz	-*
[8]		0	CCCCTA	±1.85	NA	LP, BP, HP	SIMO	I–I	1.5 MHz	-
[9]	1	0	CFOA	NA	NA	LP, BP, HP	SIMO	I–I	<1 MHz	Current buffer required at output
	2	0	CFOA	NA	NA	LP, BP	SIMO	V–V	<1 MHz	Yes
[10]		0	CDBA	±1.25	NA	LP, BP, HP	SIMO	I–V	10 MHz	No
[11]		2	CDBA	±5	NA	AP, LP, BP	SIMO	I–V	1 MHz	No
[12]		0	MCCCDTA	±3	NA	LP, BP, HP, BS, AP	MISO	I–I	1.27 MHz	-
[14]		2	LT1228	±5	NA	LP, BP, HP, BS, AP	MISO	V–V	159.19 KHz	No
[15]		2	FDCCII	±1.65	NA	LP, BP, HP, BS, AP	MISO	V–V	1 MHz	No
[16]		2	CFCTA	±5	NA	LP, BP, HP, BS, AP	MISO	V–V	2.8 MHz	Yes
[17]		2	I-CB VDDDA	±1.25	NA	LP, BP, HP, BS, AP	MISO	V–V	1.074 MHz	Yes
This Work		1	I-CB, VCII±	±0.9	1.47	HP, BP, LP I-AP, NI-AP, I-BS, NI-BP	SIMO	I/V–V/I	1–32 MHz	No

LP: Low pass; BP: Band pass; BS: Band stop; HP: High pass; AP: All pass, I: Inverting, NI: Non-inverting; SIMO: Single-input multiple-output; MIMO: Multiple-input multiple-output; MISO: Multiple-input single-output; FTFN: Four-terminal floating nullor; OTA: Operational transconductance amplifier; DVCC: Differential voltage current conveyor; CCCCTA: Current-controlled current conveyor transconductance amplifier; CFOA: Current feedback operational amplifier; CDBA: Current differencing buffered amplifier; MCCCDTA: Modified current-controlled current differencing transconductance amplifier; CFCTA: Current follower cascaded transconductance amplifier; I-CB: Inverting current buffer; VCII: Second-generation voltage conveyor. * The circuit suffers from high input impedances and three current buffers are required at inputs.

. As seen, the proposed circuit is the only one providing both inverting and non-inverting type AP and BS outputs in current and voltage forms. The proposed circuit is also the only one that can produce all possible outputs as current and voltage signals in low-impedance and high-impedance terminals, respectively. It also enjoys low-voltage operation. Although the circuit proposed in [7] does not employ floating capacitors, it requires three extra current buffers at the input. In addition, compared to the previously published universal filters of [6,11,14,15,16,17], which employ two floating capacitors, there is only one floating capacitor in the proposed circuit. Compared to [9,16,17], the proposed circuit does not require extra current and/or voltage buffers at the input and output terminals.

6. Conclusions

In this paper a new VCII-based multifunction filter was presented. It was demonstrated that, taking advantage from one current buffer and four second-generation voltage conveyors (VCII) as active building blocks, it can perform BP, HP, LP AP, and BS filtering actions simultaneously maintaining a very low circuit complexity as well as a low static power consumption. It was shown that, the versatility of the VCII block allows us to produce outputs in forms of both current and voltage signals. Filter functionality was also acknowledged through simulations, which showed a good agreement with the presented theory. The robustness of the circuit against fabrication mismatches was analyzed and a final comparison between the presented work and the available literature was given.