Optimization Considerations for Short Channel Poly-Si 1T-DRAM

Round 1

Reviewer 1 Report

The proposed paper detailing some optimization consideration that should be taken for designing 1T-DRAM looks interesting itself since this work outcome could help for large scale design of DRAM. However, I have few remarks:

1. Careful reediting of the abstract is advised to help readers to better understand your work and valorize the outcome of your work.
2. Figure 1 showing cross section of the simulated structure is not clear. Clearly show all details for both structure with clear dimension. The figure show that drain, source, poly-S body and substrate thickness are different. In the figure caption clearly state that the parameter is poly-Si thickness.
3. Comparing your simulation results such hold time, transistor size, body thickness drain voltage to other work from literature is also recommended.
4. Line 191 to 193 are unclear. Please clearly state which performance is better, T_body20nm or T_body60nm and why?
5. Professional English proof reading is advised to improve the writing style and fix typos errors.

Author Response

Comment 1: Careful reediting of the abstract is advised to help readers to better understand your work and valorize the outcome of your work.

Our response: Thank you for this suggestion. We modified the abstract (page 1, lines 11-17) to make it more comprehensive.

Comment 2: Figure 1 showing cross section of the simulated structure is not clear. Clearly show all details for both structure with clear dimension. The figure show that drain, source, poly-Si body and substrate thickness are different. In the figure caption clearly state that the parameter is poly-Si thickness.

Our response: Figure 1 shows the cross-sections of the two simulated devices. Both devices have the same 100 nm buried oxide thickness and 800 nm substrate thickness. The devices differ only in their body thickness. We added the substrate thickness of the simulated devices in Table 1 to clarify their dimensions, indicated the body thickness in Figure 1, and modified the figure’s caption to clearly explain the parameter difference between the two devices. Also, we added explanation about the cross section of the simulated devices (in page 2, line 61-62)

Comment 3: Comparing your simulation results such hold time, transistor size, body thickness drain voltage to other work from literature is also recommended.

Our response: Research on Poly-Si 1T-DRAM is in its early stages, and according to other published work, simulation results vary widely with hold time, transistor size, body thickness, and drain voltage. We investigated 5 papers to compare the results with other papers. In these papers, sensing margins defined by the current difference between the "1" and "0" states at a 10ns hold time in a poly-Si 1T-DRAM cells are less than 10uA. Also, when the retention time is defined as the hold time when the difference between two currents is 3uA, the retention time of these papers varies from 0 seconds to approximately 3 msec. (Retention time of 0 means that sensing margin is less than 3uA.) References to other studies about poly-Si 1T-DRAM cells are as follows.

Reference:

1. Jang, W.-D. et al Polycrystalline silicon metal-oxide-semiconductor field-effect transistor-basedstacked multi-layer one-transistor dynamic random-access memory with double-gate structure for the embedded systems The Japan Society of Applied Physics 2020, 59. Japanese Journal of Applied Physics 59. https://doi.org/10.7567/1347-4065/ab65d2
2. Yoon, Y.-J. et al A polycrystalline-silicon dual-gate MOSFET-based 1T-DRAM using grain boundary-induced variable resistance Applied Physics Letters 2019, https://doi.org/10.1063/1.5090934
3. Seo, J.-H. et al Fabrication and Characterization of a Thin-Body Poly-Si 1T DRAM With Charge-Trap Effect IEEE Electron Device Letters 2019, 40. https://doi.org/1109/LED.2019.2901003
4. Kim, H.-J.; Yoo, S.-Y; Kang, I.-M.; Cho, S.-J.; Sun, W.-K.; Shin, H.-S. Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM. Micromachines 2020, 2, 228; https://doi.org/10.3390/mi11020228.
5. Kim, H.-J.; Kang, I.-M.; Cho, S.-J.; Sun, W.-K.; Shin, H.-S. Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode. Semiconductor Science and Technology 2019, 34, 105007. https://doiorg/10.1088/1361-6641/ab3a07.

 

Comment 4: Line 191 to 193 are unclear. Please clearly state which performance is better, Tbody20nm or Tbody60nm and why?

Our response: The sensing margin and retention time of Tbody60nm are larger than those of Tbody20nm because Tbody60nm has a hole trapping effect in both its Read”1” and Read”0” states regardless of the Write”1” drain voltage. The hole trapping effect in the Read”1” state increases the “1” current, and in the Read”0” state, the hole trapping effect sustains a long memory cycle. We have revised the explanation (page 8, line 194-196) more clearly according to your helpful advice.

Comment 5: Professional English proof reading is advised to improve the writing style and fix typos errors.

Our response: We appreciate your suggestion; we had a professional editor make a second pass to address this issue.

Author Response File: Author Response.pdf

Reviewer 2 Report

This submission is series paper that published from elsewhere by the same authors. This paper tackles the scaling difficulty of conventional 1T-1C DRAM. However, the simulation adapted significantly outdated design parameters. 

1) The gate length of 70 nm is more than 10 years old technology in DRAM, where the density is of very important concern. For example, current mass produced DRAM used 17 nm.

2) In timing parameters, the DRAM can only find application for writing timing less than 25 ~ 35 nsec unless otherwise it won't be compatible with host. However, this paper uses 500 nsec for programming. 

3) The authors should address how to justify only one vertical grain boundary in the center of the film. The authors introduced that the grain boundary will be introduced by annealing amorphous silicon. Then, the reviewer naturally suspect that the grain boundary will very randomly formed.  

4) That being said, the variability due to random grain boundary formation should be much more important topic. In fact, the similar operation has been studied and published elsewhere by the authors.

5) It is shown that Vd=0.1V can be used for write '1'. This fact adversely implies that the device suffers significantly from wordline disturb. It has to be clarified how to assure the write disturb inhibition. 

6) As the wordline voltages for write '0' and write '1' are different, the proposed device must suffer from two step refresh; refresh data '1' followed by data '0' or vice versa. This is huge disadvantage of low power and high speed applications. This fact needs to be disclosed.

7) For reproduction by peer readers, the trap concentration and trap energy level assigned for the grain boundary were disclosed. The authors are encouraged how to justify those values ? Any references or in-depth explanation is necessary.

8) For array use, a simulation for the memory cell under unselected row (BL disturbed conditions) must be included.

 

Author Response

Comment 1: The gate length of 70 nm is more than 10 years old technology in DRAM, where the density is of very important concern. For example, current mass produced DRAM used 17 nm.

Our response: Thank you for raising this concern. 1T-1C DRAM has a severe disadvantage because it requires capacitor fabrication. Several studies have shown that capacitorless 1T-DRAM can operate as a memory cell even though it has no capacitor. In particular, poly-Si 1T-DRAM has the advantage of greatly improving the density because it is stackable in a 3D structure. Poly-Si 1T-DRAM is in the early stages of research and its physical operating mechanisms are the subject of current studies. This paper confirms these properties and proposes operating conditions and device structures that optimize operating performance. In addition, since the transistor size of the poly-Si device is determined by the poly-Si deposition process, it is necessary to study this process along with functional investigations. We intend to study short-channel devices having less than a 30nm gate length in future work that considers both processes and operating mechanisms.

Comment 2: In timing parameters, the DRAM can only find application for writing timing less than 25 ~ 35 nsec unless otherwise it won't be compatible with host. However, this paper uses 500 nsec for programming.

Our response: Writing time in poly-Si 1T-DRAM depends on its transistor size or gate structure. As the transistor size decreases, the drain on current increases, so memory operation is possible with even a short writing time. Besides, recent studies have shown that poly-Si 1T-DRAM devices with a double gate or FinFET structure can have reduced writing time. For this manuscript, a single gate SOI cell was simulated to propose a general optimization method, but we expect that writing time can be reduced by changing the gate structure and reducing the transistor size. Here are some recent studies:

References:

1. Yoon, Y.-J. et al Capacitorless one-transistor dynamic random-access memory based on double-gate GaAs junctionless transistor Japanese Journal of Applied Physics 2017, 56. https://doi.org/10.7567/JJAP.56.06GF01
2. Yoon, Y.-J. et al Capacitorless one-transistor dynamic random-access memory based on asymmetric double-gate Ge/GaAs-heterojunction tunneling field-effect transistor with n-doped boosting layer and drainunderlap structure Japanese Journal of Applied Physics 2018, https://doi.org/10.7567/JJAP.57.04FG03
3. Han, J.-W. et al Hybrid 1T e-DRAM and e-NVM Realized in One 10 nm node Ferro FinFET device with Charge Trapping and Domain Switching Effects 2018 IEEE International Electron Devices Meeting (IEDM) 1-5 Dec. 2018, San Francisco, CA, USA. https://doi.org/1109/IEDM.2018.8614650

 

Comment 3: The authors should address how to justify only one vertical grain boundary in the center of the film. The authors introduced that the grain boundary will be introduced by annealing amorphous silicon. Then, the reviewer naturally suspect that the grain boundary will very randomly formed.

Comment 4: That being said, the variability due to random grain boundary formation should be much more important topic. In fact, the similar operation has been studied and published elsewhere by the authors.

Our response: Since comment 3 and comment 4 are similar, we will answer them together. As you said, GBs are distributed with a random number and location in the poly-Si body. In our previous studies, we found that the sensing margin of a poly-Si 1T-DRAM cell is affected by the number rather than the location of the GBs and that the sensing margin decreases in inverse proportion to the number of GBs. In this paper, since the devices simulated have a gate length as small as 70 nm, we assumed that there was only one GB in the channel. To simplify the simulation, this GB was located in the center of the channel based on the following recent research:

References:

1. Baek, M.-H.; Lee, S.-H.; Kwon, D.W.; Seo, J.Y.; Park, B.-G. Hole Trapping Phenomenon at the Grain Boundary of Thin Poly-Si Floating-Body MOSFET and Its Capacitor-Less DRAM Application Journal of Nanoscience and Nanotechnology 2017, 17, pp. 2906–2990. https://doi.org/info:doi/10.1166/jnn.2017.14027.
2. Kim, H.-J.; Kang, I.-M.; Cho, S.-J.; Sun, W.-K.; Shin, H.-S. Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode. Semiconductor Science and Technology 2019, 34, 105007. https://doi.org/10.1088/1361-6641/ab3a07.
3. Kim, H.-J.; Yoo, S.-Y; Kang, I.-M.; Cho, S.-J.; Sun, W.-K.; Shin, H.-S. Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM. Micromachines 2020, 2, 228; https://doi.org/10.3390/mi11020228.

 

Comment 5: It is shown that Vd=0.1V can be used for write '1'. This fact adversely implies that the device suffers significantly from wordline disturb. It has to be clarified how to assure the write disturb inhibition.

Comment 6: As the wordline voltages for write '0' and write '1' are different, the proposed device must suffer from two step refresh; refresh data '1' followed by data '0' or vice versa. This is huge disadvantage of low power and high speed applications. This fact needs to be disclosed.

Comment 8: For array use, a simulation for the memory cell under unselected row (BL disturbed conditions) must be included.

Our response: Since comment 5,6 and comment 8 are similar, we will answer together. These comments are about whether the poly-Si 1T-DRAM structure can operate as a memory device under array conditions. However, this study analyzed the physical operation mechanism of poly-Si 1T-DRAM in a one-cell unit to present a general optimization method as stated earlier. Expanding the device in array units does not fit the theme of this paper, and it is difficult to perform this task in 8 days because an HSPICE circuit simulator is required for array conditions. We intend to pursue operations in an array environment in subsequent studies. In addition, since different operating voltages for Write"1" and Write"0" present an intrinsic 1T-DRAM device problem, we believe the refresh issue is another research topic for this device. The following references show that in 1T-DRAM operation, the voltages for Write”1” and Write”0” are different.

1. S.; Nagoga.M; Sallese.J.M; Fazan.P. A SOI capacitor-less 1T-DRAM concept. 2001 IEEE International SOI Conference. Proceedings, Durango, USA, 1-4 Oct. 2001; pp. 153-154. https://doi.org/10.1109/SOIC.2001.958032.
2. S.; Nagoga.M; Sallese.J.M; Fazan.P. A capacitor-less 1T-DRAM cell. IEEE Electron Device Letters 2002, 23, pp 85-87. https://doi.org/ 10.1109/55.981314.
3. R.; Villaret.A.; Malinge.P.; Gasiot.G.; Mazoyer.P.; Roche.P.; et al. Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications. Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005, Kyoto, Japan, 14-16 June 2005; pp. 38-39. https://doi.org/ 10.1109/.2005.1469203.
4. Kim, H.-J.; Kang, I.-M.; Cho, S.-J.; Sun, W.-K.; Shin, H.-S. Analysis of operation characteristics of junctionless poly-Si 1T-DRAM in accumulation mode. Semiconductor Science and Technology 2019, 34, 105007. https://doi.org/10.1088/1361-6641/ab3a07.
5. Kim, H.-J.; Yoo, S.-Y; Kang, I.-M.; Cho, S.-J.; Sun, W.-K.; Shin, H.-S. Analysis of the Sensing Margin of Silicon and Poly-Si 1T-DRAM. Micromachines 2020, 2, 228; https://doi.org/10.3390/mi11020228.

 

Comment 7: For reproduction by peer readers, the trap concentration and trap energy level assigned for the grain boundary were disclosed. The authors are encouraged how to justify those values? Any references or in-depth explanation is necessary.

Our response: In the tail of the conduction band and valance band, trap densities have an exponential distribution, and near the mid-gap, they have a Gaussian distribution. The trap concentration and trap energy level were chosen based on recent research. We have added an explanation of the trap concentration and energy band used in our simulation (page 3, lines 87-88) to implement your suggestion.

Author Response File: Author Response.pdf

Reviewer 3 Report

The manuscript entitled “Optimization considerations for short channel poly-Si 1T-DRAM. I noted that the validation of the method presented in this manuscript is incomplete and not clear. Whilst the optimisation has been compared to other existing (published) works, I am unsure whether the analysis and the simulation methods chosen for comparison are capture complex physics of this device and thus the results may not have been put in the right context. I would suggest if the authors could describe the simulation methodology in sufficient detail.
Otherwise, the manuscript is interesting and publishable.

Author Response

Comment 1: I noted that the validation of the method presented in this manuscript is incomplete and not clear. Whilst the optimisation has been compared to other existing (published) works, I am unsure whether the analysis and the simulation methods chosen for comparison are capture complex physics of this device and thus the results may not have been put in the right context. I would suggest if the authors could describe the simulation methodology in sufficient detail.

Our response: Thank you for your helpful comments. Poly-Si parameters are used for our simulation and GB in poly-Si body represents poly-Si’s properties. Also, density of states in the GB which result in trapping charge effect was selected by referring to several papers. In addition, We performed transient simulation in order of “Hold-Write”0”-Hold-Read”0”-Hold-Write”1”-Hold-Read”1”. Before and after Write and Read operations, hold operation was performed to check how long the memory cell can hold the data state. We used band to band tunneling model in TCAD simulation tool to form excess hole in Write”1” operation.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

The authors reviewed the paper as suggested and answered my comments. The quality of the reviewed proposed paper has been improved compared to the first draft. I appreciate adding more literature references and valorizing your simulation outcome.

Reviewer 2 Report

The reviewer find that the response is inadequately addressed. Instead of revising and updating point-by-point comment, the authors have chosen the way to smudging out. The reviewer failed to find any improvement through this review round and reluctantly recommend the reject. 

Reviewer 3 Report

The corrections are satisfactory. The revised manuscript is publishable.