Quenching Circuit and SPAD Integrated in CMOS 65 nm with 7.8 ps FWHM Single Photon Timing Resolution

Abstract

This paper presents a new quenching circuit (QC) and single photon avalanche diode (SPAD) implemented in TSMC CMOS 65 nm technology. The QC was optimized for single photon timing resolution (SPTR) with a view to an implementation in a 3D digital SiPM. The presented QC has a timing jitter of 4 ps full width at half maximum (FWHM) and the SPAD and QC has a 7.8 ps FWHM SPTR. The QC adjustable threshold allows timing resolution optimization as well as SPAD excess voltage and rise time characterization. The adjustable threshold, hold-off and recharge are essential to optimize the performances of each SPAD. This paper also provides a better understanding of the different contributions to the SPTR. A study of the contribution of the SPAD excess voltage variation combined to the QC time propagation delay variation is presented. The proposed SPAD and QC eliminates the SPAD excess voltage contribution to the SPTR for excess voltage higher than 1 V due to its fixed time propagation delay.

1. Introduction

Single photon avalanche diodes (SPAD) are solid-state detectors used for applications requiring high timing resolution and single photon sensitivity, including positron emission tomography (PET) [1,2,3,4,5], fluorescence lifetime imaging microscopy (FLIM) [6,7], Raman spectroscopy [8,9], optical communication [10,11] and 3D ranging [12,13,14]. In clinical PET, time-of-flight (ToF) improves the positron–electron annihilation localization along the line of response resulting in a better contrast to noise ratio in the reconstructed image [15]. However, to improve significantly the contrast in the image of preclinical PET scanners, one must achieve tens of ps full width at half maximum (FWHM) of coincidence timing resolution (CTR) [16,17].

To achieve such high timing resolution, both the scintillator and the photodetector must be improved. The current scintillators used in PET (lutetium oxyorthosilicate (LSO) type crystals) are limiting the timing resolution to the order of 100 ps [16]. Using different mechanisms such as hot intraband luminescence [18] or quantum confinement in nano-scintillators [19,20], it is possible to increase the number of prompt photons to improve significantly the timing resolution. This paper focus on the development of the photodetector and its associated electronics to be used with these scintillators. On the photodetector side, the single photon timing resolution (SPTR) must be improved to the order of tens of ps FWHM to reach a CTR of tens of ps FWHM with the fast scintillators [20].

The SPTR is the timing jitter of the whole detector, including its readout electronic, when triggered by a single photon. While applications such as rangefinders minimize this jitter by averaging multiple measurements, ToF-PET and time imaging calorimeter require optimized SPTR for single event time arrival detection. Furthermore, in low-light detection applications such as Cherenkov radiators or Cherenkov PET detectors [21,22,23], the SPTR is critical since very few photons are emitted, hence detected.

One of the main challenges for SPAD-based detectors is combining both high photodetection efficiency (PDE) and high SPTR. At this level, commercially available SiPMs offer high fill factor and PDE but suffer from a limited SPTR coming from their parallel and distributed architecture for two reasons: (1) since all SPADs are connected in parallel, the detector has a high output capacitance which directly affects the rising edge slope (lower ${\displaystyle \frac{dV}{dt}}$) [24,25] of the output signal; and (2) each SPAD has a timing skew coming from the SPAD-to-output distance mismatch [25,26].

Unlike in an analog SiPM, SPADs in a digital SiPM designed on a 2D ASIC (application specific integrated circuit) are readout individually by a quenching circuit (QC), eliminating the effect of the high output capacitance at the cost of a lower fill factor. Similarly to an analog SiPM, a digital SiPM has routing skew between each QC and the time-to-digital converter (TDC) usually located in the ASIC periphery [1,27,28]. These contributions constrain the SPTR of such detectors to hundreds of ps FWHM [1,24,25,26,27,28,29].

We propose to use a 3D digital SiPM as a solution to all aforementioned problems (Figure 1) [30,31,32,33]. In this approach, different silicon tiers dedicated to specific functions are stacked and routed using vertical interconnections. For example (Figure 1), a top layer could include a SPAD array designed in an optoelectronic technology with through silicon vias (TSV) to interconnect to the second tier, which could be implemented in a deep submicron technology node to optimize both timing measurements and data processing. To optimize the timing performance, a QC and a TDC integrated per pixel provides means to characterize and correct the SPAD-to-SPAD skew. Since the pixel size is in the order of 50 × 50 µm² range and performance under 10 ps is mandatory for some of the aforementioned applications, every individual contribution in timing and size must be optimized. The TDC developed to be integrated in the pixel has a timing jitter of 6.9 ps rms [33] and the first results of a 2D pixel in CMOS 65 nm has a 17.5 ps FWHM SPTR [34].

To obtain a SPAD array with a 10 ps SPTR, the first step is to achieve a single SPAD and quenching circuit that can reach a SPTR of 10 ps. Many developments have been made to improve quenching circuits regarding the low area and the timing precision [35,36,37,38,39,40]. Furthermore, developments have been made on SPAD to optimize the SPTR such as a shallow trench isolation (STI) architecture to reduce the diffusion tail of the SPAD to reach a SPTR of 27 ps FWHM for a 14 µm SPAD [41]. In other development, an edge covering was added to the SPAD and it lowered their SPTR from 40 to 20 ps FWHM with a 20 µm SPAD [26]. On the quenching circuit side, an external timing pick-off circuit with a low threshold was developed and obtain similar SPTR characteristics with a different SPAD diameter: 32 ps FWHM for 20 µm SPAD, 34 ps FWHM for 50 µm SPAD and 35 ps FWHM for a 100 µm SPAD [42]. An SPTR of 20 ps FWHM was measured with a single SPAD of 50 µm at cryogenic temperature [43]. Still, there is not a SPAD and QC architecture that reached a SPTR of 10 ps for a single SPAD.

This paper presents a fully integrated QC designed in TSMC CMOS 65 nm for high timing precision with low jitter and an optimized architecture for low time propagation delay variation. The objective is to reach a 10 ps FWHM SPTR at the SPAD and QC level. This paper also provides a better understanding of the SPAD excess voltage variation impact on the SPTR. The implemented QC occupies 30 × 18 µm² and uses an integrated fast comparator with an adjustable threshold to optimize the timing jitter of the photodetector. Section 2 presents the architecture and the design considerations, Section 3 presents the materials and methods and Section 4 contains the results obtained with the 2D version of the detector. Section 5 presents the discussions and Section 6 provides the conclusions.

2. Architecture

2.1. Quenching Circuit

The proposed QC is a passive quenching with an active recharge and can be divided into four sections: the recharge transistor, the quench transistor, the comparator and two monostable circuits for the programmable hold-off and recharge time (Figure 2). The transistors routed to the SPAD are 3.3 V transistors, hence setting the SPAD excess voltage limit. The recharge transistor was designed to provide 1 mA for sub-ns recharge for the full input capacitive load (SPAD, TSV and the TSV contact). The quenching path is composed of two transistors in series: a cascode 3.3 V transistor that limits the current and a second transistor switches off the branch when a hit is detected and hold it off during the hold-off time.

The QC was designed to obtain high single photon timing resolution. To this end, an open-loop operational amplifier (Op-Amp) was used as a fast comparator with the advantage that the trigger following the crossing does not suffer from the time walk of a typical comparator with hysteresis. That said, the circuit is still immune to noise and undesired triggering as the SPAD is in a hold-off following the detection of an event. The Op-Amp was designed to obtain both low time propagation delay variation and low jitter as a function of input signal variations [44]. The Op-Amp is used as a leading edge discriminator. For a non-optimized discriminator, a variation in the input signal amplitude will impact the time propagation delay of the discriminator. This variation, if not compensated or minimized, will add up to the jitter of the detector. To this end, the Op-Amp was designed to minimize the time propagation delay variation caused by the undervoltage and overvoltage variation in regards to the Op-Amp threshold. This will minimize the jitter caused by the amplitude signal build-up at the SPAD and QC interface. The Op-Amp threshold is adjustable from an external control from a few mV up to 2.5 V to select the optimal voltage threshold in the rising signal from the SPAD readout by the QC. The Op-Amp has a size of 13 × 8 µm².

Figure 3 shows the two stage Op-Amp used as a comparator. Since the QC must sustain 3.3 V, the transistors used in the differential input pairs (M2-M3) and the current source (M1) are 3.3 V transistors. M4-M13 are standard 1 V transistors to match the subsequent electronics supply. Consequently, the Op-Amp simultaneously acts as both a discriminator and a level down shifter from 3.3 V to 1 V. The input pair is PMOS based to optimize the timing performance of the Op-Amp when the threshold is close to 0 V. M13 acts as a switch to turn off the QC by forcing the Op-Amp output at a high level resulting in a hold-off state of the QC. M12 is a cascode transistor to limit noise injection to the differential input pair from the subsequent circuits, in this case, a TDC.

The last section of the quenching circuit is monostable circuits required for both the programmable hold-off and recharge time. The hold-off defines the time a SPAD is intentionally turned off to minimize afterpulsing coming from trapped charges in the SPAD. The hold-off thus limits the correlated avalanche rate. The TDC also gives a feedback to maintain the QC in hold-off during its conversion time. Since the QC must address different SPAD designs in size/technologies where the threshold must be tailored to, the recharge time is also programmable. An adjustable recharge time can help minimize the undesired dead time while assuring a long enough recharge time to fully recharge the SPAD. The QC has a total size of 30 × 18 µm² including the top contact for the TSV connection of the 3D digital SiPM architecture to be developed.

2.2. Single Photon Avalanche Diode

Figure 4 shows a cross section of the 32 sided polygon SPAD made in CMOS 65 nm. The SPAD is a standard $p^{+}$ implantation (anode) in an n-well (cathode) with a p-well guard ring. A polysilicon layer (gate) was used as blockages for shallow trench isolation (STI) to minimize its effect on the guard ring and on the dark count noise (DCR) [41]. The SPAD active area is 20 µm. The SPAD has a standard architecture and is expected to have low photodetection efficiency (PDE) and high DCR, but its low capacitance and low area make it suitable for high timing precision measurements.

3. Materials and Methods

For test purposes, the ASIC is wirebonded on a dedicated daughterboard and powered using a motherboard, both custom designed (Figure 5). The motherboard contains an FGPA with the aim to communicate and configure the ASIC. The daughterboard is designed to fit on an optical test setup, giving the flexibility to connect different ASIC on the same motherboard. The proper supply circuits and event generator circuits used for timing measurements are on the daughterboard.

3.1. Quenching Circuit Characteristics

The quenching circuit characteristics such as the dead time, the hold-off time, the recharge time and the power consumption must be measured. The QC output pulse width is the sum of the hold-off time and the recharge time. By measuring its width, it is possible to determine the QC dead time and thus the maximum count rate of the QC.

A second output was added to the QC to determine the hold-off and recharge time. The second output signal is the recharge pulse only. By measuring the recharge pulse width, one can determine the recharge time and also the hold-off time by subtracting the recharge pulse width from the QC pulse width.

The power consumption depends on the count rate and on the Op-Amp bias current source that has an impact on the timing jitter. Three measurements were made at 25 µA, 50 µA and 100 µA current sources with count rate of 1 kcps and 1 Mcps. The measurements presented in the subsequent section were performed with a current source of 50 µA unless otherwise specified.

3.2. Quenching Circuit Electronic Timing Jitter

The QC timing jitter measurements use a fast input buffer on the daughterboard designed to minimize the jitter due to the signal rise time. The input signal is buffered using a LTC6957 to minimize the effect of its rise time (400 ps over 1 V) on the timing jitter of the QC. The signals were measured with an Agilent MSO-X 90324A, with 80 GSPS, 13 GHz vertical bandwidth and differential probes. Three different measurements were made using the setup shown in Figure 6. First, the timing jitter of the test setup (input buffer, output buffer and the oscilloscope) was measured using probe 1 and probe 3. Second, the timing jitter of the quenching circuit and the input/output buffer was measured using probe 1 and probe 2. From these two measurements, the quenching circuit contribution can be obtained. The timing jitter is measured with a threshold sweep from 1 mV to 700 mV for 1 V input steps and from 1 mV to 2500 mV for 3.3 V input steps. Third, the time propagation delay of the quenching circuit is measured to determine its variation as a function of overvoltage (0 V to 2 V) and threshold level (100 mV to 1 V) using probe 1 and probe 2.

3.3. Single Photon Timing Resolution

During the SPAD and QC SPTR measurements, the SPAD is illuminated by a Spectra Physics Mai Tai 80 MHz Ti:Sapphire pulsed laser (Figure 7). The pulse width is specified to be <100 s, which means that the laser contribution to the jitter is negligible. The test setup contribution including the laser, reference diode, oscilloscope and probe is measured at 3 ps FWHM. An optical parametric oscillator can tune the wavelength from 345 nm to 2500 nm (410 nm was used for the measurements). The light is attenuated with neutral density filters to ensure the measurements are made in a photon starved environment. The beam intensity is measured using an 818-UV Newport diode and a 1918-R Newport power meter to evaluate the number of photons hitting the SPAD. The laser has been attenuated so that the average number of photons per pulse reaching the SPAD avalanche region is lower than 0.04. The timing jitter measurements are acquired with a Teledyne Lecroy SDA 6000A oscilloscope, with 20 GSPS, 6 GHz vertical bandwidth, an active probe and a Becker and Hickl PHD 400 fast diode as the reference timing detector. The light spot from the laser is defocused using the microscope lens so that the spot has a >5 mm diameter to ensure a good illumination uniformity over all the SPAD active region.The SPTR measurements are performed as a function of QC threshold (1 mV up to 1.6 V) and excess voltage (0.5 V to 1.75 V).

3.4. SPAD Characteristics

The SPAD is characterized using the methods presented in [30,45] with the test setup presented in Figure 7. The SPAD breakdown voltage was measured using IV curves. The DCR and afterpulsing are measured as a function of the SPAD excess voltage (0.5 V to 1.5 V) at a room temperature with a hold-off of 100 ns. The single SPAD photon detection efficiency (PDE) is measured at a SPAD excess voltage of 1.5 V and wavelength from 400 nm to 700 nm. For the PDE measurements, the light spot is focused within the center of the SPAD active area using the microscope lens (5 µm spot size ) (Figure 7). To make sure that the high DCR/dead time did not saturate the SPAD, a 10 ns hold-off was used to get a maximum count rate of 100 MHz with the SPAD. The DCR of <1 MHz represents a dead time of 1% compared to the maximum count rate.

3.5. SPAD Excess Voltage Variation

The SPAD excess voltage varies within a single SPAD and there are many possible factors. It is important to note that a variation of the SPAD breakdown voltage results in a SPAD excess voltage variation if the high voltage (HV) supply is fixed. There are two external factors that can have an impact on the measured excess voltage. A variation of the HV supply for a fix SPAD breakdown voltage will be seen as a variation of the excess voltage (the one use in this measurement has a sub mV variation). A temperature variation will vary the SPAD breakdown voltage and will result in a variation of the SPAD excess voltage to be quenched. The variation of the excess voltage can also be from SPAD internal contributions. These variations can be due to electric field variation within the SPAD active area, the position of the seed of the avalanche, the statistical build-up of the avalanche or a combination of them. Using the QC adjustable threshold, it is possible to measure the excess voltage that is quenched in order to stop the avalanche and see its variation between each avalanche. This measurement is done in two steps. First, the voltage comparator must be characterized to determine its discrimination threshold variation. Second, the adjustable threshold of the comparator is used to measure the variation of the quenched excess voltage applied to the QC.

An ideal comparator exactly discriminates if the input signal is below or over the threshold. In reality, the comparator slowly starts to discriminate the input signal as the amplitude approaches the threshold level. The setup presented in Figure 6 is used with step signals of varying amplitude and a fixed threshold to produce the discriminator S-curve, from which the discrimination range in mV around the threshold is extracted. More specifically, taking the derivative of the S-curve highlights this range and qualifies the discrimination noise. A sweep of ±50 mV around the threshold was used for this measurement.

Once the comparator has been characterized on a dedicated test circuit, the same measurement is done on a second test circuit where a SPAD is directly connected at the input of the QC. Since it is the SPAD excess voltage variation that must be characterized, instead of varying the input amplitude, the QC threshold is varied from ± 50 mV around the SPAD excess voltage. The resulting S-curve was differentiated to determine the variation of the excess voltage in FWHM.

3.6. Timing Jitter Due to the SPAD Excess Voltage Variation

This measurement combines the results of the time propagation delay of the QC and the SPAD excess voltage variation. The SPAD excess voltage variation is an input signal variation of the QC. This variation has an effect on the time propagation delay which impacts the SPTR. The SPAD excess voltage variation measurement is a histogram representing the different SPAD excess voltage applied to the QC. By transposing the value of time propagation delay of the QC associated to the SPAD excess voltage, the timing jitter contribution of these combined measurements is obtained.

4. Results

4.1. Quenching Circuit Characteristics

The QC programmable hold-off is measured and ranges from 2 ns up to 100 ns. The programmable recharge is measured and ranges from 2 ns up to 10 ns. The total dead time of the QC is the sum of both the programmable hold-off and recharge times, which ranges from 4 ns to 110 ns. This provides a maximum count rate of about 250 Mcps. The power consumption of the QC is 85 µW, 170 µW and 340 µW at a count rate of 1 kcps for the Op-Amp current source of 25 µA, 50 µA and 100 µA, respectively. At a rate of 1 Mcps, the power consumption of the QC is 115 µW, 200 µW and 370 µW.

4.2. Quenching Circuit Electronic Timing Jitter

The timing jitter of the setup is measured at 1.7 ps rms (∼4 ps FWHM). This represents the timing resolution lower boundary of the setup for a 1 V input signal.

Figure 8 presents the timing jitter of the QC in response to pulse generator stimuli. For the 1 V input amplitude, the timing jitter varies between 4 ps and 4.4 ps FWHM for a threshold lower than 0.5 V (Figure 9). For a threshold higher than 0.6 V, the timing jitter deteriorates due to the contribution of the input signal roll-off.

The timing jitter for the 3.3 V input step varies between 3 ps and 4 ps FWHM for a threshold between 5 mV and 2 V. At low threshold (sub 50 mV), the jitter slightly deteriorates due to a limitation in the Op-Amp. The lowest timing jitter corresponds to a 1.5 V threshold (1.3 ps rms or about 3 ps FWHM). The better balance of the Op-Amp’s underdrive and overdrive explains this result. The timing jitter increases around 2.5 V (comparator discrimination limit and input signal roll-off contribution).

Figure 10 shows the time propagation delay of the quenching circuit as a function of the overvoltage and of the threshold. The overvoltage corresponds to the input applied voltage minus the threshold. The time propagation delay reaches stability above 1 V of overvoltage for a fix threshold. The threshold must be stable in order to minimize its impact on the timing performance. One could define the slope of the flat region as a metric to highlight the timing impact of the time propagation delay. In the present case, the value is ~3 ps/100 mV for the overvoltage.

4.3. Single Photon Timing Resolution

Figure 11 shows the SPTR of the 20 µm SPAD and the QC. The measured timing jitter is 7.8 ps FWHM. This includes the test setup contribution measured at 3 ps FWHM (oscilloscope and probe). Hence, the corrected SPTR of the SPAD and QC is $\sqrt{\left({7.8}^2-3^2\right)}$ = ~7 ps FWHM considering that the contributions are not correlated. The second peak at 65 ps is a reflection in the optical setup.

Figure 12 presents the effect of the QC threshold on the timing jitter of the detector for multiple excess voltages applied to the SPAD. The timing jitter is better at high excess voltage. Using low threshold minimizes the jitter, especially at low excess voltage.

Figure 13 shows the relationship between the SPTR and the Op-Amp power consumption. A minimum of 100 µW static power consumption is required to obtain sub-10 ps SPTR. Higher power consumption does not improve the SPTR further.

4.4. SPAD Characteristics

The SPAD characteristics are summarized in

Table 1. SPAD characteristics summary.

Characteristics	This Work	[46]	[47]	[48]	[49]	[41]	[50]
Technology	65	65	90	150	160	180	350
VBD/VEX (V)	9.9/1.5	9/0.4	14.9/2.4	19/5	26/3–9	11/0.8	25/6
SPAD diameter (µm)	20	8	6.4	10	10–80	14	20
DCR (cps/µm2)	2.8 k	15.6 k	3.1	1	0.13–0.19	4 k	1.2
Afterpulsing (%)	<10	<1	<1	<13	<1.26	N/A	<1
@ Hold-off	(0.1 µs)	(5 µs)	(15 ns)	(50 ns)	(50 ns)		(40 ns)
Peak PDE (%)	8	5.5	44	32	71	N/A	48
SPTR (ps FWHM)	7.8	235	51	42	28	27	80

. The SPAD breakdown voltage is 9.9 V. The single SPAD PDE is between 2% and 8% in the wavelength range of 400 nm to 700 nm with a peak at 470 nm. The SPAD architecture (shallow $p^{+}$ n-well junction) as well as the multiple intermetal dielectric layers over the SPAD may explain the low PDE. These characteristics lead to low light absorption into the thin high-field region of the SPAD.

4.5. SPAD Excess Voltage Variation

Figure 14 shows the discrimination S-curve of the QC using a step signal as input. The slope is steep and the peak of the variation of the discrimination is about 15 mV. Figure 15 shows that the variation is about 3 mV FWHM at different amplitude level. This shows that the QC has a precision of 3 mV and that it can be used to evaluate the SPAD excess voltage variation of tens of mV.

The same measurements are performed using a SPAD as the input instead of the step signal (Figure 16). The discrimination variation increases from 3 mV to 30 mV. We infer this change to be from the SPAD excess voltage variation and is about 30 mV FWHM.

4.6. Timing Jitter Due to the SPAD Excess Voltage Variation

The 30 mV SPAD excess voltage variation from Figure 16 may be transposed into timing jitter thanks to the time propagation delay data from Figure 10. Figure 17 compares the SPAD excess voltage variation jitter contribution with the measured SPTR. At low excess voltage (<300 mV), the QC contribution (jitter from the time propagation delay) dominates the measured SPTR (>20 ps FWHM). From 300 mV to about 700 mV, the timing jitter of the QC associated with the variation of the input signal lowers from 20 ps to 7 ps FWHM. At higher excess voltage (>0.7 V), the time propagation delay variation is small, representing a 3 ps FWHM contribution to the single photon timing resolution.

This timing jitter study provides an important insight about the single SPAD SPTR: the SPAD excess voltage variation is not limiting the global SPTR if the time propagation delay of the QC is low (~3 ps/100 mV in this QC).

5. Discussion

The QC proposed in this paper is designed to be integrated in a 3D digital SiPM for which three major properties must be optimized: power consumption, size and timing performance.

The QC power consumption has two contributions, the static power consumption of the Op-Amp and the dynamic consumption of the QC. As presented in Figure 13, to obtain a SPTR below 10 ps, a static power consumption of 85 µW is required in the Op-Amp. For application requiring a limited number of pixels or a small detector area (<5 × 5 mm²), the power consumption may not be an issue. However, for applications such as a PET scanner with large area of detectors, a 85 µW static power consumption per pixel in a 3D digital SiPM is still high. Since the projected SPAD size is 50 µm and the LabPET II rabbit scanner has about 50,000 1.1 × 1.1 mm² pixels, there will be 24.2 millions QC in the scanner [51]. The total power consumption of all the QC would be approximately 2.05 kW, 4 times higher than the estimated power consumption of 520 W of the current front-end electronics of the LabPET II rabbit scanner [52]. The static power consumption could be reduced or eliminated by choosing another discriminator architecture. However, this may come at the expense of the SPTR. Further optimization of the Op-Amp to reduce its static power consumption is mandatory for system integration.

Since the objective is to integrate the QC and a TDC within the 50 × 50 µm² pixel of the 3D digital SiPM, the QC size is of high importance. The proposed QC has a size of 30 × 18 µm² including a contact area for the TSV. With this architecture, the size could easily be reduced to 15 × 18 µm² while keeping the sub-10 ps SPTR capability if designed for a 2D device. The present version’s size is larger since it includes the TSV landing site (where no noise sensitive circuit may be placed) and some extra feature to find the best operating point (variable threshold, hold-off, etc.). Reducing the size for a 3D integrated detector would require architecture modifications of the discriminator and, as for the power consumption, may come at the expense of the SPTR. A size of 30 × 18 µm² represents less than 25 % of the total size of the 3D digital SiPM pixel, which seems acceptable.

The main objective of this detector is to obtain a SPTR below 10 ps FWHM. The timing jitter of the QC alone, i.e., without the SPAD, was optimized and is extremely low. Indeed, since its value is of the same order than the test setup contribution (∼4 ps FWHM), we believe that the timing jitter is dominated by either the output buffer or the measurement setup. The timing jitter of the QC alone is significantly lower than 4 ps FWHM. Knowing that the QC will drive an individual TDC in the 3D digital SiPM instead of the full test setup, its contribution to the SPTR should be lower than 4 ps FWHM. According to Table 1, the developed SPAD has an excellent SPTR (7.8 ps). Furthermore, the present SPAD design exhibits overall better results if compared to a previous SPAD design made in the same technology node [46]. In a 3D digital SiPM, a bigger capacitance is expected between the SPAD and the Op-Amp. With an adjustable threshold, the Op-Amp should provide a suitable solution to select the optimal point in the risetime of the signal to optimize the SPTR.

As for the SPAD developed, it suffers from a low PDE (8%) and from a high DCR (900 kcps) compared to other CMOS SPAD made in higher technology node [50]. These characteristics are not suitable for applications such as PET scanners, which require a high fill factor and high PDE to detect the low level of scintillation light. However, application such as rangefinding would benefit from a 2D detector made in CMOS 65 nm since correlated measurements are less affected by high DCR and lower PDE can be compensated with higher photon flux. Furthermore, on-chip post-processing can easily be added in a CMOS technology to improve the timing performance.

This work also aims to better understand the different contribution to the SPTR from the combination of the SPAD and the QC. The measured SPTR of the QC with an integrated SPAD is 7.8 ps FWHM (Figure 11). The jitter measurement with a step signal demonstrated that the QC jitter is extremely low, i.e., similar to test setup jitter of 4 ps FWHM (Figure 8). This timing jitter study provides an important insight about the single SPAD SPTR: the combination of the SPAD excess voltage variation and the time propagation delay variation must be low enough to be a negligible contribution to the SPAD SPTR. In the case of the QC developed, it does not limit the SPTR for a SPAD with an excess voltage variation of 30 mV FWHM or lower if sufficient excess voltage is applied (Figure 17). Consequently, the main contribution of the 7.8 ps must come from the SPAD itself (avalanche multiplication statistics) or from the QC input signal shape (e.g., parasitic capacitance) that affects the QC timing jitter. Considering that a proper design can be achieved on the SPAD layer, the 3D process connecting the SPAD to the QC is critical since the SPTR could be limited by the parasitic capacitance at the QC input node. Further studies with varying capacitance at the input of the QC could help determine the main contribution between the two aforementioned.

6. Conclusions

This paper presents a new QC integrated in TSMC CMOS 65 nm technology. The QC was designed with view to be integrated in a 3D digital SiPM and is optimized for fast timing, low area and low power consumption. The extremely low timing jitters measured for the QC alone (<4 ps) and for the QC with an integrated SPAD (7.8 ps) establish that fast timing electronics for single shot timing measurements in a 3D digital SiPM is achievable. To optimize the QC for timing, it is important to use a comparator that will not be affected by the amplitude variation at its input. Since the SPTR is not affected by the variation in this SPAD and QC, the Op-Amp proposed is well adapted to eliminate a contribution to the SPTR from a SPAD excess voltage variation of 30 mV or lower like in the SPAD presented in this paper. The QC’s adjustable threshold feature allows timing resolution optimization as well as SPAD excess voltage characterization. The QC has a total size of 30 × 18 µm² including a contact for a TSV connection in the 3D digital SiPM architecture. The power consumption of the QC is 130 µW at a count rate of 1 Mcps. The adjustable threshold, and hold-off and recharge times are essential since the SPAD and QC interconnection in the 3D digital SiPM is under development. The next step for this project is to study the mm-scale uniformity of the quenching circuit characteristics in an array. This includes the timing jitter and the time delay propagation variation to ensure that the QC developed will not affect the timing precision of a SPAD array, either from timing jitter or timing skew.