Analysis of Oxide Capacitance Changes Based on the Formation–Annihilation of Conductive Filaments in a SiO₂/Si-NCs/SiO₂ Stack Layer-Based MIS-like Capacitor

Abstract

This work reports on the correlation between resistive switching (RS) with capacitance switching (CS) states observed in SiO₂/Si-nanocrystals (Si-NCs)/SiO₂ stack layers using a metal-insulating semiconductor (MIS)-like device. The formation of Si-NCs, which act as conductive nodes, of about 6.7 nm in size was confirmed using a transmission electron microscope. These devices exhibit bipolar RS properties with an intermediate resistive state (IRS), which is a self-compliance behavior related to the presence of the Si-NCs layer. The current value changes from 40 nA to 550 µA, indicating RS from a high resistance state (HRS) to a low resistance state (LRS) with the IRS at 100 µA. The accumulation (C_A) and inversion capacitance (C_I) also change when these RS events occur. The C_A switches from 2.52 nF to 3 nF with an intermediate CS of 2.7 nF for the HRS, LRS, and IRS, respectively. The C_I also switches from 0.23 nF to 0.6 nF for the HRS and LRS, respectively. These devices show an ON/OFF current ratio of 10⁴ with retention times of 10⁴ s. Furthermore, both C_A and C_I states remained stable for more than 10³ s. These findings highlight the potential of these devices for applications in information storage through memristor and memcapacitor technologies.

1. Introduction

Recently, non-volatile memories (NVMs) have gained considerable attention because of the instability created by the considerable increase in elements at smaller dimensions, as described by Moore’s law [1,2,3]. Therefore, some alternatives to storage devices for storing high-density information have emerged. NVMs, especially resistance random access memories (ReRAMS), have gained considerable interest in recent years due to their low power consumption, low cost, and high operating speed. An alternative to this kind of NVM are memristive devices. The term memristor was theoretically coined by Prof. Chua in 1961 and, since its invention in 2008 by HP Labs, has become a promising candidate due to the resistive switching (RS) phenomenon which consists of a reversible change between low and high resistance states (LRS and HRS, respectively), with it being capable of retaining its resistance over time [4,5]. In addition, the mem-term has also been extended to memcapacitive and meminductive devices, with new alternatives being developed for information storage [6]. Several studies have described the simultaneous behavior of RS and capacitive switching (CS) [7,8,9,10,11,12,13,14], with them reporting the important role of conductive filaments (CFs) within dielectric matrices in the electrical properties of the devices. For instance, S. X. Wu et al. [9] reported heterostructures based on Pt/LaAlO₃/Nb:SrTiO₃, where the formation of a CF contributes to the presence of both resistive and capacitive switching behavior. Minji Park et al. [12] studied graphene sheets embedded in an organic polymer with remarkable results in multilevel nonvolatile memcapacitive and memristive behavior. Minju Kim et al. [13] demonstrated nonvolatile and reversible capacitance changes in a floating-gate MOS capacitor with Ag/CeO_x/Pt/HfO_x/n-Si. They improved the performance of the serial capacitor of Ag/CeO_x/Pt and Pt/HfO_x/n-Si compared to that of a single capacitor of Pt/HfO_x/n-Si, caused by CF formation through the Ag/CeO_x/Pt stack. These characteristics are relevant for memory applications because they substantially improve the information storage capacity of the devices.

The use of active layers such as solutions, polymers, or more complex structures makes their implementation difficult in conventional silicon-based electronic device fabrication processes. One of the materials commonly used in Si-technology that exhibits intrinsic RS properties is silicon oxide (SiO_x, x < 2) due to the formation–annihilation of CFs created by the interconnection of silicon nanocrystals (Si-NCs) [15,16]. An alternative for the development of RS devices is the use of SiO₂/Si-NCs multilayer (ML) structures in which the separation and size of the Si-NCs are controlled by the thickness of the SiO₂ and Si layers, respectively. In our previous studies, we have shown that unipolar RS can be obtained in Si-NCs/SiO₂ multilayers (MLs) where the SET and RESET voltages decrease as the number of Si-NCs/SiO₂ layers decreases [15]. Bipolar RS (BRS) behavior has also been demonstrated for devices with eight Si-NCs/SiO₂ bilayers, whereby the mechanism responsible for the charge transport in the different resistive states was analyzed [16]. However, it has also been shown that the different resistive states can be obtained by changing the stop voltage. In these devices, Si-NCs act as conductive nodes that allow for the formation of the CFs. However, the capacitive behavior in these structures has not been explored yet.

Based on these previous studies, an improvement in RS properties can be achieved by reducing the number of layers and adjusting the thickness of the SiO₂ layer embedded in the Si-NCs. Therefore, in this work, we report MIS-like devices consisting of stacked ML systems based on SiO₂/Si-NCs/SiO₂ as the I-layer and indium tin oxide (ITO) as the top M-electrode. These devices exhibit a stable relationship between memristive and memcapacitive behavior. Current vs. voltage (I-V) and capacitance vs. voltage (C-V) measurements show that these structures behave with five capacitive states related to three resistance states due to the formation–annihilation of CFs, which at the same time promote changes in the stoichiometry of the SiO_x matrix. Long retention times and stability are obtained for the different resistive and capacitive states, demonstrating promising characteristics.

2. Materials and Methods

The fabrication process involved the deposition of three successive layers of SiO₂ (~3 nm), Si (~6 nm), and SiO₂ (~10 nm) on a p-type Si (100) substrate with a resistivity of 1–5 Ω cm using an RF magnetron sputtering system. Deposition was carried out with 2-inch Si (99.99% purity) and SiO₂ (99.99% purity) targets and with RF power settings of 70 W and 100 W, respectively. Prior to deposition, the Si substrates were thoroughly cleaned using acetone, ethanol, and deionized water in an ultrasonic bath. To remove the native oxide, the Si substrates were immersed in 10% aqueous hydrofluoric acid solution (HF) for 2 min. For the deposition process, the temperature and rotation of the Si substrates were maintained at a constant value of 500 °C and 20 rpm, respectively. After deposition, SiO₂/Si/SiO₂ ML was thermally annealed at 1100 °C for 2 h in N₂ atmosphere to induce the formation of Si-NCs in the Si-layer. A 700 nm-thick aluminum layer was deposited on the backside of the Si-substrate through evaporation and then thermally annealed in forming gas to obtain ohmic contact. Then, an ITO of 100 nm thickness was deposited on the upper SiO₂ (10 nm) layer using a magnetron sputtering system at 270 °C with a rotation speed of 20 rpm. A photolithography process was employed to fabricate square-shaped patterns with an area of 1 mm². A three-dimensional schematic structure of the device is shown in Figure 1a. Transmission electron microscopy (TEM) was used to determine the thickness of the ML structure and the formation of Si-NCs after the thermal annealing process wherein their size is limited by the thickness of the Si layer [15,16,17,18]. A semiconductor parameter analyzer Keithley 4200-SCS was used to carry out the I-V and C-V curves. For both measurements, the bias was applied to the ITO top electrode and Al was grounded. C-V curves were performed from inversion (reverse bias, RB) to accumulation (forward bias, FB) at 100 kHz (sine wave with 30 mV of amplitude).

3. Results and Discussion

Figure 1b shows a TEM micrograph of the cross-sectional view of the device, in which the thickness of the entire SiO₂/Si-NCs/SiO₂ ML system is about 19.0 ± 1.0 nm. The presence of the Si-NCs embedded in the ML with a size of 6.7 ± 0.8 nm is also corroborated by an interplanar distance of ~3.2 Å, which corresponds to the [111] plane for silicon. Figure 2a shows the C-V behavior of a fresh (black line) device, that is, without any electrical stress. It can be observed that in RB, the device exhibits an inversion capacitance of about 0.33 nF at +2 V. As the voltage becomes negative (FB), the capacitance increases, and it reaches a maximum value of 2.92 nF at −1 V and then it sharply decreases to 0.85 nF at −3 V in the accumulation region. This reduction in capacitance suggests a leaking of the charge accumulated at the SiO₂/Si-NCs/SiO₂/p-Si substrate interface, which could indicate the existence of some pristine conductive paths in the ML. Therefore, I-V measurements were performed to understand the C-V behavior, as shown in Figure 2b. The voltage sweep was applied at FB (0 V → −13 V) with a current compliance (CC) of 20 mA. An exponential increase in current is observed for low voltages until it reaches the CC at about −6 V, indicating that the device is in a low resistance state (LRS) due to the presence of CFs created by defects in the material (including the Si-NCs).

X-ray photoelectron spectroscopy (XPS) analysis showed that Si diffusion from the Si layer toward the SiO₂ layers occurs in this kind of SiO₂/Si ML, producing an ML with SiO_x (x < 2) layers with gradual Si excess [15,16]. Also, this diffusion coefficient is higher in the films that are only a few nanometers thick, such as in this case. Moreover, since this ML was subjected to a thermal annealing process, it is expected that we will see the formation of Si-NCs embedded in the Si layer capped by SiO_x layers, as shown in Figure 1b. It is known that SiO_x films are typically unstable, whereby some Si-O bonds can be broken when a voltage is applied, leading to the formation of Si dangling bonds (unbound Si atoms) and Si-Si bonds. Si-Si bonds along with Si-NCs are responsible for the formation of the CFs in the dielectric matrix, resulting in a change in resistance state. Nevertheless, CFs are initially present in the devices from this work, resulting in high carrier conduction (LRS), as observed during the first I-V measurement. The high silicon concentration in the SiO_x films suppresses oxygen coordination defects and consecutively influences the development of Si defects neighboring the Si-NCs, which can form CFs that enhance the charge flow in the device at low voltages. Moreover, as observed in the TEM image, the thickness of SiO_x films is lower than 10 nm, enhancing the charge carriers injection through the ML.

As observed in Figure 2b, when the voltage reaches −11 V, the current drops by about one order of magnitude, indicating the breaking-off of the CFs, switching the devices from the LRS to the HRS (RESET process). A new I-V measurement from −13 V → 0 V shows that the device remains in the HRS. After the RS changes from the LRS to the HRS, a second C-V measurement (red line) is performed, as shown in Figure 2a. This measurement exhibits the expected capacitor behavior, maintaining both inversion and accumulation regions. At RB (+2 V), the inversion capacitance is about 0.46 nF, while at FB (−3 V), the accumulation capacitance is about 3 nF, which will be referred to as the high capacitance state at the inversion region (HCS_I) and HCS at the accumulation region (HCS_A), respectively.

Figure 3a shows the bipolar RS (BRS) behavior obtained in these devices. After the RS from the LRS to the HRS was obtained at FB, two complete measurement cycles were performed. During the first cycle (sweeps 1–4), the first measurement at RB (0 V → +11 V) shows that the device is in the HRS. As the voltage becomes higher, the current gradually increases until an intermediate resistive state (IRS) is observed at about +5 V; as the voltage increases, the devices finally switch to the LRS at about +9.5 V (SET process), which is maintained during the second measurement (+11 V → 0 V). These devices exhibit the IRS as a self-compliance behavior, and this is related to the presence of the Si-NC layer as a consequence of the single-electron trapping phenomenon (in Si-NCs) involving the Coulomb blocking effect. In fact, this behavior has been reported before whereby the number of Si-NC layers is related to the number of current steps [15]. With a subsequent measurement (third measurement) to negative voltages (0 V → −11 V), the device shows the opposite resistive change (LRS → HRS) or the RESET process at −7 V, which is maintained during the fourth measurement of −11→ 0 V.

A second measurement cycle (sweeps 5–8) was performed at a voltage range where the device starts to show staircase current (the IRS) to explore its effect on the capacitance behavior. During voltage sweep 5 at RB (0 → +6 V), the current shows one peak at about +1.5 V, which indicates possible competition between the formation–annihilation of the CF until the change in resistance state from the HRS → the IRS is obtained at +7 V. The IRS is maintained during voltage sweeps 6 (+6 V → 0 V) and 7 (0 V → −11 V) at RB and FB, respectively. When the voltage exceeds −6 V in sweep 7, a RESET process is observed, achieving a switch to the HRS which is maintained during voltage sweep 8. During the I-V measurements, new C-V curves were measured to observe the behavior of the ML-based devices after the SET, RESET, and IRS processes, as shown in Figure 3b.

Once the device is at SET (LRS), a low capacitance state at accumulation (LCS_A) and the inversion region (LCS_I) is observed, where the capacitance values are 2.52 and 0.23 nF at −3 V and +2 V, respectively. For RESET (HRS), the HCS_A and HCS_I values of about 3.0 and 0.6 nF are observed at −3 V and +2 V, respectively. For the IRS, an intermediate capacitance state at accumulation (ICS_A) value of 2.72 nF is obtained at −3 V. However, at inversion, the ICS_I is about 0.27 nF, which is close to LCS_I (0.23 nF) at +2 V. Although the HCS_A and HCS_I capacitive states are obtained by changing the polarity, it is clearly observed that the inversion capacitance changes (from HCS_I to LCS_I) if the RS occurs, as shown in Figure 3b at +2 V. Therefore, the device exhibits three resistive states (LRS, IRS, and HRS) with five capacitive states (HCS_A, ICS_A, and LCS_A in accumulation mode and HCS_I and LCS_I in inversion mode). The retention times of resistance and capacitance states were also measured, as shown in Figure 3c,d, respectively. Both the LRS and HRS remain unchanged for 10⁴ s (limit of the source) with current values of about 550 µA and 40 nA, respectively. This indicates an ON/OFF ratio of about 10⁴, which is higher than that reported for SiO₂-based devices [19,20,21,22,23]. As observed in Figure 3d, similar behavior for stability was observed in the HCS, ICS, and LCS values for both accumulation and inversion capacitance, of about >3 × 10³ s, demonstrating promising storage and stability characteristics.

To identify the charge transport mechanisms involved in the HRS and LRS, the I-V curves were analyzed. The most reported conduction mechanisms for RS-based devices include Schottky emission, Poole–Frenkel (P-F) emission, Fowler–Nordheim (F-N), trap-assisted tunneling (TAT), space charge limited conduction (SCLC), hopping conduction, and ohmic conduction [24,25,26,27,28,29]. Figure 4 shows the bi-logarithmic J-E curves and a schematic model during the SET (Figure 4a,b) and RESET (Figure 4c,d) processes. It is important to note that in situ TEM electrical measurements were not carried out, and micrographs (b) and (d) are only used to represent the CF formation/rupture. By analyzing the slopes of fitting lines, we can determine the specific current transport mechanisms in each resistive state. Figure 4a shows three linear fitting zones obtained in the HRS with different slopes corresponding to the SCLC conduction mechanism. The initial slope reflects a pronounced injection of charge, resulting in the complete filling of traps (I ∝ V²). During this phase, oxygen ions migrate toward the ITO electrode under the influence of the applied electric field [30]. As the applied electric field becomes higher, different slopes occur, leading to a flow of charge through the SiO_x/Si-NCs multilayer, which in turn triggers changes in the microstructure of the SiO_x layers by the breaking-off weak Si-O bonds and setting oxygen ions in motion [31,32,33].

This process generates Si dangling bonds, which form Si-Si bonds that establish connections with the Si-NCs, giving rise to the CF responsible for the increase in current, as shown in Figure 4b. This process allows the RS to change from the HRS to the LRS (SET). Once the device was in the LRS, a slope of about 1.0 was obtained, indicating ohmic conduction as the mechanism responsible for charge transport and CF formation. As shown in Figure 4c, which depicts the bi-logarithmic J-E curves during the transition LRS-HRS (RESET) process, the ohmic conduction remains as the transport mechanism since the device is still in the LRS state. As the current drops during the transition from LRS to HRS, the oxygen ions return to the dielectric matrix, and the device once again alters the microstructure of SiO_x, causing the CF to disconnect (shown in Figure 4d), as evidenced by the slopes of 3.6 and 4.8. Finally, the lowest slope value (1.4) indicates that thermally generated carriers are released from their trapped states (due to oxygen vacancies) [30].

The chemical changes and stoichiometry produced in the SiO_x layers during CF formation–annihilation are observed through the variation in the dielectric constant (ε). When the device is in the LRS, the Si excess within the SiO_x layer moves toward the CF formation, which translates into a more stoichiometric oxide layer. While the opposite process occurs in the annihilation of the CF; the oxygen ions that return to the matrix rebound with the Si atoms that form the CF, expanding the sub-oxide region with increased presence of Si excess throughout the matrix. This chemical restructuration is observed through the switching of the capacitance value because of the changes in the ε value. As observed in Figure 5, the ε value changes from 5.93 (2.52 nF) to 7.11 (3 nF) with an intermediate ε of about 6.57 (2.72 nF) for the LRS, HRS, and IRS, respectively. Therefore, the presence or absence of the CF contributes to oxide capacitance through the Si/O variation in the SiO_x matrix, which leads to a higher/lower ε value [34,35].

4. Conclusions

MIS-like devices were fabricated using SiO₂/Si-NCs/SiO₂ ML structures as active material deposited by sputtering. Through TEM analysis, the presence of Si-NCs embedded in the SiO₂ matrix with a crystallographic orientation of [111] was confirmed. It was possible to observe that the devices showed a bipolar RS with SET and RESET voltages lower than |10 V|, as well as an ON/OFF ratio of 10⁴ and retention times of 10⁴ s, reflecting good operation stability. Furthermore, it was possible to observe changes in the capacitance of the devices when switching between the different resistive states (HRS, IRS, and LRS) due to the important role played by the formation–annihilation of the conductive filaments in the composition of the dielectric matrix, as observed in the changes in the dielectric constant. Finally, the combination of both RS and CS phenomena in the same device allowed for greater versatility in its operation, enabling its application in Si-based NVMs with higher storage security.