Co-sputtering of SiO
2 and high-κ Ta
2O
5 was used to make multicomponent gate dielectric stacks for In-Ga-Zn-O thin-film transistors (IGZO TFTs) under an overall low thermal budget (T = 150 °C). Characterization of the multicomponent layers and of the TFTs working characteristics (employing them) was performed in terms of static performance, reliability, and stability to understand the role of the incorporation of the high-κ material in the gate dielectric stack. It is shown that inherent disadvantages of the high-κ material, such as poorer interface properties and poor gate insulation, can be counterbalanced by inclusion of SiO
2 both mixed with Ta
2O
5 and as thin interfacial layers. A stack comprising a (Ta
2O
5)
x(SiO
2)
100 − x film with x = 69 and a thin SiO
2 film at the interface with IGZO resulted in the best performing TFTs, with field-effect mobility (µ
FE) ≈ 16 cm
2·V
−1·s
−1, subthreshold slope (SS) ≈ 0.15 V/dec and on/off ratio exceeding 10
7. Anomalous
Vth shifts were observed during positive gate bias stress (PGBS), followed by very slow recoveries (time constant exceeding 8 × 10
5 s), and analysis of the stress and recovery processes for the different gate dielectric stacks showed that the relevant mechanism is not dominated by the interfaces but seems to be related to the migration of charged species in the dielectric. The incorporation of additional SiO
2 layers into the gate dielectric stack is shown to effectively counterbalance this anomalous shift. This multilayered gate dielectric stack approach is in line with both the large area and the flexible electronics needs, yielding reliable devices with performance suitable for successful integration on new electronic applications.
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