A Unified Semiconductor-Device-Physics-Based Ballistic Model for the Threshold Voltage of Modern Multiple-Gate Metal-Oxide-Semiconductor Field-Effect-Transistors

Abstract

Based on the minimum conduction band edge caused by the minimum channel potential resulting from the quasi-3D scaling theory and the 3D density of state (DOS) accompanied by the Fermi–Dirac distribution function on the source and drain sides, a unified semiconductor-device-physics-based ballistic model is developed for the threshold voltage of modern multiple-gate (MG) transistors, including FinFET, Ω-gate MOSFET, and nanosheet (NS) MOSFET. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate ballistic effects and resist threshold voltage degradation. In addition, as the device dimension is further reduced to give rise to the 2D/1D DOS, the lowest conduction band edge is increased to resist threshold voltage degradation. The nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge caused by the quasi-3D minimum channel potential. When the n-type MOSFET (N-FET) is compared to the P-type MOSFET (P-FET), the P-FET shows more threshold voltage because the hole has a more effective mass than the electron.

1. Introduction

The modern multiple-gate (MG) MOSFET as shown in Figure 1 is superior to planar MOSFET in suppressing short-channel effects (SCEs) and supporting a higher driving current and packing density. Among the MG transistors, the proposed triple-gate (TG) MOSFET (i.e., FinFET) [1,2,3] with the ultra-thin silicon body and 3D gate oxide coverage can enhance the switching speed and decrease electrostatic power consumption more effectively than the double-gate (DG) MOSFET, which was proposed as the first non-planar MOSFET with unique volume conduction [4,5]. Meanwhile, to further increase the IC packing density to accommodate future graphics processing units (GPUs) with trillions of transistors, the 3D integrated circuit (IC) has been converted from the conventional lateral CMOS layout to the vertical gate-stacked complementary field-effect transistor (CFET) [6,7,8]. The nanosheet MOSFET [9,10,11] comprising CFET has been recognized as an alternative to FinFET and has served as the basic building block for the implementation of next-generation 3D ultra-large-scale integration (ULSI). As the device feature size is further reduced toward 3 nm/2 nm, the free carriers can directly arrive in the drain side without backscattering because the feature size is smaller than the mean free path. This implies that the traditional drift-diffusion model (DDM), based on the thermal equilibrium between the free carriers and the lattice, is no longer accurate for developing the model of device behavior. Instead of DDM, the ballistic transport model (BTM) should be applied to model the device. The threshold voltage is one of the essential semiconductor device parameters that must be carefully monitored when the 3D ULSI is evaluated for its electrostatic power consumption to achieve power saving. In this work, a unified threshold voltage model for the ballistic FinFET, Ω-gate MOSFET, and nanosheet transistor is achieved based on the quasi-3D scaling theory, the density of state, and the Fermi–Dirac distribution function. It is shown that the thin silicon, thin gate oxide, and high work function will alleviate the ballistic effects and resist threshold voltage degradation. In addition, the nanosheet MOSFET exhibits the largest threshold voltage among the three transistors due to the smallest minimum conduction band edge. As the device height/width is further reduced to bring about 2D/1D DOS for the MG MOSFETs, the threshold voltage will be increased to some extent because the 2D/1D DOS can induce a smaller carrier concentration than the 3D DOS for the transistors.

2. Model Description

2.1. Quasi-3D Scaling Theory for the Ballistic MG MOSFETs

As the device is further scaled down to work in the subthreshold regime, where the electrical field parallel to the channel direction strongly affects the device’s behavior, the channel potential of Φ_MC can be governed by the quasi-3D scaling theory by accounting for the short-channel effects [12]:

$${\displaystyle \frac{d^2{\mathrm{\Phi }}_{MC}(z)}{d{z}^2}}+{\displaystyle \frac{{\mathrm{\Phi }}_{MC}(z)-{\varphi }_{MCL}}{{{\lambda }_{MG}}^2}}=0$$

(1)

with

$$\left\{\begin{array}{l}{\varphi }_{MCL}=V_{gs}-V_{fb}-{\displaystyle \frac{q{N}_a{{\lambda }_{MG}}^2}{{\epsilon }_{si}}}\\ {\displaystyle \frac{1}{{{\lambda }_{MG}}^2}}={\displaystyle \frac{1}{{\theta }^2}}\left({\displaystyle \frac{\rho }{{{\lambda }_{SG-x-z}}^2}}+{\displaystyle \frac{1-\rho }{{{\lambda }_{DG-x-z}}^2}}+{\displaystyle \frac{1}{{{\lambda }_{DG-y-z}}^2}}\right)\end{array}\right.$$

(2)

$$\left\{\begin{array}{l}{\lambda }_{SG-x-z}=\sqrt{{\displaystyle \frac{\left(2C_H+C_{ox}\right)H^2}{2C_{ox}}}},{\lambda }_{DG-x-z}=\sqrt{{\displaystyle \frac{\left(4C_H+C_{ox}\right)H^2}{8C_{ox}}}}\\ {\lambda }_{DG-y-z}=\sqrt{{\displaystyle \frac{\left(4C_W+C_{ox}\right)W^2}{8C_{ox}}}},\alpha ={\displaystyle \frac{W_o}{W}}\end{array}\right.$$

(3)

$$C_H={\displaystyle \frac{{\epsilon }_{si}}{H}},C_W={\displaystyle \frac{{\epsilon }_{si}}{W}},C_{ox}={\displaystyle \frac{{\epsilon }_{ox}}{t_{ox}}},V_{fb}={\mathrm{\Phi }}_m-{\mathrm{\Phi }}_s$$

(4)

where φ_MCL is the long-channel bulk potential. The 3D scaling length λ_MG in (1) can be expressed in (2), where λ_SG–x–z, λ_DG–x–z, and λ_DG–y–z are the 2D scaling lengths for the single-gate and double-gate MOSFETs residing in the x–z and y–z cut planes, respectively. $\theta$ ($1\le \theta <2$) considers the coupling effects between the x–z and y–z planes and a is the ratio of single-gate oxide to the entire gate oxide in the y–z cut plane. For nanosheet MOSFET, one obtains $\rho$ = 0; for FinFET MOSFET, we have $\rho$ = 1. However, 0 < $\rho$ < 1 should be used to develop the 3D scaling length for Ω-gate MOSFET, and W_o is the opening at the bottom gate oxide of Ω-gate FET. The channel width, height, and gate oxide thickness in (3) are denoted by W, H, and t_ox. The difference in work function between the gate material and silicon body causes the flat-band voltage of V_fb in (4). The solution of (1) can be obtained as

$${\mathrm{\Phi }}_{MC}(z)=T{e}^{{\displaystyle \frac{-{\lambda }_{MG}}{z}}}+U{e}^{{\displaystyle \frac{{\lambda }_{MG}}{z}}}+{\varphi }_{MCL}$$

(5)

With the boundary conditions of Φ_MC(z = 0) = V_bi and Φ_MC(Z = L_g) = V_bi + V_ds; the coefficients for T and U in (5) can be obtained as

$$T={\displaystyle \frac{\left(V_{bi}-{\varphi }_{MCL}\right)e^{L_g/{\lambda }_{MG}}-\left(V_{bi}+V_{ds}-{\varphi }_{MCL}\right)}{2\sinh \left(L_g/{\lambda }_{MG}\right)}}$$

(6)

$$U=-{\displaystyle \frac{\left(V_{bi}-{\varphi }_{MCL}\right)e^{-L_g/{\lambda }_{MG}}-\left(V_{bi}+V_{ds}-{\varphi }_{MCL}\right)}{2\sinh \left(L_g/{\lambda }_{MG}\right)}}$$

(7)

where V_ds and V_bi are the drain voltage and built-in potential at the junction between the source/drain and channel. With (6) and (7), the minimum channel potential for the ballistic MG MOSFETs can be expressed as

$${\mathrm{\Phi }}_{\min }=2\sqrt{TU}+V_{gs}-V_{fb}-{\displaystyle \frac{q{N}_a{{\lambda }_{MG}}^2}{{\epsilon }_{si}}}$$

(8)

Both T and U in (8) can be linearized for V_gs, which leads to

$$T=\alpha V_{gs}+\beta , U=\kappa V_{gs}+\delta$$

(9)

with

$$\alpha ={\displaystyle \frac{1-e^{L_g/{\lambda }_{MG}}}{2\sinh \left(L_g/{\lambda }_{MG}\right)}}, \beta ={\displaystyle \frac{(V_{bi}+V_{fb}+\frac{q{N}_a{{\lambda }_{MG}}^2}{{\epsilon }_i})(e^{\frac{L_g}{{\lambda }_{MG}}}-1)-V_{ds}}{2\sinh \left(L_g/{\lambda }_{MG}\right)}}$$

(10)

$$\kappa ={\displaystyle \frac{e^{-L_g/{\lambda }_{MG}}-1}{2\sinh \left(L_g/{\lambda }_{MG}\right)}}, \delta ={\displaystyle \frac{V_{ds}-(V_{bi}+V_{fb}+\frac{q{N}_A{{\lambda }_{MG}}^2}{{\epsilon }_{si}})(e^{\frac{-L_g}{{\lambda }_{MG}}}-1)}{2\mathrm{S}inh\left(L_g/{\lambda }_{MG}\right)}}$$

(11)

2.2. Free Electron Concentration for the Ballistic MG MOSFETs

The free electron concentration for the MG MOSFETs by considering the ballistic transport mode (BTM) can be expressed as follows:

$$n={\displaystyle \underset{E_{C,\min }}{\overset{\propto }{\int }}{g}_v\times D(E)\times \left[f_s(E)-f_d(E)\right]dE}$$

(12)

where g_v is the silicon degeneracy; D(E) is the density of state (DOS), which has been divided by 2 by considering the electron per spin in calculating free electron concentration; and f_s(E) and f_d(E) are the Fermi–Dirac distribution functions on the source/drain sides, respectively. The 3D DOS in (12), by considering the 3D wave equation, can be obtained as

$$D(E)={\displaystyle \frac{4\pi m^{*}\sqrt{2m^{*}(E-E_{C,\min })}}{h^3}}$$

(13)

with

$$E_{C,\min }=E_C-q{\mathrm{\Phi }}_{\min }$$

(14)

where m* is the effective mass of the electron, and E_C,min is the minimum conduction edge caused by the minimum channel potential of Φ_min, as shown in (8). The Fermi–Dirac distribution functions on the source/drain sides can be expressed as

$$f_s(E)={\displaystyle \frac{1}{1+e^{(E-F_{FS})/kT}}},f_d(E)={\displaystyle \frac{1}{1+e^{(E-F_{Fd})/kT}}}$$

(15)

with

$$E_{Fd}=E_{Fs}-q{V}_{ds}$$

(16)

where E_Fd and E_Fs are the quasi-Fermi levels on the drain/source sides, respectively. By substituting (13)–(16) into (12), the free electron concentration for the ballistic MG MOSFETs can be obtained as

$$n={\displaystyle \frac{g_v{T}_o{\left(\sqrt{2kT{m}^{*}\pi }\right)}^3}{h^3}}\left[F_{1/2}({\eta }_{Fs})-F_{1/2}({\eta }_{Fd})\right]$$

(17)

with

$$\left\{\begin{array}{l}{F}_{1/2}({\eta }_{Fs})={\displaystyle \frac{2}{\sqrt{\pi }}}{\displaystyle {\int }_0^{+\propto }{\eta }^{1/2}\left(\frac{1}{1+e^{\eta -{\eta }_{Fs}}}\right)d}\eta \\ F_{1/2}({\eta }_{Fd})={\displaystyle \frac{2}{\sqrt{\pi }}}{\displaystyle {\int }_0^{+\propto }{\eta }^{1/2}\left(\frac{1}{1+e^{\eta -{\eta }_{Fd}}}\right)d}\eta \end{array}\right.$$

(18)

and

$$\left\{\begin{array}{l}{\eta }_{Fs}={\displaystyle \frac{(E_{Fs}-E_{C,\min })}{kT}}, {\eta }_{Fd}={\displaystyle \frac{(E_{Fs}-q{V}_{ds}-E_{C,\min })}{kT}}\\ E_{Fs}=E_C-\left({\displaystyle \frac{E_G}{2}}+kT\ln {\displaystyle \frac{N_d{N}_a}{{n_i}^2}}\right)\end{array}\right.$$

(19)

where $F_{1/2}({\eta }_{Fs})$ and $F_{1/2}({\eta }_{Fs})$ are the Fermi–Dirac integrals of order 1/2. For the non-degenerate carrier statistics (i.e., Maxwell Boltzmann statistics), (17) can be further reduced as

$$n={\displaystyle \frac{g_v{\left(\sqrt{2kT{m}^{*}\pi }\right)}^3}{h^3}}{e}^{{\displaystyle \frac{E_{Fs}-E_C}{kT}}}{e}^{{\displaystyle \frac{{\mathrm{\Phi }}_{\min }}{V_T}}}\left(1-e^{{\displaystyle \frac{-q{V}_{ds}}{kT}}}\right)$$

(20)

because the Fermi–Dirac integral of any order can be reduced as exponential terms (i.e., F_i(h) = e^h), which is shown as follows:

$$\left\{\begin{array}{l}{F}_{1/2}({\eta }_{Fs})={\displaystyle \frac{2}{\sqrt{\pi }}}{\displaystyle {\int }_0^{+\propto }{\eta }^{1/2}\left(\frac{1}{1+e^{\eta -{\eta }_{Fs}}}\right)d}\eta \approx e^{{\eta }_{Fs}} \\ F_{1/2}({\eta }_{Fd})={\displaystyle \frac{2}{\sqrt{\pi }}}{\displaystyle {\int }_0^{+\propto }{\eta }^{1/2}\left(\frac{1}{1+e^{\eta -{\eta }_{Fd}}}\right)d}\eta \approx e^{{\eta }_{Fd}}\end{array}\right.$$

(21)

2.3. Criterion of Threshold Voltage for the Ballistic MG MOSFETs

To attain the threshold condition, the minority carrier concentration of n-FET should be equal to the majority carrier concentration of p-FET. This implies that the electron concentration of n in N-FET should be equal to N_a of P-substrate by assuming the complete impurity ionization (i.e., p $\approx$ N_a) in P-FET. According to the criterion of threshold condition, the threshold voltage of gate bias should satisfy the following criterion:

$${\left.n\right|}_{V_{gs}=V_{th}}=N_a$$

(22)

where Vth is the threshold voltage. By substituting (22) into (20), the minimum channel potential corresponding to the threshold criterion can be obtained as

$${\mathrm{\Phi }}_{\min ,3D}=V_T\ln \left({\displaystyle \frac{N_a{h}^3}{g_v{\left(\sqrt{2kT{m}^{*}\pi }\right)}^3{e}^{\frac{E_{Fs}-E_C}{kT}}\left(1-e^{\frac{-q{V}_{ds}}{kT}}\right)}}\right)$$

(23)

From (8)–(11), and (23), the threshold voltage can be achieved by solving for the quadratic equation of V_gs. This leads to

$$V_{th}={\displaystyle \frac{S-\sqrt{S^2-4RV}}{2R}}$$

(24)

with

$$\left\{\begin{array}{l}R=\left(1-4\alpha \kappa \right) , S=2\gamma +4\left(\beta \kappa +\alpha \delta \right)\\ V={\gamma }^2-4\beta \delta , \gamma ={\mathrm{\Phi }}_{\min ,3D}+V_{fb}+{\displaystyle \frac{q{N}_a{{\lambda }_{MG}}^2}{{\epsilon }_{si}}}\end{array}\right.$$

(25)

It should be noted that the BTM brings about the new minimum channel potential shown in (23), which can uniquely determine the threshold voltage for the ballistic MG MOSFETs.

2.4. Free Electron Concentration for the Low-Dimensional Ballistic MG MOSFETs

As the device height/weight is shrunk and comparable/smaller than the electron wavelength (~2 nm), the 2D/1D DOS should be applied to derive the free electron concentration for the device. The 2D/1D DOS for the MG transistors can be obtained by solving the 2D/1D wave equation. This leads to

$$\left\{\begin{array}{l}{D}_{2\mathrm{D}}(E)=\left({\displaystyle \frac{2\pi m^{*}}{h^2}}\right)\\ D_{1D}(E)=\sqrt{{\displaystyle \frac{m^{*}}{2h^2\left(E-E_{C,\min }\right)}}}\end{array}\right.$$

(26)

D_2D(E) and D_1D(E) have considered the spin per electron. According to the similar developing procedure as shown in (12), the 2D/1D free electron concentration can be expressed as

$$n_{2D}=\left({\displaystyle \frac{2m^{*}{g}_{v}kT}{h^2}}\right)\left[F_0({\eta }_{Fs})-F_0({\eta }_{Fd})\right]$$

(27)

$$n_{1D}=\left(\sqrt{{\displaystyle \frac{m^{*}\pi }{2}}}{\displaystyle \frac{g_v}{h}}\right)\left[F_{-1/2}({\eta }_{Fs})-F_{-1/2}({\eta }_{Fd})\right]$$

(28)

where F₀(h_F) and F_−1/2(h_F) are the Fermi–Dirac integrals of orders 0 and −1/2, respectively. They can be expressed as

$$\left\{\begin{array}{l}{F}_0({\eta }_F)={\displaystyle {\int }_0^{+\propto }\frac{1}{1+e^{\eta -{\eta }_F}}d}\eta \\ F_{-1/2}({\eta }_F)={\displaystyle \frac{1}{\sqrt{\pi }}}{\displaystyle {\int }_0^{\propto }\frac{{\eta }^{-1/2}}{1+e^{\eta -{\eta }_F}}d\eta }\end{array}\right.$$

(29)

Similarly, in terms of non-degenerate carrier statistics, (27) and (28) can be further reduced as

$$n_{2D}=\left({\displaystyle \frac{2m^{*}{g}_{v}kT}{h^2}}\right)e^{{\displaystyle \frac{E_{F1}-E_C}{kT}}}{e}^{{\displaystyle \frac{{\mathrm{\Phi }}_{\min }}{V_T}}}\left(1-e^{{\displaystyle \frac{-q{V}_{ds}}{kT}}}\right)$$

(30)

$$n_{1D}=\left(\sqrt{{\displaystyle \frac{m^{*}\pi }{2}}}{\displaystyle \frac{g_v}{h}}\right)e^{{\displaystyle \frac{E_{F1}-E_C}{kT}}}{e}^{{\displaystyle \frac{{\mathrm{\Phi }}_{\min }}{V_T}}}\left(1-e^{{\displaystyle \frac{-q{V}_{ds}}{kT}}}\right)$$

(31)

2.5. Criterion of Threshold Voltage for the Low-Dimensional Ballistic MG MOSFETs

By setting the free electron density equal to the substrate doping concentration, as shown in (22), the criterion of threshold voltage for 2D and 1D MG devices can be shown as

$${\mathrm{\Phi }}_{\min ,2D}=V_T\ln \left({\displaystyle \frac{N_a\times W\times h^2}{\left(2\pi g_v{m}^{*}kT\right)e^{\frac{E_{F1}-E_C}{kT}}\left(1-e^{\frac{-q{V}_{ds}}{kT}}\right)}}\right)$$

(32)

$${\mathrm{\Phi }}_{\min ,1D}=V_T\ln \left({\displaystyle \frac{N_a\times W\times H\times h}{g_v\left(\sqrt{0.5\times m^{*}kT\pi }\right)e^{\frac{E_{F1}-E_C}{kT}}\left(1-e^{\frac{-q{V}_{ds}}{kT}}\right)}}\right)$$

(33)

By replacing Φ_min,3D with Φ_min,2D and Φ_min,1D, the threshold voltage for 2D and 1D MG MOSFETs can be obtained.

3. Results and Discussion

The 3D device simulator “SDEVICE” was employed to validate the proposed model [13]. Unless otherwise stated, the following device parameters were used to simulate the MG MOSFETs: the device structure’s square shape, the effective electron mass = 1.08m₀, and the valley degeneracy of the silicon g_v = 6. The following physics models for “SDEVICE” were used to simulate the device: (1) The graded density model was included to simulate the carrier density by accounting for the carrier confinement. (2) The bandgap narrowing model was included for doping concentration bandgap correction. (3) The effective carrier density was included to account for the bandgap narrowing effects. (4) The electron quantum potential model was included to simulate the electrostatic potential, ensuring that the Poisson equation was self-consistent with the wave equation. (5) The doping-dependent mobility model was included to simulate the impurity scattering effect. (6) The SRH recombination model accounted for doping-dependent and temperature-dependent effects. (7) The ballistic mobility was included to account for the ballistic effects. Figure 2 plots the threshold voltage versus the channel length of FinFET for different silicon thicknesses. As the channel length decreased, the thin silicon produced a larger threshold voltage than the thick silicon due to the alleviated ballistic effects that result in threshold voltage degradation. Figure 3 plots the threshold voltage versus the channel length of Ω-gate MOSFET for different oxide thicknesses. The thin gate oxide that effectively resists the ballistic effects induced a smaller threshold voltage degradation than the thick gate oxide. Figure 4 shows how the work function affected the threshold voltage as the channel length decreased for nanosheet MOSFET. The high work function brought about a high threshold voltage as the channel length decreased, as opposed to the low work function, which reduced the threshold voltage due to the strong ballistic effects. To show how the different dimensionalities of the devices affect the threshold voltage, Figure 5 shows the different ratios of device width to device height (i.e., W $\times$ H) used by considering (2 nm $\times$ 2 nm), (2 nm $\times$ 5 nm), and (5 nm $\times$ 5 nm) cross-section areas of FinFET, with the channel length decreasing from 20 nm to 10 nm. Note that as the device dimension approaches the electron wavelength of ~2 nm, the 2D/1D density of state should be accounted for in calculating the electron concentration, as shown in Figure 5. It is shown that the 1D device with the cross-section area of 2 nm $\times$ 2 nm induced the largest threshold voltage as opposed to the 3D device with the cross-section area of 5 nm $\times$ 5 nm, which resulted in the smallest threshold voltage because the high-dimensional device could not effectively alleviate the ballistic effects that degraded the threshold voltage. Figure 6 shows the threshold voltage versus the channel length for different devices’ structures, including nanosheet MOSFET, Ω-gate MOSFET, and FinFET. The nanosheet MOSFET exhibited the largest threshold voltage and smallest threshold voltage degradation with the gate surrounding the channel regime. On the other hand, FinFET, with the smallest gate coverage, showed the smallest threshold voltage and largest threshold voltage degradation among the three devices. The device and material parameters such as channel width (W), channel height (H), oxide thickness (T_ox), and work function (F_M) had the same effect on the different device structures such as FinFET, Ω-gate FET, and nanosheet FET. In other words, Figure 2 can also be used to describe the Ω-gate FET and nanosheet FET. Figure 3 can also be used to illustrate FinFET and nanosheet. Figure 4 can also be applied to demonstrate Ω-gate FET and FinFET. It is known that the scaling factor provides the designing guidance for the subthreshold behavior of the MG devices [14,15]. Since the scaling factor “L_g/2λ_MG” inherited from the MG devices affects the threshold voltage significantly [15], Figure 7 plots the threshold voltage versus the scaling factor for different silicon and oxide combinations of the FinFET. It can be seen that as the scaling factor was reduced to below three, the threshold voltage significantly degraded. Therefore, when designing the MG MOSFETs, the allowable silicon/oxide thickness combinations corresponding to the appropriate scaling factor should be carefully accounted for.

4. Conclusions

For modern multiple-gate (MG) transistors composed of FinFET, Ω-gate MOSFET, and nanosheet MOSFET, a unified ballistic model for the threshold voltage is proposed and validated. The model can also be applied to P-type MG devices by interchanging the device parameters between electron and hole. Accompanied by the P-type MG MOSFET, the modern complementary gate-stacked MOSFET (i.e., CFET) can be integrated to simulate the subthreshold logic circuit for its low-power circuit application.