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Cryptography
Special Issues
Implementation and Verification of Secure Hardware against Physical Attacks
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Implementation and Verification of Secure Hardware against Physical Attacks

A special issue of Cryptography (ISSN 2410-387X). This special issue belongs to the section "Hardware Security".

Deadline for manuscript submissions: closed (15 March 2022) | Viewed by 20373

Special Issue Editors

Dr. Itamar Levi

E-Mail Website
Guest Editor
Faculty of Engineering, Bar-Ilan University, Ramat Gan 5290002, Israel
Interests: cryptographic hardware and embedded systems; hardware countermeasures against physical and side channel attacks; hardware security analysis; security evaluation and methodologies; TRNGs and PUFs; power reduction methodologies for high-speed VLSI
Dr. Johann Knechtel

E-Mail Website
Guest Editor
Division of Engineering, New York University, Saadiyat Island, Abu Dhabi PO Box 129188, United Arab Emirates
Interests: hardware security; electronic design automation (EDA); 3D integration; emerging Technologies
Prof. Dr. Selçuk Köse

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA
Interests: hardware security; VLSI
Dr. Giuseppe Scotti

E-Mail Website
Guest Editor
Department of Electronics, Information and Communication Engineering, Sapienza University of Rome, 00185 Rome, Italy
Interests: CMOS integrated circuits; cryptographic hardware and side channel attacks; countermeasures against power analysis attack; design methodologies for secure Ips; PUFs design methodologies and implementation on both ASIC and FPGA platforms

Special Issue Information

Dear Colleagues,

Secured electronic systems are of paramount importance for all computational platforms and for various applications. From stand-alone rarely communicating devices such as biochips, through network-connected complex and smart devices such as AI accelerators and actuators, to high-computational power network devices, all are vulnerable to local and remote physical attacks. Implementation-related aspects of cryptographic systems and their real-world sensitivities is in the focus of this Special Issue. The spectrum of challenges related to hardware security is very broad, including design, manufacturing, testing, validation, and the ability to bring into play robust mechanisms which will be supported by the industry and are agnostic to design and verification tools. We welcome submissions spanning side-channel security aspects through secure supply chains and manufacturing, sensitivity to fault injection and protection mechanisms, and security-oriented design automation. More specifically, this Special Issue promotes aspects closely connected with implementation, technological, and architectural aspects of cryptographic hardware. From design-for-security and security analysis (e.g., 3D integration technologies and security of new platforms such as multi-sensor devices), through utilization of security mechanisms and their analysis, e.g., power regulators and sensors, to various hardware security-related aspects, we welcome theoretical analysis, optimization, and security evaluation of all of these aspects.   

Guidelines:

Authors are invited to submit a title and an extended abstract of the proposed manuscript, potentially covering, but not limited to, the following topics:

-Hardware security analysis of primitives

-Protection mechanisms for symmetric/asymmetric designs (e.g., facing horizontal attacks)

-Side-channel analysis, including attack modeling, simulation and countermeasures.

-Fault injection, detection, attacks and modeling

-Analysis, modeling and implementation aspects of true random number generators (TRNGs) and physically unclonable functions (PUFs)

-Protection from AI architectures and AI-assisted attacks supported by rigorous analysis

-Analysis of hardware trojans and devices’ reconfigurability/reprogramming

-Validation and evaluation methodologies for physical security

-Novel and emerging technologies for security applications

Dr. Itamar Levi
Dr. Johann Knechtel
Prof. Dr. Selçuk Köse
Dr. Giuseppe Scotti
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Cryptography is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Hardware security
  • Side-channel analysis attacks
  • Attack modeling
  • Attacks simulation
  • Attack detection mechanisms and circuitry
  • Hardware/software countermeasures
  • Fault injection
  • Fault detection
  • Analysis and modeling of TRNGs
  • Theoretical analysis and modeling of PUFs
  • Design and validation of secure hardware
  • Security evaluation tools and methodologies

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Published Papers (5 papers)

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22 pages, 1595 KiB  
Article
A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL
by Abhrajit Sengupta, Mohammed Nabeel, Mohammed Ashraf, Johann Knechtel and Ozgur Sinanoglu
Cryptography 2022, 6(2), 22; https://doi.org/10.3390/cryptography6020022 - 5 May 2022
Cited by 1 | Viewed by 3310
Abstract
Split manufacturing was introduced as a countermeasure against hardware-level security threats such as IP piracy, overbuilding, and insertion of hardware Trojans. However, the security promise of split manufacturing has been challenged by various attacks which exploit the well-known working principles of design tools [...] Read more.
Split manufacturing was introduced as a countermeasure against hardware-level security threats such as IP piracy, overbuilding, and insertion of hardware Trojans. However, the security promise of split manufacturing has been challenged by various attacks which exploit the well-known working principles of design tools to infer the missing back-end-of-line (BEOL) interconnects. In this work, we define the security of split manufacturing formally and provide the associated proof, and we advocate accordingly for a novel, formally secure paradigm. Inspired by the notion of logic locking, we protect the front-end-of-line (FEOL) layout by embedding secret keys which are implemented through the BEOL in such a way that they become indecipherable to foundry-based attacks. At the same time, our technique is competitive with prior art in terms of layout overhead, especially for large-scale designs (ITC’99 benchmarks). Furthermore, another concern for split manufacturing is its practicality (despite successful prototyping). Therefore, we promote an alternative implementation strategy, based on package-level routing, which enables formally secure IP protection without splitting at all, and thus, without the need for a dedicated BEOL facility. We refer to this as “poor man’s split manufacturing” and we study the practicality of this approach by means of physical-design exploration. Full article
(This article belongs to the Special Issue Implementation and Verification of Secure Hardware against Physical Attacks)
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23 pages, 5667 KiB  
Article
The Cost of a True Random Bit—On the Electronic Cost Gain of ASIC Time-Domain-Based TRNGs
by Netanel Klein, Eyal Harel and Itamar Levi
Cryptography 2021, 5(3), 25; https://doi.org/10.3390/cryptography5030025 - 18 Sep 2021
Cited by 7 | Viewed by 3774
Abstract
Random number generators are of paramount importance in numerous fields. Under certain well-defined adversarial settings, True Random Number Generators (TRNGs) are more secure than their computational (pseudo) random number generator counterparts. TRNGs are also known to be more efficiently implemented on hardware platforms [...] Read more.
Random number generators are of paramount importance in numerous fields. Under certain well-defined adversarial settings, True Random Number Generators (TRNGs) are more secure than their computational (pseudo) random number generator counterparts. TRNGs are also known to be more efficiently implemented on hardware platforms where, for various applications, efficiency in terms of electronic cost factors is critical. In this manuscript, we first provide an evaluation of robustness and reliability of efficient time-domain-based TRNG implementation over FPGA platform. In particular, we demonstrate sensitivities which imply a TRNG construction which is not agnostic to electronic-design-automation tools and to the level of designers’ know-how. This entails a large amount of effort and validation to make the designs robust, as well as requires a high degree of complexity from non-trivial FPGAs flows. This motivates the second part of the manuscript, where we propose an ASIC-based implementation of the TRNG, along with the optimization steps to enhance its characteristics. The optimized design improves the randomness-throughput by 42× for the same entropy level described in previous works, and it can provide maximal entropy level of 0.985 with 7× improvement in randomness throughput over the raw samples (no pre-processing). The proposed design simultaneously provides a reduced energy of 0.1 (mW/bit) for the same entropy level as previous works, and 1.06 (mW/bit) for the higher entropy flavor, and a lower area utilization of 0.000252 (mm2) on a 65 nm technology evaluation, situating it in the top-class of the discuss ratings. This leads to the quantitative question of the gain in electronic cost factors over ASIC TRNGs, and the minimum Cost Per Bit/Source possible to date. Finally, we exemplify a TRNG versus PRNG cost-extrapolation for security architects and designers, targeting an ASIC scenario feeding a lightweight encryption core. Full article
(This article belongs to the Special Issue Implementation and Verification of Secure Hardware against Physical Attacks)
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22 pages, 3151 KiB  
Article
Improved Filtering Techniques for Single- and Multi-Trace Side-Channel Analysis
by Dor Salomon, Amir Weiss and Itamar Levi
Cryptography 2021, 5(3), 24; https://doi.org/10.3390/cryptography5030024 - 13 Sep 2021
Cited by 3 | Viewed by 3521
Abstract
Side-channel analysis (SCA) attacks constantly improve and evolve. Implementations are therefore designed to withstand strong SCA adversaries. Different side channels exhibit varying statistical characteristics of the sensed or exfiltrated leakage, as well as the embedding of different countermeasures. This makes it crucial to [...] Read more.
Side-channel analysis (SCA) attacks constantly improve and evolve. Implementations are therefore designed to withstand strong SCA adversaries. Different side channels exhibit varying statistical characteristics of the sensed or exfiltrated leakage, as well as the embedding of different countermeasures. This makes it crucial to improve and adapt pre-processing and denoising techniques, and abilities to evaluate the adversarial best-case scenario. We address two popular SCA scenarios: (1) a single-trace context, modeling an adversary that captures only one leakage trace, and (2) a multi-trace (or statistical) scenario, that models the classical SCA context. Given that horizontal attacks, localized electromagnetic attacks and remote-SCA attacks are becoming evermore powerful, both scenarios are of interest and importance. In the single-trace context, we improve on existing Singular Spectral Analysis (SSA) based techniques by utilizing spectral property variations over time that stem from the cryptographic implementation. By adapting overlapped-SSA and optimizing over the method parameters, we achieve a significantly shorter computation time, which is the main challenge of the SSA-based technique, and a higher information gain (in terms of the Signal-to-Noise Ratio (SNR)). In the multi-trace context, a profiling strategy is proposed to optimize a Band-Pass Filter (BPF) based on a low-computational cost criterion, which is shown to be efficient for unprotected and low protection level countermeasures. In addition, a slightly more computationally intensive optimized ‘shaped’ filter is presented that utilizes a frequency-domain SNR-based coefficient thresholding. Our experimental results exhibit significant improvements over a set of various implementations embedded with countermeasures in hardware and software platforms, corresponding to varying baseline SNR levels and statistical leakage characteristics. Full article
(This article belongs to the Special Issue Implementation and Verification of Secure Hardware against Physical Attacks)
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19 pages, 885 KiB  
Article
A Novel Ultra-Compact FPGA PUF: The DD-PUF
by Riccardo Della Sala, Davide Bellizia and Giuseppe Scotti
Cryptography 2021, 5(3), 23; https://doi.org/10.3390/cryptography5030023 - 8 Sep 2021
Cited by 22 | Viewed by 4618
Abstract
In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a [...] Read more.
In this paper, we present a novel ultra-compact Physical Unclonable Function (PUF) architecture and its FPGA implementation. The proposed Delay Difference PUF (DD-PUF) is the most dense FPGA-compatible PUF ever reported in the literature, allowing the implementation of two PUF bits in a single slice and provides very good values for all the most important figures of merit. The architecture of the proposed PUF exploits the delay difference between two nominally identical signal paths and the metastability features of D-Latches with an asynchronous reset input. The DD-PUF has been implemented on both Xilinx Spartan-6 and Artix-7 devices and the resulting design flows which allow to accurately balance the nominal delay of the different signal paths is outlined. The circuits have been extensively tested under temperature and supply voltage variations and the results of our evaluations on both FPGA families have shown that the proposed architecture and implementation are able to fit in just 32 Configurable Logic Blocks (CLBs) without sacrificing steadiness, uniqueness and uniformity, thus outperforming most of the previously published FPGA-compatible PUFs. Full article
(This article belongs to the Special Issue Implementation and Verification of Secure Hardware against Physical Attacks)
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16 pages, 3824 KiB  
Article
SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks
by Davide Bellizia, Riccardo Della Sala and Giuseppe Scotti
Cryptography 2021, 5(3), 16; https://doi.org/10.3390/cryptography5030016 - 28 Jun 2021
Cited by 1 | Viewed by 3426
Abstract
With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the [...] Read more.
With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL. Full article
(This article belongs to the Special Issue Implementation and Verification of Secure Hardware against Physical Attacks)
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