Search for Articles:
Title / Keyword
Author / Affiliation / Email
Journal
Article Type
 
 
Advanced Search
 
Section
Special Issue
Volume
Issue
Number
Page
 
5.3
2.6
Journals
Electronics
Special Issues
Selected Papers from XXXVIII Conference on Design of Circuits and...
share announcement

Selected Papers from XXXVIII Conference on Design of Circuits and Integrated Systems—DCIS 2023

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: 30 November 2024 | Viewed by 3754

Special Issue Editors

Dr. Francisco Javier González-Cañete

E-Mail Website
Guest Editor
Departamento de Tecnología Electrónica, Universidad de Málaga, ETSI Telecomunicación, 29071 Málaga, Spain
Interests: ad hoc networks; manets; falling detection; wearables; sensors; wireless sensor networks; WSN
Dr. Martín González García

E-Mail Website
Guest Editor
Departamento Tecnologia Electronica, ETSI Telecomunicacion, University of Málaga, 29010 Málaga, Spain
Interests: ASIC; FPGA; microelectronic design; hardware processing in artificial vision
Prof. Dr. Antonio J. Lopez-Martin

E-Mail Website
Guest Editor
Department of Electrical, Electronic and Communications Engineering, Public University of Navarra, Campus Arrosadia, 31006 Pamplona, Spain
Interests: microelectronic design; wireless communications, signal processing and instrumentation
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The XXXVIII Conference on Design of Circuits and Integrated Systems (DCIS 2023) will be held on the 15–17 November 2023, Málaga, Spain. DCIS 2023 aims to provide a platform for researchers in the highly active fields of micro- and nano-electronic circuits and integrated systems. It will provide an excellent forum to present and discuss works on the emerging challenges offered by technology in the areas of modelling, design, implementation and the testing of devices, circuits and systems. Authors of accepted papers are invited to submit the extended versions (at least 50% extension for the submissions) of their original papers and contributions.

The topics of interest include, but are not limited to, the following:

  • Analog/mixed-signal circuits and systems;
  • Design of power-, thermal- and variability-aware circuits and systems;
  • New computing and hardware paradigms (machine learning, approximate and stochastic computing, bio-inspired computing, cognitive computing, etc.);
  • Circuits and systems in advanced and emerging technologies (FDSOI, 3DICs, NVRAM, NWFET, silicon photonics, quantum, etc.);
  • Reconfigurable devices and systems (FPGA, NVRAM, memristors, etc.);
  • Embedded and high-performance computing;
  • EDA tools and methods;
  • Industrial and power electronics;
  • Sustainable computing and systems;
  • Sensory circuits and systems;
  • Energy management and harvesting;
  • Test, fault tolerance, reliability and modelling;
  • Radiofrequency ICs (5G, 6G, RFID, NFC, etc.);
  • On-chip and off-chip interconnects;
  • IoT and applications (industry 4.0, personalized healthcare, etc.);
  • Hardware security;
  • Educational Methods for Electronics.

Dr. Francisco Javier González-Cañete
Dr. Martín González García
Prof. Dr. Antonio Lopez-Martin
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • analog circuits
  • integrated circuits
  • mixed signals
  • signal processing
  • system-on-chip

Benefits of Publishing in a Special Issue

  • Ease of navigation: Grouping papers by topic helps scholars navigate broad scope journals more efficiently.
  • Greater discoverability: Special Issues support the reach and impact of scientific research. Articles in Special Issues are more discoverable and cited more frequently.
  • Expansion of research network: Special Issues facilitate connections among authors, fostering scientific collaborations.
  • External promotion: Articles in Special Issues are often promoted through the journal's social media, increasing their visibility.
  • e-Book format: Special Issues with more than 10 articles can be published as dedicated e-books, ensuring wide and rapid dissemination.

Further information on MDPI's Special Issue polices can be found here.

Published Papers (3 papers)

Download All Papers
Order results
Result details
Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:

Research

11 pages, 480 KiB  
Article
High-Data-Rate Modulators Based on Graphene Transistors: Device Circuit Co-Design Proposals
by Anibal Pacheco-Sanchez, J. Noé Ramos-Silva, Nikolaos Mavredakis, Eloy Ramírez-García and David Jiménez
Electronics 2024, 13(20), 4022; https://doi.org/10.3390/electronics13204022 - 12 Oct 2024
Viewed by 798
Abstract
The multifunctionality feature of graphene field-effect transistors (GFETs) is exploited here to design circuit building blocks of high-data-rate modulators by using a physics-based compact model. Educated device performance projections are obtained with the experimentally calibrated model and used to choose an appropriate improved [...] Read more.
The multifunctionality feature of graphene field-effect transistors (GFETs) is exploited here to design circuit building blocks of high-data-rate modulators by using a physics-based compact model. Educated device performance projections are obtained with the experimentally calibrated model and used to choose an appropriate improved feasible GFET for these applications. Phase-shift and frequency-shift keying (PSK and FSK) modulation schemes are obtained with 0.6 GHz GFET-based multifunctional circuits used alternatively in different operation modes: inverting and in-phase amplification and frequency multiplication. An adequate baseband signal applied to the transistors’ input also serves to enhance the device and circuit performance reproducibility since the impact of traps is diminished. Quadrature PSK is also achieved by combining two GFET-based multifunctional circuits. This device circuit co-design proposal intends to boost the heterogeneous implementation of graphene devices with incumbent technologies into a single chip: the baseband pulses can be generated with CMOS technology as a front end of line and the multifunctional GFET-based circuits as a back end of line. Full article
(This article belongs to the Special Issue Selected Papers from XXXVIII Conference on Design of Circuits and Integrated Systems—DCIS 2023)
►▼ Show Figures

Figure 1

14 pages, 1233 KiB  
Article
Optimizing Artificial Neural Networks to Minimize Arithmetic Errors in Stochastic Computing Implementations
by Christiam F. Frasser, Alejandro Morán, Vincent Canals, Joan Font, Eugeni Isern, Miquel Roca and Josep L. Rosselló
Electronics 2024, 13(14), 2846; https://doi.org/10.3390/electronics13142846 - 19 Jul 2024
Viewed by 772
Abstract
Deploying modern neural networks on resource-constrained edge devices necessitates a series of optimizations to ready them for production. These optimizations typically involve pruning, quantization, and fixed-point conversion to compress the model size and enhance energy efficiency. While these optimizations are generally adequate for [...] Read more.
Deploying modern neural networks on resource-constrained edge devices necessitates a series of optimizations to ready them for production. These optimizations typically involve pruning, quantization, and fixed-point conversion to compress the model size and enhance energy efficiency. While these optimizations are generally adequate for most edge devices, there exists potential for further improving the energy efficiency by leveraging special-purpose hardware and unconventional computing paradigms. In this study, we explore stochastic computing neural networks and their impact on quantization and overall performance concerning weight distributions. When arithmetic operations such as addition and multiplication are executed by stochastic computing hardware, the arithmetic error may significantly increase, leading to a diminished overall accuracy. To bridge the accuracy gap between a fixed-point model and its stochastic computing implementation, we propose a novel approximate arithmetic-aware training method. We validate the efficacy of our approach by implementing the LeNet-5 convolutional neural network on an FPGA. Our experimental results reveal a negligible accuracy degradation of merely 0.01% compared with the floating-point counterpart, while achieving a substantial 27× speedup and 33× enhancement in energy efficiency compared with other FPGA implementations. Additionally, the proposed method enhances the likelihood of selecting optimal LFSR seeds for stochastic computing systems. Full article
(This article belongs to the Special Issue Selected Papers from XXXVIII Conference on Design of Circuits and Integrated Systems—DCIS 2023)
►▼ Show Figures

Figure 1

21 pages, 935 KiB  
Article
Enabling Efficient On-Edge Spiking Neural Network Acceleration with Highly Flexible FPGA Architectures
by Samuel López-Asunción and Pablo Ituero
Electronics 2024, 13(6), 1074; https://doi.org/10.3390/electronics13061074 - 14 Mar 2024
Cited by 1 | Viewed by 1416
Abstract
Spiking neural networks (SNNs) promise to perform tasks currently performed by classical artificial neural networks (ANNs) faster, in smaller footprints, and using less energy. Neuromorphic processors are set out to revolutionize computing at a large scale, but the move to edge-computing applications calls [...] Read more.
Spiking neural networks (SNNs) promise to perform tasks currently performed by classical artificial neural networks (ANNs) faster, in smaller footprints, and using less energy. Neuromorphic processors are set out to revolutionize computing at a large scale, but the move to edge-computing applications calls for finely-tuned custom implementations to keep pushing towards more efficient systems. To that end, we examined the architectural design space for executing spiking neuron models on FPGA platforms, focusing on achieving ultra-low area and power consumption. This work presents an efficient clock-driven spiking neuron architecture used for the implementation of both fully-connected cores and 2D convolutional cores, which rely on deep pipelines for synaptic processing and distributed memory for weight and neuron states. With them, we developed an accelerator for an SNN version of the LeNet-5 network trained on the MNIST dataset. At around 5.5 slices/neuron and only 348 mW, it is able to use 33% less area and four times less power per neuron as current state-of-the-art implementations while keeping low simulation step times. Full article
(This article belongs to the Special Issue Selected Papers from XXXVIII Conference on Design of Circuits and Integrated Systems—DCIS 2023)
►▼ Show Figures

Figure 1

Show export options expand_more Show export options expand_less
Select all
Export citation of selected articles as:
 
Displaying articles 1-3
Back to TopTop