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Electronics
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Digital Hardware Architectures: Systems and Applications
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Digital Hardware Architectures: Systems and Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (1 May 2023) | Viewed by 11194

Special Issue Editors

Prof. Dr. Daniel Ziener

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Guest Editor
Computer Architecture and Embedded Systems, Department of Computer Science and Automation, Technische Universität Ilmenau, Helmholtzplatz 5, Zusebau, 98693 Ilmenau, Germany
Interests: computer architecture; embedded systems; reconfigurable computing; FPGA accelerators; secure embedded systems; reliable and fault tolerant embedded systems
Dr. Nikolaos Alachiotis

E-Mail Website
Guest Editor
Computer Architecture for Embedded Systems (CAES), Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, 7522 NB Enschede, The Netherlands
Interests: computer architectures; reconfigurable computing; FPGA accelerators; bioinformatics
Dr. Hasan Irmak

E-Mail Website
Guest Editor
Computer Architecture for Embedded Systems, Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, 7522 NB Enschede, The Netherlands
Interests: signal processing; video processing; image processing; artificial intelligence; embedded systems; reconfigurable computing; FPGA accelerators

Special Issue Information

Dear Colleagues,

The efficient deployment of applications with digital hardware architectures is a challenging task in embedded system design. Computational requirements, power and resource budgets, and other system specifications play a critical role in the decision of the hardware platform and the system architecture. This Special Issue aims to present the latest advances in applications in embedded systems that benefit from new architectures of different hardware platforms, such as graphics processing units (GPUs), field-programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs). Relevant applications include (but are not limited to):

  • Signal, video, and image processing;
  • Artificial intelligence;
  • Bioinformatics;
  • High-performance computing;
  • Data processing.

Prof. Dr. Daniel Ziener
Dr. Nikolaos Alachiotis
Dr. Hasan Irmak
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Hardware Architectures
  • Software Architectures
  • FPGA
  • GPU
  • ASIC
  • DSP
  • CPU

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Published Papers (4 papers)

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Research

15 pages, 1169 KiB  
Article
Fully Parallel Proposal of Naive Bayes on FPGA
by Wysterlânya K. P. Barros, Matheus T. Barbosa, Leonardo A. Dias and Marcelo A. C. Fernandes
Electronics 2022, 11(16), 2565; https://doi.org/10.3390/electronics11162565 - 17 Aug 2022
Viewed by 2266
Abstract
This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gate [...] Read more.
This work proposes a fully parallel hardware architecture of the Naive Bayes classifier to obtain high-speed processing and low energy consumption. The details of the proposed architecture are described throughout this work. Besides, a fixed-point implementation on a Stratix V Field Programmable Gate Array (FPGA) is presented and evaluated regarding the hardware area occupation, processing time (throughput), and dynamic power consumption. In addition, a comparative design analysis was carried out with state-of-the-art works, showing that the proposed implementation achieved a speedup of up to 104× and power savings of up to 107×-times while also reducing the hardware occupancy by up to 102×-times fewer logic cells. Full article
(This article belongs to the Special Issue Digital Hardware Architectures: Systems and Applications)
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10 pages, 998 KiB  
Article
A Configurable IP Core for Calculating the Integer Square Root for Serial and Parallel Implementations in FPGA
by Vladimir Matyukha, Sergey Voloshchuk and Sergey Mosin
Electronics 2022, 11(15), 2335; https://doi.org/10.3390/electronics11152335 - 27 Jul 2022
Cited by 1 | Viewed by 2011
Abstract
The development of digital technologies is in many ways associated with an improvement of integrated technologies, microelectronic components, and the capabilities of hardware acceleration of the most computationally complex operations. Field-programmable gate arrays (FPGAs) are actively used for prototyping or the small-scale production [...] Read more.
The development of digital technologies is in many ways associated with an improvement of integrated technologies, microelectronic components, and the capabilities of hardware acceleration of the most computationally complex operations. Field-programmable gate arrays (FPGAs) are actively used for prototyping or the small-scale production of special purpose digital signal processing (DSP) devices. The implementation of DSP algorithms is variative in nature and affects important indicators of a produced device, such as the accuracy of the numerical solution, performance, structural/functional complexity, etc. The architectural features of the FPGA can be used for choosing an effective DSP algorithm in the form of solving the multicriteria discrete optimization problem. This paper analyzes and selects an effective algorithm for calculating the integer square root, which is one of the most frequently used digital signal processing operations. A behavioral model based on a non-restoring algorithm is presented. The SystemVerilog description of the module for calculating the square root, presented in the form of a universal configurable IP core, has been developed and synthesized. The configuration allows one to change the width of the input data bus and select the serial or parallel processing mode for scalar or vector data. The results of testing and comparison of the obtained characteristics with the corresponding Xilinx Cordic IP core are presented. The field test of the proposed IP core implemented in the Xilinx FPGA SOC xc7z045ffg900-2 has demonstrated the gain in the maximum system frequency at 174 MHz in the sequential mode with a 48-bit input bus and 169 MHz in the pipelined mode at a reduction of both the structural complexity and the number of used FPGA internal resources in comparison with the Xilinx Cordic IP core. Full article
(This article belongs to the Special Issue Digital Hardware Architectures: Systems and Applications)
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13 pages, 3169 KiB  
Article
Structured Design of Complex Hardware Microarchitectures Based on Explicit Generic Implementations of Custom Microarchitectural Mechanisms
by Alexander Antonov
Electronics 2022, 11(7), 1055; https://doi.org/10.3390/electronics11071055 - 28 Mar 2022
Viewed by 2649
Abstract
In typical computer system design flows, hardware microarchitecture is commonly considered a dynamically developing domain, where abstract mechanisms remain mostly in conceptual form and exhibit poor source code reuse in designs. However, many important basic mechanisms appear to be pervasive and persistent. This [...] Read more.
In typical computer system design flows, hardware microarchitecture is commonly considered a dynamically developing domain, where abstract mechanisms remain mostly in conceptual form and exhibit poor source code reuse in designs. However, many important basic mechanisms appear to be pervasive and persistent. This paper summarizes original efforts to propose generic implementations of microarchitectural mechanisms for in-order and out-of-order microarchitectures and various demo designs based on these implementations. The basic EDA components proposed for this design approach are “Kernel IP (KIP) cores”—open-source collection of programmable hardware generators inferred from microarchitectural templates. KIP cores feasibility for their role is demonstrated from the viewpoints of abstract representation of microarchitectural mechanisms, support of functional differentiation of designs, and generic optimizations. Experimental designing according to this approach has shown useful separation of concerns in hardware design activities, lower design effort, and increased formalization and code reuse. Full article
(This article belongs to the Special Issue Digital Hardware Architectures: Systems and Applications)
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19 pages, 971 KiB  
Article
Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications
by Rui Chen and Bing Li
Electronics 2022, 11(6), 935; https://doi.org/10.3390/electronics11060935 - 17 Mar 2022
Cited by 4 | Viewed by 2939
Abstract
The widespread use of the internet of things (IoT) is due to the value of the data collected by IoT devices. These IoT devices generate, process, and exchange large amounts of safety-critical or privacy-sensitive data. Before transmission, the data should be protected against [...] Read more.
The widespread use of the internet of things (IoT) is due to the value of the data collected by IoT devices. These IoT devices generate, process, and exchange large amounts of safety-critical or privacy-sensitive data. Before transmission, the data should be protected against information leakage and data stealing. Deploying authenticated encryption with additional data (AEAD) algorithms on IoT devices ensures data confidentiality and integrity. However, AEAD algorithms are computationally intensive, while IoT devices are resource constrained or even battery powered. Therefore, a low-cost, low-power, and high-efficiency method of implementing an AEAD algorithm into resource-constrained IoT devices is required. The SM4-CCM algorithm, introduced in RFC 8998, is selected as the AEAD algorithm to address this problem. Algorithms similar to SM4-CCM (e.g., SM4 and AES-CCM) provide many architectural design references, but it is challenging to decide which architecture is the most suitable for SM4-CCM. In order to find the most efficient SM4-CCM hardware architecture, a design space exploration method is proposed. Firstly, the SM4-CCM algorithm is divided into five layers, and three candidate architectures are provided for each layer. Secondly, 63 design schemes for SM4-CCM are constructed by combining candidate architectures from each layer. Finally, a batch number of comparisons and analyses of experimental results are used to identify the most efficient one. Under TSMC 90 nm technology, the experimental results of the identified scheme show that the throughput, power consumption, and area achieve 199.99 Mbps, 1.625 mW, and 14.6 K gates, respectively. As a proof of concept, implementing this scheme on an FPGA board is also presented. Full article
(This article belongs to the Special Issue Digital Hardware Architectures: Systems and Applications)
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