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Electronics
Special Issues
Hardware and Architecture Ⅱ
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Hardware and Architecture Ⅱ

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (15 October 2020) | Viewed by 23198

Special Issue Editor

Prof. Dr. Michael Hüebner

E-Mail Website
Guest Editor
Computer Engineering, Brandenburg University of Technology Cottbus-Senftenberg, Universitätsplatz 1, 01968 Senftenberg, Germany
Interests: reconfigurable computing; system on chip; embedded systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Novel trends in cyber-physical systems, the Internet of things, neuronal networks, and machine learning require new hardware and architecture. The goal is to further reduce energy consumption while simultaneously increasing performance. This Special Issue will cover novel trends, research, and the development of hardware and architecture, and will contribute to the community with different views and solutions.

Prof. Dr. Michael Hüebner
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Embedded systems
  • Low power
  • Reconfigurable computing

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Published Papers (3 papers)

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Research

14 pages, 5053 KiB  
Article
Efficient Systolic-Array Redundancy Architecture for Offline/Online Repair
by Keewon Cho, Ingeol Lee, Hyeonchan Lim and Sungho Kang
Electronics 2020, 9(2), 338; https://doi.org/10.3390/electronics9020338 - 15 Feb 2020
Cited by 5 | Viewed by 10198
Abstract
Neural-network computing has revolutionized the field of machine learning. The systolic-array architecture is a widely used architecture for neural-network computing acceleration that was adopted by Google in its Tensor Processing Unit (TPU). To ensure the correct operation of the neural network, the reliability [...] Read more.
Neural-network computing has revolutionized the field of machine learning. The systolic-array architecture is a widely used architecture for neural-network computing acceleration that was adopted by Google in its Tensor Processing Unit (TPU). To ensure the correct operation of the neural network, the reliability of the systolic-array architecture should be guaranteed. This paper proposes an efficient systolic-array redundancy architecture that is based on systolic-array partitioning and rearranging connections of the systolic-array elements. The proposed architecture allows both offline and online repair with an extended redundancy architecture and programmable fuses and can ensure reliability even in an online situation, for which the previous fault-tolerant schemes have not been considered. Full article
(This article belongs to the Special Issue Hardware and Architecture Ⅱ)
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19 pages, 5075 KiB  
Article
CENNA: Cost-Effective Neural Network Accelerator
by Sang-Soo Park and Ki-Seok Chung
Electronics 2020, 9(1), 134; https://doi.org/10.3390/electronics9010134 - 10 Jan 2020
Cited by 10 | Viewed by 5482
Abstract
Convolutional neural networks (CNNs) are widely adopted in various applications. State-of-the-art CNN models deliver excellent classification performance, but they require a large amount of computation and data exchange because they typically employ many processing layers. Among these processing layers, convolution layers, which carry [...] Read more.
Convolutional neural networks (CNNs) are widely adopted in various applications. State-of-the-art CNN models deliver excellent classification performance, but they require a large amount of computation and data exchange because they typically employ many processing layers. Among these processing layers, convolution layers, which carry out many multiplications and additions, account for a major portion of computation and memory access. Therefore, reducing the amount of computation and memory access is the key for high-performance CNNs. In this study, we propose a cost-effective neural network accelerator, named CENNA, whose hardware cost is reduced by employing a cost-centric matrix multiplication that employs both Strassen’s multiplication and a naïve multiplication. Furthermore, the convolution method using the proposed matrix multiplication can minimize data movement by reusing both the feature map and the convolution kernel without any additional control logic. In terms of throughput, power consumption, and silicon area, the efficiency of CENNA is up to 88 times higher than that of conventional designs for the CNN inference. Full article
(This article belongs to the Special Issue Hardware and Architecture Ⅱ)
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12 pages, 7500 KiB  
Article
Area-Efficient Pipelined FFT Processor for Zero-Padded Signals
by Yongchul Jung, Jaechan Cho, Seongjoo Lee and Yunho Jung
Electronics 2019, 8(12), 1397; https://doi.org/10.3390/electronics8121397 - 22 Nov 2019
Cited by 6 | Viewed by 6954
Abstract
This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most [...] Read more.
This paper proposes an area-efficient fast Fourier transform (FFT) processor for zero-padded signals based on the radix-2 2 and the radix-2 3 single-path delay feedback pipeline architectures. The delay elements for aligning the data in the pipeline stage are one of the most complex units and that of stage 1 is the biggest. By exploiting the fact that the input data sequence is zero-padded and that the twiddle factor multiplication in stage 1 is trivial, the proposed FFT processor can dramatically reduce the required number of delay elements. Moreover, the 256-point FFT processors were designed using hardware description language (HDL) and were synthesized to gate-level circuits using a standard cell library for 65 nm CMOS process. The proposed architecture results in a logic gate count of 40,396, which can be efficient and suitable for zero-padded FFT processors. Full article
(This article belongs to the Special Issue Hardware and Architecture Ⅱ)
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