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Electronics
Special Issues
Test and Monitoring of Aging Effects in Electronics
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Test and Monitoring of Aging Effects in Electronics

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Systems & Control Engineering".

Deadline for manuscript submissions: closed (28 February 2022) | Viewed by 6936

Special Issue Editors

Dr. Riccardo Cantoro

E-Mail Website
Guest Editor
Department of Control and Computer Engineering, Politecnico di Torino, Torino, Italy
Interests: functional test; software-based self-test; data analysis; machine learning
Dr. Michele Portolan

E-Mail Website
Guest Editor
Grenoble INP, 46 Avenue Félix Viallet, 38031 Grenoble, France
Interests: design-for-test; EDA tools; reliable systems; standards

Special Issue Information

Dear Colleagues,

Modern electronic systems are characterized by a shorter lifetime compared to more mature semiconductor technologies. Manufacturing defects strongly contribute to effects such as aging and wear-out and can irremediably jeopardize the mission of safety-critical applications if not detected and handled in time. While effective early failure screen-out during manufacturing is of course mandatory, the need for hardware- or software-triggered safety mechanisms for continuous in-field testing is steadily growing. New techniques are thus needed to support circuit designers, so that the design can be suitably hardened to extend its lifetime without sacrificing performance or cost. Furthermore, there is a need for early warning methods, to allow the user to take proper actions when a circuit is close to its wear-out but before any failure actually occurs.

The purpose of this Special Issue is to let academic and industrial researchers propose innovative solutions for enhancing state-of-the-art in the domains of testing and aging monitoring. The potential topics of the Special Issue include but are not limited to:

  • Analog and digital modules to support aging monitoring and fault diagnosis;
  • Burn-in enhancements;
  • Machine learning and Artificial Intelligence techniques for aging characterization and early failure detection;
  • Design, validation, and test of monitoring and DfT infrastructure;
  • Hardware/software or hybrid solutions for in-field test and diagnosis of safety-critical systems;
  • Aging-oriented fault modeling, and test generation;
  • Industrial and academic case studies.

Dr. Riccardo Cantoro
Dr. Michele Portolan
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • aging
  • reconfigurable systems
  • safety-critical systems
  • monitors
  • fault tolerance
  • system level test
  • fault modeling
  • design-for-test

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Published Papers (2 papers)

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Research

13 pages, 4684 KiB  
Article
Test for Reliability for Mission Critical Applications
by Mauro Pipponzi and Alberto Sangiovanni-Vincentelli
Electronics 2021, 10(16), 1985; https://doi.org/10.3390/electronics10161985 - 17 Aug 2021
Viewed by 2101
Abstract
Test for Reliability is a test flow where an Integrated Circuit (IC) device is continuously stressed under several corner conditions that can be dynamically adapted based on the real-time observation of the critical signals of the device during the evolution of the test. [...] Read more.
Test for Reliability is a test flow where an Integrated Circuit (IC) device is continuously stressed under several corner conditions that can be dynamically adapted based on the real-time observation of the critical signals of the device during the evolution of the test. We present our approach for a successful Test-for-Reliability flow, going beyond the objectives of the traditional reliability approach, and covering the entire process from design to failure analysis. Full article
(This article belongs to the Special Issue Test and Monitoring of Aging Effects in Electronics)
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16 pages, 2794 KiB  
Article
Error-Tolerant Reconfigurable VDD 10T SRAM Architecture for IoT Applications
by Neha Gupta, Ambika Prasad Shah, Sajid Khan, Santosh Kumar Vishvakarma, Michael Waltl and Patrick Girard
Electronics 2021, 10(14), 1718; https://doi.org/10.3390/electronics10141718 - 17 Jul 2021
Cited by 6 | Viewed by 3797
Abstract
This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the [...] Read more.
This paper proposes an error-tolerant reconfigurable VDD (R-VDD) scaled SRAM architecture, which significantly reduces the read and hold power using the supply voltage scaling technique. The data-dependent low-power 10T (D2LP10T) SRAM cell is used for the R-VDD scaled architecture with the improved stability and lower power consumption. The R-VDD scaled SRAM architecture is developed to avoid unessential read and hold power using VDD scaling. In this work, the cells are implemented and analyzed considering a technologically relevant 65 nm CMOS node. We analyze the failure probability during read, write, and hold mode, which shows that the proposed D2LP10T cell exhibits the lowest failure rate compared to other existing cells. Furthermore, the D2LP10T cell design offers 1.66×, 4.0×, and 1.15× higher write, read, and hold stability, respectively, as compared to the 6T cell. Moreover, leakage power, write power-delay-product (PDP), and read PDP has been reduced by 89.96%, 80.52%, and 59.80%, respectively, compared to the 6T SRAM cell at 0.4 V supply voltage. The functional improvement becomes even more apparent when the quality factor (QF) is evaluated, which is 458× higher for the proposed design than the 6T SRAM cell at 0.4 V supply voltage. A significant improvement of power dissipation, i.e., 46.07% and 74.55%, can also be observed for the R-VDD scaled architecture compared to the conventional array for the respective read and hold operation at 0.4 V supply voltage. Full article
(This article belongs to the Special Issue Test and Monitoring of Aging Effects in Electronics)
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