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Electronics
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Novel Architectures, Tools and Applications for Reconfigurable FPGA-Based Embedded Systems
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Novel Architectures, Tools and Applications for Reconfigurable FPGA-Based Embedded Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (15 June 2021) | Viewed by 6372

Special Issue Editors

Prof. Dr. Andres Otero

E-Mail Website
Guest Editor
Centro de Electrónica Industrial, Universidad Politécnica de Madrid, 28006 Madrid, Spain
Interests: embedded-system design; 3D vision; FPGA-based reconfigurable systems; machine learning in the edge
Special Issues, Collections and Topics in MDPI journals
Prof. Dr. Eduardo de la Torre

E-Mail Website
Guest Editor
Centro de Electrónica Industrial, Universidad Politécnica de Madrid, 28006 Madrid, Spain
Interests: FPGAs; reconfigurable systems; evolvable hardware; sensor networks; digital signal processing

Special Issue Information

Dear Colleagues,

Reconfigurable computing is nowadays a reality that is already being exploited in both research and industrial scenarios, which benefit from the combination of flexibility and high performance provided by this technology. Such a combination makes reconfigurability an enabling technology for self-adaptation in multiple domains, as well as the technology substrate on which evolvable and approximate circuits may operate. Design flows for reconfigurable computing, which were previously only available in academic works, are now being integrated as part of commercial tools. However, multiple research opportunities can still be identified.

In this Special Issue, we look forward to receiving original contributions providing novel architectures to exploit all of the possibilities offered by embedded reconfigurable devices. These novel architectures require custom design flows and supporting tools to extend the options already incorporated into commercial solutions. Application papers showing implementations and deployments in different scenarios are very welcome as well, with a particular accent on reconfigurable systems working under safety-critical requirements, such as aerospace or automotive.

Prof. Dr. Andres Otero
Prof. Dr. Eduardo de la Torre
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • FPGA
  • reconfigurable computing
  • self-adaptation
  • design tools
  • architectures
  • evolvable hardware
  • approximate computing

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Published Papers (2 papers)

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22 pages, 2741 KiB  
Article
Gaussian Belief Propagation on a Field-Programmable Gate Array for Solving Linear Equation Systems
by Thomas Wiedemann and Julian Spengler
Electronics 2021, 10(14), 1695; https://doi.org/10.3390/electronics10141695 - 15 Jul 2021
Viewed by 1846
Abstract
Solving Linear Equation System (LESs) is a common problem in numerous fields of science. Even though the problem is well studied and powerful solvers are available nowadays, solving LES is still a bottleneck in many numerical applications concerning computation time. This issue especially [...] Read more.
Solving Linear Equation System (LESs) is a common problem in numerous fields of science. Even though the problem is well studied and powerful solvers are available nowadays, solving LES is still a bottleneck in many numerical applications concerning computation time. This issue especially pertains to applications in mobile robotics constrained by real-time requirements, where on-top power consumption and weight play an important role. This paper provides a general framework to approximately solve large LESs by Gaussian Belief Propagation (GaBP), which is extremely suitable for parallelization and implementation in hardware on a Field-Programmable Gate Array (FPGA). We derive the simple update rules of the Message Passing Algorithm for GaBP and show how to implement the approach efficiently on a System on a Programmable Chip (SoPC). In particular, multiple dedicated co-processors take care of recurring computations in GaBP. Exploiting multiple Direct Memory Access (DMA) controllers in scatter-gather mode and available arithmetic logic slices for numerical calculations accelerate the algorithm. Presented evaluations demonstrate that the approach does not only provide an accurate approximative solution of the LES. It also outperforms traditional solvers with respect to computation time for certain LESs. Full article
(This article belongs to the Special Issue Novel Architectures, Tools and Applications for Reconfigurable FPGA-Based Embedded Systems)
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15 pages, 2367 KiB  
Article
Design Space Exploration for YOLO Neural Network Accelerator
by Hongmin Huang, Zihao Liu, Taosheng Chen, Xianghong Hu, Qiming Zhang and Xiaoming Xiong
Electronics 2020, 9(11), 1921; https://doi.org/10.3390/electronics9111921 - 16 Nov 2020
Cited by 15 | Viewed by 3810
Abstract
The You Only Look Once (YOLO) neural network has great advantages and extensive applications in computer vision. The convolutional layers are the most important part of the neural network and take up most of the computation time. Improving the efficiency of the convolution [...] Read more.
The You Only Look Once (YOLO) neural network has great advantages and extensive applications in computer vision. The convolutional layers are the most important part of the neural network and take up most of the computation time. Improving the efficiency of the convolution operations can greatly increase the speed of the neural network. Field programmable gate arrays (FPGAs) have been widely used in accelerators for convolutional neural networks (CNNs) thanks to their configurability and parallel computing. This paper proposes a design space exploration for the YOLO neural network based on FPGA. A data block transmission strategy is proposed and a multiply and accumulate (MAC) design, which consists of two 14 × 14 processing element (PE) matrices, is designed. The PE matrices are configurable for different CNNs according to the given required functions. In order to take full advantage of the limited logical resources and the memory bandwidth on the given FPGA device and to simultaneously achieve the best performance, an improved roofline model is used to evaluate the hardware design to balance the computing throughput and the memory bandwidth requirement. The accelerator achieves 41.99 giga operations per second (GOPS) and consumes 7.50 W running at the frequency of 100 MHz on the Xilinx ZC706 board. Full article
(This article belongs to the Special Issue Novel Architectures, Tools and Applications for Reconfigurable FPGA-Based Embedded Systems)
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