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A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Electronic Sensors".

Deadline for manuscript submissions: closed (30 April 2023) | Viewed by 10817

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Special Issue Editor

Prof. Dr. Kang-Yoon Lee

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Guest Editor

School of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon 16419, Korea
Interests: analog IC; power IC; RF IC; AI IC
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Today, there are numerous applications that use various sensors in manufacturing, transportation, agriculture, environment, healthcare, etc. Integrated circuits and systems play a key role in the design and development of sensors. The advances of integrated circuit technology enable the implementation of high-performance and small-sized sensors.

This Special Issue invites contributions on more recent developments and advances of integrated circuit design and sensing applications including biosensors, temperature sensors, pressure sensors, touch sensors, etc. It covers sensor devices, signal conditioning circuits, calibration, and AI-based processing techniques from multiple sensor data.

Prof. Dr. Kang-Yoon Lee
Guest Editor

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Keywords

sensors
analog front-end
signal processing
signal conditioning
calibration

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Published Papers (5 papers)

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14 pages, 3562 KiB

Open AccessArticle

A Comprehensive Methodology for Optimizing Read-Out Timing and Reference DAC Offset in High Frame Rate Image Sensing Systems

by Jaehoon Jun

Sensors 2023, 23(16), 7048; https://doi.org/10.3390/s23167048 - 9 Aug 2023

Cited by 2 | Viewed by 1770 | Correction

Abstract

This paper presents a comprehensive timing optimization methodology for power-efficient high-resolution image sensors with column-parallel single-slope analog-to-digital converters (ADCs). The aim of the method is to optimize the read-out timing for each period in the image sensor’s operation, while considering various factors such as ADC decision time, slew rate, and settling time. By adjusting the ramp reference offset and optimizing the amplifier bandwidth of the comparator, the proposed methodology minimizes the power consumption of the amplifier array, which is one of the most power-hungry circuits in the system, while maintaining a small color linearity error and ensuring optimal performance. To demonstrate the effectiveness of the proposed method, a power-efficient 108 MP 3-D stacked CMOS image sensor with a 10-bit column-parallel single-slope ADC array was implemented and verified. The image sensor achieved a random noise of 1.4 e⁻rms, a column fixed-pattern noise of 66 ppm at an analog gain of 16, and a remarkable figure-of-merit (FoM) of 0.71 e⁻·nJ. This timing optimization methodology enhances energy efficiency in high-resolution image sensors, enabling higher frame rates and improved system performance. It could be adapted for various imaging applications requiring optimized performance and reduced power consumption, making it a valuable tool for designers aiming to achieve optimal performance in power-sensitive applications. Full article

(This article belongs to the Special Issue Integrated Circuit Design and Sensing Applications)

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15 pages, 2584 KiB

Open AccessArticle

Wideband SiGe-HBT Low-Noise Amplifier with Resistive Feedback and Shunt Peaking

by Ickhyun Song, Gyungtae Ryu, Seung Hwan Jung, John D. Cressler and Moon-Kyu Cho

Sensors 2023, 23(15), 6745; https://doi.org/10.3390/s23156745 - 28 Jul 2023

Cited by 4 | Viewed by 2995

Abstract

In this work, the design of a wideband low-noise amplifier (LNA) using a resistive feedback network is proposed for potential multi-band sensing, communication, and radar applications. For achieving wide operational bandwidth and flat in-band characteristics simultaneously, the proposed LNA employs a variety of circuit design techniques, including a voltage–current (shunt–shunt) negative feedback configuration, inductive emitter degeneration, a main branch with an added cascode stage, and the shunt-peaking technique. The use of a feedback network and emitter degeneration provides broadened transfer characteristics for multi-octave coverage and a real impedance for input matching, respectively. In addition, the cascode stage pushes the band-limiting low-frequency pole, due to the Miller capacitance, to a higher frequency. Lastly, the shunt-peaking approach is optimized for the compensation of a gain reduction at higher frequency bands. The wideband LNA proposed in this study is fabricated using a commercial 0.13 μm silicon-germanium (SiGe) BiCMOS process, employing SiGe heterojunction bipolar transistors (HBTs) as the circuit’s core active elements in the main branch. The measurement results show an operational bandwidth of 2.0–29.2 GHz, a noise figure of 4.16 dB (below 26.5 GHz, which was the measurement limit), and a total power consumption of 23.1 mW under a supply voltage of 3.3 V. Regarding the nonlinearity associated with large-signal behavior, the proposed LNA exhibits an input 1-dB compression (IP1dB) point of −5.42 dBm at 12 GHz. These performance numbers confirm the strong viability of the proposed approach in comparison with other state-of-the-art designs. Full article

(This article belongs to the Special Issue Integrated Circuit Design and Sensing Applications)

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17 pages, 6914 KiB

Open AccessArticle

An MMIC LNA for Millimeter-Wave Radar and 5G Applications with GaN-on-SiC Technology

by Chaoyu Huang, Zhihao Zhang, Xinjie Wang, Hailiang Liu and Gary Zhang

Sensors 2023, 23(14), 6611; https://doi.org/10.3390/s23146611 - 22 Jul 2023

Cited by 5 | Viewed by 2958

Abstract

This paper presents a monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) that is compatible with n257 (26.5–29.5 GHz) and n258 (24.25–27.5 GHz) frequency bands for fifth-generation mobile communications system (5G) and millimeter-wave radar. The total circuit size of the LNA is 2.5 × 1.5 mm2. To guarantee a trade-off between noise figure (NF) and small signal gain, the transmission lines are connected to the source of gallium nitride (GaN)-on-SiC high electron mobility transistors (HEMT) by analyzing the nonlinear small signal equivalent circuit. A series of stability enhancement measures including source degeneration, an RC series network, and RF choke are put forward to enhance the stability of designed LNA. The designed GaN-based MMIC LNA adopts hybrid-matching networks (MNs) with co-design strategy to realize low NF and broadband characteristics across 5G n257 and n258 frequency band. Due to the different priorities of these hybrid-MNs, distinguished design strategies are employed to benefit small signal gain, input-output return loss, and NF performance. In order to meet the testing conditions of MMIC, an impeccable system for measuring small has been built to ensure the accuracy of the measured results. According to the measured results for small signal, the three-stage MMIC LNA has a linear gain of 18.2–20.3 dB and an NF of 2.5–3.1 dB with an input–output return loss better than 10 dB in the whole n257 and n258 frequency bands. Full article

(This article belongs to the Special Issue Integrated Circuit Design and Sensing Applications)

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19 pages, 7269 KiB

Open AccessArticle

Test Structure Design for Defect Detection during Active Thermal Cycling

by Ciprian Florea, Dan Simon, Adrian Bojiță, Marius Purcar, Cristian Boianceanu and Vasile Țopa

Sensors 2022, 22(19), 7223; https://doi.org/10.3390/s22197223 - 23 Sep 2022

Viewed by 1751

Abstract

Integrated power ICs acting as smart power switches for automotive or industrial applications are often subjected to active thermal cycling. Consequently, they undergo significant self-heating and are prone to various failure mechanisms related to the electro-thermo-mechanical phenomena that take place in the device metallization. In this article a test structure consisting of a lateral DMOS transistor equipped with several integrated sensors is proposed for metallization fatigue assessment. The design of the test structure is presented in detail, alongside with design considerations drawn from the literature and from simulation results. The testing procedure is then described, and experimental results are discussed. The experimental data provided by the integrated sensors correlated with the electro-thermal simulation results indicate the emergence of a failure mechanism and this is later confirmed by failure analysis. Conclusions are further drawn regarding the feasibility of using the proposed integrated sensors for monitoring defects in power ICs. Full article

(This article belongs to the Special Issue Integrated Circuit Design and Sensing Applications)

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