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Integrated Circuits and CMOS Sensors
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Integrated Circuits and CMOS Sensors

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Physical Sensors".

Deadline for manuscript submissions: closed (20 December 2023) | Viewed by 9611

Special Issue Editor

Prof. Dr. Vamsy P. Chodavarapu

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, University of Dayton, 300 College Park, Dayton, OH 45469, USA
Interests: CMOS microsystems; RF/analog/digital circuits; neuro-/biomedical- instrumentation and wearables; bio-/neuro-/RF- MEMS; biological-/chemical- sensing; nano-/bio- materials
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

The concept of “More than Moore” technologies or, in other words, the diversification of CMOS-based technologies, has gained significant attention from research groups and companies worldwide looking to create next-generation products and services. The heterogeneous and hybrid integration of CMOS with sensors, actuators, power, biology, and medicine is expected to create many new high-value products. Furthermore, the emerging application areas of hypersonics, space travel, and deep space exploration create new opportunities and challenges for CMOS-based systems.

The aim of this Special Issue is to gather original contributions or review papers from researchers actively engaged in developing new solutions in any area of integrated sensors and actuators technologically compatible with CMOS processes and CMOS solutions for emerging application areas of hypersonics, space travel, and exploration, as well as aerospace systems with extreme environment operation.

Prof. Dr. Vamsy P. Chodavarapu
Guest Editor

Manuscript Submission Information

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Keywords

  • CMOS sensor technologies: process, circuit, and architecture
  • front-end sensor electronics
  • extreme environment electronics
  • heterogeneous CMOS/sensor/actuator integration

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Published Papers (5 papers)

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Research

19 pages, 7287 KiB  
Article
Preliminary Characterization of an Active CMOS Pad Detector for Tracking and Dosimetry in HDR Brachytherapy
by Thi Ngoc Hang Bui, Matthew Large, Joel Poder, Joseph Bucci, Edoardo Bianco, Raffaele Aaron Giampaolo, Angelo Rivetti, Manuel Da Rocha Rolo, Zeljko Pastuovic, Thomas Corradino, Lucio Pancheri and Marco Petasecca
Sensors 2024, 24(2), 692; https://doi.org/10.3390/s24020692 - 22 Jan 2024
Viewed by 1424
Abstract
We assessed the accuracy of a prototype radiation detector with a built in CMOS amplifier for use in dosimetry for high dose rate brachytherapy. The detectors were fabricated on two substrates of epitaxial high resistivity silicon. The radiation detection performance of prototypes has [...] Read more.
We assessed the accuracy of a prototype radiation detector with a built in CMOS amplifier for use in dosimetry for high dose rate brachytherapy. The detectors were fabricated on two substrates of epitaxial high resistivity silicon. The radiation detection performance of prototypes has been tested by ion beam induced charge (IBIC) microscopy using a 5.5 MeV alpha particle microbeam. We also carried out the HDR Ir-192 radiation source tracking at different depths and angular dose dependence in a water equivalent phantom. The detectors show sensitivities spanning from (5.8 ± 0.021) × 10−8 to (3.6 ± 0.14) × 10−8 nC Gy−1 mCi−1 mm−2. The depth variation of the dose is within 5% with that calculated by TG-43. Higher discrepancies are recorded for 2 mm and 7 mm depths due to the scattering of secondary particles and the perturbation of the radiation field induced in the ceramic/golden package. Dwell positions and dwell time are reconstructed within ±1 mm and 20 ms, respectively. The prototype detectors provide an unprecedented sensitivity thanks to its monolithic amplification stage. Future investigation of this technology will include the optimisation of the packaging technique. Full article
(This article belongs to the Special Issue Integrated Circuits and CMOS Sensors)
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14 pages, 7553 KiB  
Article
Multi-Channel Gating Chip in 0.18 µm High-Voltage CMOS for Quantum Applications
by Christoph Ribisch, Michael Hofbauer, Seyed Saman Kohneh Poushi, Alexander Zimmer, Kerstin Schneider-Hornstein, Bernhard Goll and Horst Zimmermann
Sensors 2023, 23(24), 9644; https://doi.org/10.3390/s23249644 - 6 Dec 2023
Viewed by 1058
Abstract
A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including [...] Read more.
A gating circuit for a photonic quantum simulator is introduced. The gating circuit uses a large excess bias voltage of up to 9.9 V and an integrated single-photon avalanche diode (SPAD). Nine channels are monolithically implemented in an application-specific integrated circuit (ASIC) including nine SPADs using 0.18 µm high-voltage CMOS technology. The gating circuit achieves rise and fall times of 480 ps and 280 ps, respectively, and a minimum full-width-at-half-maximum pulse width of 1.26 ns. Thanks to a fast and sensitive comparator, a detection threshold for avalanche events of less than 100 mV is possible. The power consumption of all nine channels is about 250 mW in total. This gating chip is used to characterize the integrated SPADs. A photon detection probability of around 50% at 9.9 V excess bias and for a wavelength of 635 nm is found. Full article
(This article belongs to the Special Issue Integrated Circuits and CMOS Sensors)
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12 pages, 5428 KiB  
Communication
Design of Low-Noise CMOS Image Sensor Using a Hybrid-Correlated Multiple Sampling Technique
by Seung Ju Youn, Su Yeon Yun, Hoyeon Lee, Kwang Jin Park, Jiwon Kim and Soo Youn Kim
Sensors 2023, 23(23), 9551; https://doi.org/10.3390/s23239551 - 1 Dec 2023
Viewed by 1547
Abstract
We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the [...] Read more.
We present a 320 × 240 CMOS image sensor (CIS) using the proposed hybrid-correlated multiple sampling (HMS) technique with an adaptive dual-gain analog-to-digital converter (ADC). The proposed HMS improves the noise characteristics under low illumination by adjusting the ADC gain according to the incident light on the pixels. Depending on whether it is less than or greater than 1/4 of the full output voltage range from pixels, either correlated multiple sampling or conventional-correlated double sampling (CDS) is used with different slopes of the ramping signals. The proposed CIS achieves 11-bit resolution of the ADC using an up-down counter that controls the LSB depending on the ramping signals used. The sensor was fabricated using a 0.11 μm CIS process, and the total chip area was 2.55 mm × 4.3 mm. Compared to the conventional CDS, the measurement results showed that the maximum dark random noise was reduced by 26.7% with the proposed HMS, and the maximum figure of merit was improved by 49.1%. The total power consumption was 5.1 mW at 19 frames per second with analog, pixel, and digital supply voltages of 3.3 V, 3.3 V, and 1.5 V, respectively. Full article
(This article belongs to the Special Issue Integrated Circuits and CMOS Sensors)
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14 pages, 4171 KiB  
Article
A 21.4 pW Subthreshold Voltage Reference with 0.020 %/V Line Sensitivity Using DIBL Compensation
by Louis Colbach, Taekwang Jang and Youngwoo Ji
Sensors 2023, 23(4), 1862; https://doi.org/10.3390/s23041862 - 7 Feb 2023
Cited by 1 | Viewed by 2136
Abstract
This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the [...] Read more.
This paper presents an ultra-low-power voltage reference designed in 180 nm CMOS technology. To achieve near-zero line sensitivity, a two-transistor (2-T) voltage reference is biased with a current source to cancel the drain-induced barrier-lowering (DIBL) effect of the 2-T core, thus improving the line sensitivity. This compensation circuit achieves a Monte-Carlo-simulated line sensitivity of 0.035 %/V in a supply range of 0.6 to 1.8 V, while generating a reference voltage of 307.8 mV, with 21.4 pW power consumption. The simulated power supply rejection ratio (PSRR) is −54 dB at 100 Hz. It also achieves a temperature coefficient of 24.8 ppm/°C in a temperature range of −20 to 80 °C, with a projected area of 0.003 mm2. Full article
(This article belongs to the Special Issue Integrated Circuits and CMOS Sensors)
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10 pages, 2464 KiB  
Article
A Numerical Method of Aligning the Optical Stacks for All Pixels
by Jae-Hyeok Hwang and Yunkyung Kim
Sensors 2023, 23(2), 702; https://doi.org/10.3390/s23020702 - 8 Jan 2023
Viewed by 2539
Abstract
Reducing performance verification time is significant in product launch and production costs. This is especially true because aligning the optical stacks of off-axis pixels is a time-consuming task, but it is important to maintain sensitivity. In this paper, a numerical method to align [...] Read more.
Reducing performance verification time is significant in product launch and production costs. This is especially true because aligning the optical stacks of off-axis pixels is a time-consuming task, but it is important to maintain sensitivity. In this paper, a numerical method to align the optical stacks of off-axis pixels is suggested in order to reduce performance test time. The components of the numerical method are the optical stack height, refractive index, and chief ray angle in order to calculate the optical stacks’ optimal shift distance. The proposed method was investigated to confirm effectiveness by using optical simulation. The sub-micron backside illumination (BSI) pixels were simulated, having 2 × 2 microlens, quad-color filter array, and in-pixel deep trench isolation (DTI). Moreover, the proposed method was evaluated for various pixel pitches, microlens shapes, and CRAs. As a result, the optical stacks were optimized by using the numerical method and validated via optical simulation. Therefore, the proposed numerical method is expected to help reduce the time and cost. Full article
(This article belongs to the Special Issue Integrated Circuits and CMOS Sensors)
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